diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h b/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h index 3d1a41684d..7679461554 100644 --- a/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h +++ b/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h @@ -1,29 +1,6 @@ #ifndef __SN32F200_DEF_H #define __SN32F200_DEF_H -/*_____ I N C L U D E S ____________________________________________________*/ - -/*_____ D E F I N I T I O N S ______________________________________________*/ - -//Ture or False -// #define TRUE 0x1 -// #define FALSE 0x0 - -//Enable or Disable -#define ENABLE 0x1 -#define DISABLE 0x0 - -//Error Status -#define OK 0x0 -#define FAIL 0x1 - -//Null -// #define NULL 0 - -//Interrupt Flag Parsing Method -#define POLLING_METHOD 0x0 -#define INTERRUPT_METHOD 0x1 - //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; //SN32F230_PKG #define SN32F239 0 @@ -45,6 +22,12 @@ #define SN32F246B 2 #define SN32F2451B 3 +//SN32F240C_PKG +#define SN32F248C 0 +#define SN32F247C 1 +#define SN32F246C 2 +#define SN32F2451C 3 + //SN32F260_PKG #define SN32F268 0 #define SN32F267 1 @@ -52,6 +35,16 @@ #define SN32F2641 3 #define SN32F264 4 #define SN32F263 5 + +//SN32F280_PKG +#define SN32F289 0 +#define SN32F288 1 +#define SN32F287 2 + +//SN32F290_PKG +#define SN32F299 0 +#define SN32F298 1 +#define SN32F297 2 //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; /*_____ M A C R O S ________________________________________________________*/ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F240C.h b/os/common/ext/SONiX/SN32F2xx/SN32F240C.h new file mode 100644 index 0000000000..b1943a49a6 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F240C.h @@ -0,0 +1,3620 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F240C.h + * @brief CMSIS HeaderFile + * @version 1.01 + * @date 07. December 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 07.12.2023 18:31:37 + * from File 'SN32F240C.svd', + * last modified on Thursday, 07.12.2023 07:32:58 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F240C + * @{ + */ + + +#ifndef SN32F240C_H +#define SN32F240C_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================= SN32F240C Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 Noise Detection */ + USB_IRQn = 1, /*!< 1 USB */ + SPI0_IRQn = 6, /*!< 6 SPI0 */ + SPI1_IRQn = 7, /*!< 7 SPI1 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + I2C1_IRQn = 11, /*!< 11 I2C1 */ + UART0_IRQn = 12, /*!< 12 UART0 */ + UART1_IRQn = 13, /*!< 13 UART1 */ + UART2_IRQn = 14, /*!< 14 UART2 */ + CT16B0_IRQn = 15, /*!< 15 CT16B0 */ + CT16B1_IRQn = 16, /*!< 16 CT16B1 */ + ADC_IRQn = 24, /*!< 24 ADC */ + WDT_IRQn = 25, /*!< 25 Watchdog Timer */ + LVD_IRQn = 26, /*!< 26 Low Voltage Detection */ + P3_IRQn = 28, /*!< 28 GPIO3 */ + P2_IRQn = 29, /*!< 29 GPIO2 */ + P1_IRQn = 30, /*!< 30 GPIO1 */ + P0_IRQn = 31 /*!< 31 GPIO0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F240C System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 0 (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 31; + } ANBCTRL_b; + } ; + + union { + __IOM uint32_t PLLCTRL; /*!< (@ 0x00000004) Offset:0x04 PLL Control Register */ + + struct { + __IOM uint32_t MSEL : 3; /*!< [2..0] M value */ + uint32_t : 2; + __IOM uint32_t PSEL : 1; /*!< [5..5] P value */ + uint32_t : 9; + __IOM uint32_t PLLEN : 1; /*!< [15..15] PLL enable */ + uint32_t : 16; + } PLLCTRL_b; + } ; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 5; + __IM uint32_t PLLRDY : 1; /*!< [6..6] PLL ready flag */ + uint32_t : 25; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 3; /*!< [2..0] System clock source selection */ + uint32_t : 1; + __IM uint32_t SYSCLKST : 3; /*!< [6..4] System clock switch status */ + uint32_t : 25; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 3; /*!< [2..0] AHB clock source prescaler */ + uint32_t : 29; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 2; /*!< [1..0] LVD reset level */ + uint32_t : 2; + __IOM uint32_t LVDINTLVL : 2; /*!< [5..4] LVD interrupt level */ + uint32_t : 8; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + + union { + __IOM uint32_t IVTM; /*!< (@ 0x00000024) Offset:0x24 Interrupt Vector Table Mapping register */ + + struct { + __IOM uint32_t IVTM : 3; /*!< [2..0] Interrupt table mapping selection */ + uint32_t : 13; + __OM uint32_t IVTMKEY : 16; /*!< [31..16] IVTM register key */ + } IVTM_b; + } ; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_IE : 1; /*!< [1..1] NDT for VDD 5V interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_DET : 1; /*!< [1..1] Power noise status of NDT5V */ + uint32_t : 30; + } NDTSTS_b; + } ; + + union { + __IOM uint32_t ANTIEFT; /*!< (@ 0x00000030) Offset:0x30 Anti-EFT Ability Control Register */ + + struct { + __IOM uint32_t AEFT : 3; /*!< [2..0] Anti-EFT ability */ + uint32_t : 29; + } ANTIEFT_b; + } ; +} SN_SYS0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 1 (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + uint32_t : 4; + __IOM uint32_t USBCLKEN : 1; /*!< [4..4] Enable AHB clock for USB */ + uint32_t : 1; + __IOM uint32_t CT16B0CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B1 */ + uint32_t : 3; + __IOM uint32_t ADCCLKEN : 1; /*!< [11..11] Enable AHB clock for ADC */ + __IOM uint32_t SPI0CLKEN : 1; /*!< [12..12] Enable AHB clock for SPI0 */ + __IOM uint32_t SPI1CLKEN : 1; /*!< [13..13] Enable AHB clock for SPI1 */ + uint32_t : 2; + __IOM uint32_t UART0CLKEN : 1; /*!< [16..16] Enable AHB clock for UART0 */ + __IOM uint32_t UART1CLKEN : 1; /*!< [17..17] Enable AHB clock for UART1 */ + __IOM uint32_t UART2CLKEN : 1; /*!< [18..18] Enable AHB clock for UART2 */ + uint32_t : 1; + __IOM uint32_t I2C1CLKEN : 1; /*!< [20..20] Enable AHB clock for I2C1 */ + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + uint32_t : 2; + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + uint32_t : 2; + __IOM uint32_t CRCCLKEN : 1; /*!< [27..27] Enable AHB clock for CRC */ + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + + union { + __IOM uint32_t APBCP0; /*!< (@ 0x00000004) Offset:0x04 APB Clock Prescale Register 0 */ + + struct { + uint32_t : 16; + __IOM uint32_t ADCPRE : 3; /*!< [18..16] ADC APB clock source prescaler */ + uint32_t : 13; + } APBCP0_b; + } ; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + uint32_t : 8; + __IOM uint32_t I2C0PRE : 3; /*!< [10..8] I2C0 APB clock source prescaler */ + uint32_t : 9; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2C1PRE : 3; /*!< [26..24] I2C1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CLKOUTPRE : 3; /*!< [30..28] CLKOUT APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t PRST; /*!< (@ 0x00000010) Offset:0x10 Peripheral Reset Register */ + + struct { + __IOM uint32_t GPIO0RST : 1; /*!< [0..0] GPIO0 Reset */ + __IOM uint32_t GPIO1RST : 1; /*!< [1..1] GPIO1 Reset */ + __IOM uint32_t GPIO2RST : 1; /*!< [2..2] GPIO2 Reset */ + __IOM uint32_t GPIO3RST : 1; /*!< [3..3] GPIO3 Reset */ + uint32_t : 2; + __IOM uint32_t CT16B0RST : 1; /*!< [6..6] CT16B0 Reset */ + __IOM uint32_t CT16B1RST : 1; /*!< [7..7] CT16B1 Reset */ + uint32_t : 3; + __IOM uint32_t ADCRST : 1; /*!< [11..11] ADC Reset */ + __IOM uint32_t SPI0RST : 1; /*!< [12..12] SPI0 Reset */ + __IOM uint32_t SPI1RST : 1; /*!< [13..13] SPI1 Reset */ + uint32_t : 2; + __IOM uint32_t UART0RST : 1; /*!< [16..16] UART0 Reset */ + __IOM uint32_t UART1RST : 1; /*!< [17..17] UART1 Reset */ + __IOM uint32_t UART2RST : 1; /*!< [18..18] UART2 Reset */ + uint32_t : 1; + __IOM uint32_t I2C1RST : 1; /*!< [20..20] I2C1 Reset */ + __IOM uint32_t I2C0RST : 1; /*!< [21..21] I2C0 Reset */ + uint32_t : 2; + __IOM uint32_t WDTRST : 1; /*!< [24..24] WDT Reset */ + uint32_t : 1; + __IOM uint32_t CRCRST : 1; /*!< [26..26] CRC Reset */ + __IOM uint32_t USBRST : 1; /*!< [27..27] USB Reset */ + uint32_t : 4; + } PRST_b; + } ; +} SN_SYS1_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; +} SN_PMU_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PFPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Function Pin Assignment (SN_PFPA) + */ + +typedef struct { /*!< (@ 0x40042000) SN_PFPA Structure */ + + union { + __IOM uint32_t CT16B1; /*!< (@ 0x00000000) Offset:0x00 PFPA for CT16B1 Register */ + + struct { + __IOM uint32_t PWM00 : 1; /*!< [0..0] CT16B1_PWM00 assigned pin */ + __IOM uint32_t PWM01 : 1; /*!< [1..1] CT16B1_PWM01 assigned pin */ + __IOM uint32_t PWM02 : 1; /*!< [2..2] CT16B1_PWM02 assigned pin */ + __IOM uint32_t PWM03 : 1; /*!< [3..3] CT16B1_PWM03 assigned pin */ + __IOM uint32_t PWM04 : 1; /*!< [4..4] CT16B1_PWM04 assigned pin */ + __IOM uint32_t PWM05 : 1; /*!< [5..5] CT16B1_PWM05 assigned pin */ + __IOM uint32_t PWM06 : 1; /*!< [6..6] CT16B1_PWM06 assigned pin */ + __IOM uint32_t PWM07 : 1; /*!< [7..7] CT16B1_PWM07 assigned pin */ + __IOM uint32_t PWM08 : 1; /*!< [8..8] CT16B1_PWM08 assigned pin */ + __IOM uint32_t PWM09 : 1; /*!< [9..9] CT16B1_PWM09 assigned pin */ + __IOM uint32_t PWM10 : 1; /*!< [10..10] CT16B1_PWM10 assigned pin */ + __IOM uint32_t PWM11 : 1; /*!< [11..11] CT16B1_PWM11 assigned pin */ + __IOM uint32_t PWM12 : 1; /*!< [12..12] CT16B1_PWM12 assigned pin */ + __IOM uint32_t PWM13 : 1; /*!< [13..13] CT16B1_PWM13 assigned pin */ + __IOM uint32_t PWM14 : 1; /*!< [14..14] CT16B1_PWM14 assigned pin */ + __IOM uint32_t PWM15 : 1; /*!< [15..15] CT16B1_PWM15 assigned pin */ + __IOM uint32_t PWM16 : 1; /*!< [16..16] CT16B1_PWM16 assigned pin */ + __IOM uint32_t PWM17 : 1; /*!< [17..17] CT16B1_PWM17 assigned pin */ + __IOM uint32_t PWM18 : 1; /*!< [18..18] CT16B1_PWM18 assigned pin */ + __IOM uint32_t PWM19 : 1; /*!< [19..19] CT16B1_PWM19 assigned pin */ + __IOM uint32_t PWM20 : 1; /*!< [20..20] CT16B1_PWM20 assigned pin */ + __IOM uint32_t PWM21 : 1; /*!< [21..21] CT16B1_PWM21 assigned pin */ + __IOM uint32_t PWM22 : 1; /*!< [22..22] CT16B1_PWM22 assigned pin */ + __IOM uint32_t PWM23 : 1; /*!< [23..23] CT16B1_PWM23 assigned pin */ + uint32_t : 8; + } CT16B1_b; + } ; + + union { + __IOM uint32_t INTERFACE; /*!< (@ 0x00000004) Offset:0x04 PFPA for INTERFACE Register */ + + struct { + __IOM uint32_t I2C0 : 2; /*!< [1..0] I2C0 assigned pin */ + __IOM uint32_t I2C1 : 2; /*!< [3..2] I2C1 assigned pin */ + __IOM uint32_t SPI0 : 2; /*!< [5..4] SPI0 assigned pin */ + __IOM uint32_t SPI1 : 2; /*!< [7..6] SPI1 assigned pin */ + __IOM uint32_t MOSI1 : 3; /*!< [10..8] MOSI1 assigned pin */ + uint32_t : 21; + } INTERFACE_b; + } ; +} SN_PFPA_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO1) + */ + +typedef struct { /*!< (@ 0x40046000) SN_GPIO1 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; + + union { + __IOM uint32_t DCS; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Driving Current Select + Register */ + + struct { + __IOM uint32_t DCS0 : 2; /*!< [1..0] Driving current select of Pn.0 */ + __IOM uint32_t DCS1 : 2; /*!< [3..2] Driving current select of Pn.1 */ + __IOM uint32_t DCS2 : 2; /*!< [5..4] Driving current select of Pn.2 */ + __IOM uint32_t DCS3 : 2; /*!< [7..6] Driving current select of Pn.3 */ + __IOM uint32_t DCS4 : 2; /*!< [9..8] Driving current select of Pn.4 */ + __IOM uint32_t DCS5 : 2; /*!< [11..10] Driving current select of Pn.5 */ + __IOM uint32_t DCS6 : 2; /*!< [13..12] Driving current select of Pn.6 */ + __IOM uint32_t DCS7 : 2; /*!< [15..14] Driving current select of Pn.7 */ + __IOM uint32_t DCS8 : 2; /*!< [17..16] Driving current select of Pn.8 */ + __IOM uint32_t DCS9 : 2; /*!< [19..18] Driving current select of Pn.9 */ + __IOM uint32_t DCS10 : 2; /*!< [21..20] Driving current select of Pn.10 */ + __IOM uint32_t DCS11 : 2; /*!< [23..22] Driving current select of Pn.11 */ + __IOM uint32_t DCS12 : 2; /*!< [25..24] Driving current select of Pn.12 */ + __IOM uint32_t DCS13 : 2; /*!< [27..26] Driving current select of Pn.13 */ + __IOM uint32_t DCS14 : 2; /*!< [29..28] Driving current select of Pn.14 */ + __IOM uint32_t DCS15 : 2; /*!< [31..30] Driving current select of Pn.15 */ + } DCS_b; + } ; + + union { + __IOM uint32_t SCS; /*!< (@ 0x00000030) Offset:0x30 GPIO Port n Sinking Current Select + Register */ + + struct { + __IOM uint32_t SCS0 : 2; /*!< [1..0] Sinking current select of Pn.0 */ + __IOM uint32_t SCS1 : 2; /*!< [3..2] Sinking current select of Pn.1 */ + __IOM uint32_t SCS2 : 2; /*!< [5..4] Sinking current select of Pn.2 */ + __IOM uint32_t SCS3 : 2; /*!< [7..6] Sinking current select of Pn.3 */ + __IOM uint32_t SCS4 : 2; /*!< [9..8] Sinking current select of Pn.4 */ + __IOM uint32_t SCS5 : 2; /*!< [11..10] Sinking current select of Pn.5 */ + __IOM uint32_t SCS6 : 2; /*!< [13..12] Sinking current select of Pn.6 */ + __IOM uint32_t SCS7 : 2; /*!< [15..14] Sinking current select of Pn.7 */ + __IOM uint32_t SCS8 : 2; /*!< [17..16] Sinking current select of Pn.8 */ + __IOM uint32_t SCS9 : 2; /*!< [19..18] Sinking current select of Pn.9 */ + __IOM uint32_t SCS10 : 2; /*!< [21..20] Sinking current select of Pn.10 */ + __IOM uint32_t SCS11 : 2; /*!< [23..22] Sinking current select of Pn.11 */ + uint32_t : 8; + } SCS_b; + } ; +} SN_GPIO1_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO2) + */ + +typedef struct { /*!< (@ 0x40048000) SN_GPIO2 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; + + union { + __IOM uint32_t DCS; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Driving Current Select + Register */ + + struct { + __IOM uint32_t DCS0 : 2; /*!< [1..0] Driving current select of Pn.0 */ + __IOM uint32_t DCS1 : 2; /*!< [3..2] Driving current select of Pn.1 */ + __IOM uint32_t DCS2 : 2; /*!< [5..4] Driving current select of Pn.2 */ + __IOM uint32_t DCS3 : 2; /*!< [7..6] Driving current select of Pn.3 */ + __IOM uint32_t DCS4 : 2; /*!< [9..8] Driving current select of Pn.4 */ + __IOM uint32_t DCS5 : 2; /*!< [11..10] Driving current select of Pn.5 */ + __IOM uint32_t DCS6 : 2; /*!< [13..12] Driving current select of Pn.6 */ + __IOM uint32_t DCS7 : 2; /*!< [15..14] Driving current select of Pn.7 */ + __IOM uint32_t DCS8 : 2; /*!< [17..16] Driving current select of Pn.8 */ + __IOM uint32_t DCS9 : 2; /*!< [19..18] Driving current select of Pn.9 */ + __IOM uint32_t DCS10 : 2; /*!< [21..20] Driving current select of Pn.10 */ + __IOM uint32_t DCS11 : 2; /*!< [23..22] Driving current select of Pn.11 */ + __IOM uint32_t DCS12 : 2; /*!< [25..24] Driving current select of Pn.12 */ + __IOM uint32_t DCS13 : 2; /*!< [27..26] Driving current select of Pn.13 */ + __IOM uint32_t DCS14 : 2; /*!< [29..28] Driving current select of Pn.14 */ + __IOM uint32_t DCS15 : 2; /*!< [31..30] Driving current select of Pn.15 */ + } DCS_b; + } ; +} SN_GPIO2_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO3) + */ + +typedef struct { /*!< (@ 0x4004A000) SN_GPIO3 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + uint32_t : 3; + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + uint32_t : 20; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + uint32_t : 3; + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + uint32_t : 20; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + uint32_t : 6; + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + uint32_t : 8; + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + uint32_t : 3; + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + uint32_t : 20; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + uint32_t : 3; + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + uint32_t : 20; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + uint32_t : 3; + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + uint32_t : 20; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + uint32_t : 3; + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + uint32_t : 20; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + uint32_t : 3; + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + uint32_t : 20; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + uint32_t : 3; + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + uint32_t : 20; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + uint32_t : 3; + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + uint32_t : 20; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + uint32_t : 3; + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + uint32_t : 20; + } BCLR_b; + } ; + + union { + __IOM uint32_t DCS; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Driving Current Select + Register */ + + struct { + __IOM uint32_t DCS0 : 2; /*!< [1..0] Driving current select of Pn.0 */ + __IOM uint32_t DCS1 : 2; /*!< [3..2] Driving current select of Pn.1 */ + uint32_t : 6; + __IOM uint32_t DCS5 : 2; /*!< [11..10] Driving current select of Pn.5 */ + __IOM uint32_t DCS6 : 2; /*!< [13..12] Driving current select of Pn.6 */ + __IOM uint32_t DCS7 : 2; /*!< [15..14] Driving current select of Pn.7 */ + __IOM uint32_t DCS8 : 2; /*!< [17..16] Driving current select of Pn.8 */ + __IOM uint32_t DCS9 : 2; /*!< [19..18] Driving current select of Pn.9 */ + __IOM uint32_t DCS10 : 2; /*!< [21..20] Driving current select of Pn.10 */ + __IOM uint32_t DCS11 : 2; /*!< [23..22] Driving current select of Pn.11 */ + uint32_t : 8; + } DCS_b; + } ; +} SN_GPIO3_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO0) + */ + +typedef struct { /*!< (@ 0x40044000) SN_GPIO0 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; + + union { + __IOM uint32_t DCS; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Driving Current Select + Register */ + + struct { + __IOM uint32_t DCS0 : 2; /*!< [1..0] Driving current select of Pn.0 */ + __IOM uint32_t DCS1 : 2; /*!< [3..2] Driving current select of Pn.1 */ + __IOM uint32_t DCS2 : 2; /*!< [5..4] Driving current select of Pn.2 */ + __IOM uint32_t DCS3 : 2; /*!< [7..6] Driving current select of Pn.3 */ + __IOM uint32_t DCS4 : 2; /*!< [9..8] Driving current select of Pn.4 */ + __IOM uint32_t DCS5 : 2; /*!< [11..10] Driving current select of Pn.5 */ + __IOM uint32_t DCS6 : 2; /*!< [13..12] Driving current select of Pn.6 */ + __IOM uint32_t DCS7 : 2; /*!< [15..14] Driving current select of Pn.7 */ + __IOM uint32_t DCS8 : 2; /*!< [17..16] Driving current select of Pn.8 */ + __IOM uint32_t DCS9 : 2; /*!< [19..18] Driving current select of Pn.9 */ + __IOM uint32_t DCS10 : 2; /*!< [21..20] Driving current select of Pn.10 */ + __IOM uint32_t DCS11 : 2; /*!< [23..22] Driving current select of Pn.11 */ + __IOM uint32_t DCS12 : 2; /*!< [25..24] Driving current select of Pn.12 */ + __IOM uint32_t DCS13 : 2; /*!< [27..26] Driving current select of Pn.13 */ + __IOM uint32_t DCS14 : 2; /*!< [29..28] Driving current select of Pn.14 */ + __IOM uint32_t DCS15 : 2; /*!< [31..30] Driving current select of Pn.15 */ + } DCS_b; + } ; + + union { + __IOM uint32_t SCS; /*!< (@ 0x00000030) Offset:0x30 GPIO Port n Sinking Current Select + Register */ + + struct { + uint32_t : 16; + __IOM uint32_t SCS8 : 2; /*!< [17..16] Sinking current select of Pn.8 */ + __IOM uint32_t SCS9 : 2; /*!< [19..18] Sinking current select of Pn.9 */ + __IOM uint32_t SCS10 : 2; /*!< [21..20] Sinking current select of Pn.10 */ + __IOM uint32_t SCS11 : 2; /*!< [23..22] Sinking current select of Pn.11 */ + __IOM uint32_t SCS12 : 2; /*!< [25..24] Sinking current select of Pn.12 */ + __IOM uint32_t SCS13 : 2; /*!< [27..26] Sinking current select of Pn.13 */ + __IOM uint32_t SCS14 : 2; /*!< [29..28] Sinking current select of Pn.14 */ + __IOM uint32_t SCS15 : 2; /*!< [31..30] Sinking current select of Pn.15 */ + } SCS_b; + } ; +} SN_GPIO0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (SN_ADC) + */ + +typedef struct { /*!< (@ 0x40026000) SN_ADC Structure */ + + union { + __IOM uint32_t ADM; /*!< (@ 0x00000000) Offset:0x00 ADC Management Register */ + + struct { + __IOM uint32_t CHS : 5; /*!< [4..0] ADC input channel */ + __IOM uint32_t GCHS : 1; /*!< [5..5] ADC global channel enable */ + __IOM uint32_t EOC : 1; /*!< [6..6] ADC status */ + __IOM uint32_t ADS : 1; /*!< [7..7] ADC start control */ + __IOM uint32_t ADLEN : 1; /*!< [8..8] ADC resolution */ + __IOM uint32_t ADCKS : 3; /*!< [11..9] ADC clock source divider */ + __IOM uint32_t ADENB : 1; /*!< [12..12] ADC enable */ + __IOM uint32_t AVREFHSEL : 1; /*!< [13..13] ADC high reference voltage source */ + __IOM uint32_t VHS : 3; /*!< [16..14] Internal Ref. voltage source */ + uint32_t : 15; + } ADM_b; + } ; + + union { + __IM uint32_t ADB; /*!< (@ 0x00000004) Offset:0x04 ADC Data Register */ + + struct { + __IM uint32_t ADB : 12; /*!< [11..0] ADB11~ADB4 bits for 8-bit ADC, ADB11~ADB0 bits for 12-bit + ADC */ + uint32_t : 20; + } ADB_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C ADC Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] AIN0 interrupt enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] AIN1 interrupt enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] AIN2 interrupt enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] AIN3 interrupt enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] AIN4 interrupt enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] AIN5 interrupt enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] AIN6 interrupt enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] AIN7 interrupt enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] AIN8 interrupt enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] AIN9 interrupt enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] AIN10 interrupt enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] AIN11 interrupt enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] AIN12 interrupt enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] AIN13 interrupt enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] AIN14 interrupt enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] AIN15 interrupt enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] AIN16 interrupt enable */ + uint32_t : 15; + } IE_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 ADC Raw Interrupt Status Register */ + + struct { + __IOM uint32_t EOCIF0 : 1; /*!< [0..0] AIN0 interrupt flag */ + __IOM uint32_t EOCIF1 : 1; /*!< [1..1] AIN1 interrupt flag */ + __IOM uint32_t EOCIF2 : 1; /*!< [2..2] AIN2 interrupt flag */ + __IOM uint32_t EOCIF3 : 1; /*!< [3..3] AIN0 interrupt flag */ + __IOM uint32_t EOCIF4 : 1; /*!< [4..4] AIN4 interrupt flag */ + __IOM uint32_t EOCIF5 : 1; /*!< [5..5] AIN5 interrupt flag */ + __IOM uint32_t EOCIF6 : 1; /*!< [6..6] AIN6 interrupt flag */ + __IOM uint32_t EOCIF7 : 1; /*!< [7..7] AIN7 interrupt flag */ + __IOM uint32_t EOCIF8 : 1; /*!< [8..8] AIN8 interrupt flag */ + __IOM uint32_t EOCIF9 : 1; /*!< [9..9] AIN9 interrupt flag */ + __IOM uint32_t EOCIF10 : 1; /*!< [10..10] AIN10 interrupt flag */ + __IOM uint32_t EOCIF11 : 1; /*!< [11..11] AIN11 interrupt flag */ + __IOM uint32_t EOCIF12 : 1; /*!< [12..12] AIN12 interrupt flag */ + __IOM uint32_t EOCIF13 : 1; /*!< [13..13] AIN13 interrupt flag */ + __IOM uint32_t EOCIF14 : 1; /*!< [14..14] AIN14 interrupt flag */ + __IOM uint32_t EOCIF15 : 1; /*!< [15..15] AIN15 interrupt flag */ + __IOM uint32_t EOCIF16 : 1; /*!< [16..16] AIN16 interrupt flag */ + uint32_t : 15; + } RIS_b; + } ; + __IOM uint32_t CALI; /*!< (@ 0x00000014) Offset:0x14 ADC Calibration Register */ +} SN_ADC_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + __IOM uint32_t CIS : 2; /*!< [3..2] Counter Input Select */ + uint32_t : 28; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + uint32_t : 29; + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IM uint32_t RESERVED1[23]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000080) Offset:0x80 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture on CT16Bn_CAP0 rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture on CT16Bn_CAP0 falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000084) Offset:0x84 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + uint32_t : 24; + __IM uint32_t CAP0IF : 1; /*!< [25..25] Interrupt flag for capture channel 0 */ + uint32_t : 6; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + uint32_t : 24; + __OM uint32_t CAP0IC : 1; /*!< [25..25] CAP0IF clear bit */ + uint32_t : 6; + } IC_b; + } ; +} SN_CT16B0_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B1) + */ + +typedef struct { /*!< (@ 0x40002000) SN_CT16B1 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + __IOM uint32_t MR4IE : 1; /*!< [12..12] Enable generating an interrupt when MR4 matches TC */ + __IOM uint32_t MR4RST : 1; /*!< [13..13] Enable reset TC when MR4 matches TC */ + __IOM uint32_t MR4STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR4 matches TC */ + __IOM uint32_t MR5IE : 1; /*!< [15..15] Enable generating an interrupt when MR5 matches TC */ + __IOM uint32_t MR5RST : 1; /*!< [16..16] Enable reset TC when MR5 matches TC */ + __IOM uint32_t MR5STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR5 matches TC */ + __IOM uint32_t MR6IE : 1; /*!< [18..18] Enable generating an interrupt when MR6 matches TC */ + __IOM uint32_t MR6RST : 1; /*!< [19..19] Enable reset TC when MR6 matches TC */ + __IOM uint32_t MR6STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR6 matches TC */ + __IOM uint32_t MR7IE : 1; /*!< [21..21] Enable generating an interrupt when MR7 matches TC */ + __IOM uint32_t MR7RST : 1; /*!< [22..22] Enable reset TC when MR7 matches TC */ + __IOM uint32_t MR7STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR7 matches TC */ + __IOM uint32_t MR8IE : 1; /*!< [24..24] Enable generating an interrupt when MR8 matches TC */ + __IOM uint32_t MR8RST : 1; /*!< [25..25] Enable reset TC when MR8 matches TC */ + __IOM uint32_t MR8STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR8 matches TC */ + __IOM uint32_t MR9IE : 1; /*!< [27..27] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [28..28] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR9 matches TC */ + uint32_t : 2; + } MCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ + + struct { + __IOM uint32_t MR10IE : 1; /*!< [0..0] Enable generating an interrupt when MR10 matches TC */ + __IOM uint32_t MR10RST : 1; /*!< [1..1] Enable reset TC when MR10 matches TC */ + __IOM uint32_t MR10STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR10 matches TC */ + __IOM uint32_t MR11IE : 1; /*!< [3..3] Enable generating an interrupt when MR11 matches TC */ + __IOM uint32_t MR11RST : 1; /*!< [4..4] Enable reset TC when MR11 matches TC */ + __IOM uint32_t MR11STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR11 matches TC */ + __IOM uint32_t MR12IE : 1; /*!< [6..6] Enable generating an interrupt when MR12 matches TC */ + __IOM uint32_t MR12RST : 1; /*!< [7..7] Enable reset TC when MR12 matches TC */ + __IOM uint32_t MR12STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR12 matches TC */ + __IOM uint32_t MR13IE : 1; /*!< [9..9] Enable generating an interrupt when MR13 matches TC */ + __IOM uint32_t MR13RST : 1; /*!< [10..10] Enable reset TC when MR13 matches TC */ + __IOM uint32_t MR13STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR13 matches + TC */ + __IOM uint32_t MR14IE : 1; /*!< [12..12] Enable generating an interrupt when MR14 matches TC */ + __IOM uint32_t MR14RST : 1; /*!< [13..13] Enable reset TC when MR14 matches TC */ + __IOM uint32_t MR14STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR14 matches + TC */ + __IOM uint32_t MR15IE : 1; /*!< [15..15] Enable generating an interrupt when MR15 matches TC */ + __IOM uint32_t MR15RST : 1; /*!< [16..16] Enable reset TC when MR15 matches TC */ + __IOM uint32_t MR15STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR15 matches + TC */ + __IOM uint32_t MR16IE : 1; /*!< [18..18] Enable generating an interrupt when MR16 matches TC */ + __IOM uint32_t MR16RST : 1; /*!< [19..19] Enable reset TC when MR16 matches TC */ + __IOM uint32_t MR16STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR16 matches + TC */ + __IOM uint32_t MR17IE : 1; /*!< [21..21] Enable generating an interrupt when MR17 matches TC */ + __IOM uint32_t MR17RST : 1; /*!< [22..22] Enable reset TC when MR17 matches TC */ + __IOM uint32_t MR17STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR17 matches + TC */ + __IOM uint32_t MR18IE : 1; /*!< [24..24] Enable generating an interrupt when MR18 matches TC */ + __IOM uint32_t MR18RST : 1; /*!< [25..25] Enable reset TC when MR18 matches TC */ + __IOM uint32_t MR18STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR18 matches + TC */ + __IOM uint32_t MR19IE : 1; /*!< [27..27] Enable generating an interrupt when MR19 matches TC */ + __IOM uint32_t MR19RST : 1; /*!< [28..28] Enable reset TC when MR19 matches TC */ + __IOM uint32_t MR19STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR19 matches + TC */ + uint32_t : 2; + } MCTRL2_b; + } ; + + union { + __IOM uint32_t MCTRL3; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn Match Control Register 3 */ + + struct { + __IOM uint32_t MR20IE : 1; /*!< [0..0] Enable generating an interrupt when MR20 matches TC */ + __IOM uint32_t MR20RST : 1; /*!< [1..1] Enable reset TC when MR20 matches TC */ + __IOM uint32_t MR20STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR20 matches TC */ + __IOM uint32_t MR21IE : 1; /*!< [3..3] Enable generating an interrupt when MR21 matches TC */ + __IOM uint32_t MR21RST : 1; /*!< [4..4] Enable reset TC when MR21 matches TC */ + __IOM uint32_t MR21STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR21 matches TC */ + __IOM uint32_t MR22IE : 1; /*!< [6..6] Enable generating an interrupt when MR22 matches TC */ + __IOM uint32_t MR22RST : 1; /*!< [7..7] Enable reset TC when MR22 matches TC */ + __IOM uint32_t MR22STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR22 matches TC */ + __IOM uint32_t MR23IE : 1; /*!< [9..9] Enable generating an interrupt when MR23 matches TC */ + __IOM uint32_t MR23RST : 1; /*!< [10..10] Enable reset TC when MR23 matches TC */ + __IOM uint32_t MR23STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR23 matches + TC */ + __IOM uint32_t MR24IE : 1; /*!< [12..12] Enable generating an interrupt when MR24 matches TC */ + __IOM uint32_t MR24RST : 1; /*!< [13..13] Enable reset TC when MR24 matches TC */ + __IOM uint32_t MR24STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR24 matches + TC */ + uint32_t : 17; + } MCTRL3_b; + } ; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + __IOM uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + __IOM uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + __IOM uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + __IOM uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + __IOM uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + __IOM uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + __IOM uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + __IOM uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + __IOM uint32_t MR13; /*!< (@ 0x00000054) Offset:0x54 CT16Bn MR13 Register */ + __IOM uint32_t MR14; /*!< (@ 0x00000058) Offset:0x58 CT16Bn MR14 Register */ + __IOM uint32_t MR15; /*!< (@ 0x0000005C) Offset:0x5C CT16Bn MR15 Register */ + __IOM uint32_t MR16; /*!< (@ 0x00000060) Offset:0x60 CT16Bn MR16 Register */ + __IOM uint32_t MR17; /*!< (@ 0x00000064) Offset:0x64 CT16Bn MR17 Register */ + __IOM uint32_t MR18; /*!< (@ 0x00000068) Offset:0x68 CT16Bn MR18 Register */ + __IOM uint32_t MR19; /*!< (@ 0x0000006C) Offset:0x6C CT16Bn MR19 Register */ + __IOM uint32_t MR20; /*!< (@ 0x00000070) Offset:0x70 CT16Bn MR20 Register */ + __IOM uint32_t MR21; /*!< (@ 0x00000074) Offset:0x74 CT16Bn MR21 Register */ + __IOM uint32_t MR22; /*!< (@ 0x00000078) Offset:0x78 CT16Bn MR22 Register */ + __IOM uint32_t MR23; /*!< (@ 0x0000007C) Offset:0x7C CT16Bn MR23 Register */ + __IOM uint32_t MR24; /*!< (@ 0x00000080) Offset:0x80 CT16Bn MR24 Register */ + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t EM; /*!< (@ 0x00000088) Offset:0x88 CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC doesn't match MR0 and EMC0 is not 0, this + bit will drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC doesn't match MR1 and EMC1 is not 0, this + bit will drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC doesn't match MR2 and EMC2 is not 0, this + bit will drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC doesn't match MR3 and EMC3 is not 0, this + bit will drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM4 : 1; /*!< [4..4] When the TC doesn't match MR4 and EMC4 is not 0, this + bit will drive the state of CT16Bn_PWM4 output. */ + __IOM uint32_t EM5 : 1; /*!< [5..5] When the TC doesn't match MR5 and EMC5 is not 0, this + bit will drive the state of CT16Bn_PWM5 output. */ + __IOM uint32_t EM6 : 1; /*!< [6..6] When the TC doesn't match MR6 and EMC6 is not 0, this + bit will drive the state of CT16Bn_PWM6 output. */ + __IOM uint32_t EM7 : 1; /*!< [7..7] When the TC doesn't match MR7 and EMC7 is not 0, this + bit will drive the state of CT16Bn_PWM7 output. */ + __IOM uint32_t EM8 : 1; /*!< [8..8] When the TC doesn't match MR8 and EMC8 is not 0, this + bit will drive the state of CT16Bn_PWM8 output. */ + __IOM uint32_t EM9 : 1; /*!< [9..9] When the TC doesn't match MR9 and EMC9 is not 0, this + bit will drive the state of CT16Bn_PWM9 output. */ + __IOM uint32_t EM10 : 1; /*!< [10..10] When the TC doesn't match MR10 and EMC10 is not 0, + this bit will drive the state of CT16Bn_PWM10 output. */ + __IOM uint32_t EM11 : 1; /*!< [11..11] When the TC doesn't match MR11 and EMC11 is not 0, + this bit will drive the state of CT16Bn_PWM11 output. */ + __IOM uint32_t EM12 : 1; /*!< [12..12] When the TC doesn't match MR12 and EMC12 is not 0, + this bit will drive the state of CT16Bn_PWM12 output. */ + __IOM uint32_t EM13 : 1; /*!< [13..13] When the TC doesn't match MR13 and EMC13 is not 0, + this bit will drive the state of CT16Bn_PWM13 output. */ + __IOM uint32_t EM14 : 1; /*!< [14..14] When the TC doesn't match MR14 and EMC14 is not 0, + this bit will drive the state of CT16Bn_PWM14 output. */ + __IOM uint32_t EM15 : 1; /*!< [15..15] When the TC doesn't match MR15 and EMC15 is not 0, + this bit will drive the state of CT16Bn_PWM15 output. */ + __IOM uint32_t EM16 : 1; /*!< [16..16] When the TC doesn't match MR16 and EMC16 is not 0, + this bit will drive the state of CT16Bn_PWM16 output. */ + __IOM uint32_t EM17 : 1; /*!< [17..17] When the TC doesn't match MR17 and EMC17 is not 0, + this bit will drive the state of CT16Bn_PWM17 output. */ + __IOM uint32_t EM18 : 1; /*!< [18..18] When the TC doesn't match MR18 and EMC18 is not 0, + this bit will drive the state of CT16Bn_PWM18 output. */ + __IOM uint32_t EM19 : 1; /*!< [19..19] When the TC doesn't match MR19 and EMC19 is not 0, + this bit will drive the state of CT16Bn_PWM19 output. */ + __IOM uint32_t EM20 : 1; /*!< [20..20] When the TC doesn't match MR20 and EMC20 is not 0, + this bit will drive the state of CT16Bn_PWM20 output. */ + __IOM uint32_t EM21 : 1; /*!< [21..21] When the TC doesn't match MR21 and EMC21 is not 0, + this bit will drive the state of CT16Bn_PWM21 output. */ + __IOM uint32_t EM22 : 1; /*!< [22..22] When the TC doesn't match MR22 and EMC22 is not 0, + this bit will drive the state of CT16Bn_PWM22 output. */ + __IOM uint32_t EM23 : 1; /*!< [23..23] When the TC doesn't match MR23 and EMC23 is not 0, + this bit will drive the state of CT16Bn_PWM23 output. */ + uint32_t : 8; + } EM_b; + } ; + + union { + __IOM uint32_t EMC; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Control register */ + + struct { + __IOM uint32_t EMC0 : 2; /*!< [1..0] CT16Bn_PWM0 functionality when the TC matches MR0 */ + __IOM uint32_t EMC1 : 2; /*!< [3..2] CT16Bn_PWM1 functionality when the TC matches MR1 */ + __IOM uint32_t EMC2 : 2; /*!< [5..4] CT16Bn_PWM2 functionality when the TC matches MR2 */ + __IOM uint32_t EMC3 : 2; /*!< [7..6] CT16Bn_PWM3 functionality when the TC matches MR3 */ + __IOM uint32_t EMC4 : 2; /*!< [9..8] CT16Bn_PWM4 functionality when the TC matches MR4 */ + __IOM uint32_t EMC5 : 2; /*!< [11..10] CT16Bn_PWM5 functionality when the TC matches MR5 */ + __IOM uint32_t EMC6 : 2; /*!< [13..12] CT16Bn_PWM6 functionality when the TC matches MR6 */ + __IOM uint32_t EMC7 : 2; /*!< [15..14] CT16Bn_PWM7 functionality when the TC matches MR7 */ + __IOM uint32_t EMC8 : 2; /*!< [17..16] CT16Bn_PWM8 functionality when the TC matches MR8 */ + __IOM uint32_t EMC9 : 2; /*!< [19..18] CT16Bn_PWM9 functionality when the TC matches MR9 */ + __IOM uint32_t EMC10 : 2; /*!< [21..20] CT16Bn_PWM10 functionality when the TC matches MR10 */ + __IOM uint32_t EMC11 : 2; /*!< [23..22] CT16Bn_PWM11 functionality when the TC matches MR11 */ + __IOM uint32_t EMC12 : 2; /*!< [25..24] CT16Bn_PWM12 functionality when the TC matches MR12 */ + __IOM uint32_t EMC13 : 2; /*!< [27..26] CT16Bn_PWM13 functionality when the TC matches MR13 */ + __IOM uint32_t EMC14 : 2; /*!< [29..28] CT16Bn_PWM14 functionality when the TC matches MR14 */ + __IOM uint32_t EMC15 : 2; /*!< [31..30] CT16Bn_PWM15 functionality when the TC matches MR15 */ + } EMC_b; + } ; + + union { + __IOM uint32_t EMC2; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register + 2 */ + + struct { + __IOM uint32_t EMC16 : 2; /*!< [1..0] CT16Bn_PWM16 functionality when the TC matches MR16 */ + __IOM uint32_t EMC17 : 2; /*!< [3..2] CT16Bn_PWM17 functionality when the TC matches MR17 */ + __IOM uint32_t EMC18 : 2; /*!< [5..4] CT16Bn_PWM18 functionality when the TC matches MR18 */ + __IOM uint32_t EMC19 : 2; /*!< [7..6] CT16Bn_PWM19 functionality when the TC matches MR19 */ + __IOM uint32_t EMC20 : 2; /*!< [9..8] CT16Bn_PWM20 functionality when the TC matches MR20 */ + __IOM uint32_t EMC21 : 2; /*!< [11..10] CT16Bn_PWM21 functionality when the TC matches MR21 */ + __IOM uint32_t EMC22 : 2; /*!< [13..12] CT16Bn_PWM22 functionality when the TC matches MR22 */ + __IOM uint32_t EMC23 : 2; /*!< [15..14] CT16Bn_PWM23 functionality when the TC matches MR23 */ + uint32_t : 16; + } EMC2_b; + } ; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000094) Offset:0x94 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0MODE : 2; /*!< [1..0] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [3..2] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [5..4] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [7..6] PWM3 output mode */ + __IOM uint32_t PWM4MODE : 2; /*!< [9..8] PWM4 output mode */ + __IOM uint32_t PWM5MODE : 2; /*!< [11..10] PWM5 output mode */ + __IOM uint32_t PWM6MODE : 2; /*!< [13..12] PWM6 output mode */ + __IOM uint32_t PWM7MODE : 2; /*!< [15..14] PWM7 output mode */ + __IOM uint32_t PWM8MODE : 2; /*!< [17..16] PWM8 output mode */ + __IOM uint32_t PWM9MODE : 2; /*!< [19..18] PWM9 output mode */ + __IOM uint32_t PWM10MODE : 2; /*!< [21..20] PWM10 output mode */ + __IOM uint32_t PWM11MODE : 2; /*!< [23..22] PWM11 output mode */ + __IOM uint32_t PWM12MODE : 2; /*!< [25..24] PWM12 output mode */ + __IOM uint32_t PWM13MODE : 2; /*!< [27..26] PWM13 output mode */ + __IOM uint32_t PWM14MODE : 2; /*!< [29..28] PWM14 output mode */ + __IOM uint32_t PWM15MODE : 2; /*!< [31..30] PWM15 output mode */ + } PWMCTRL_b; + } ; + + union { + __IOM uint32_t PWMCTRL2; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register 2 */ + + struct { + __IOM uint32_t PWM16MODE : 2; /*!< [1..0] PWM16 output mode */ + __IOM uint32_t PWM17MODE : 2; /*!< [3..2] PWM17 output mode */ + __IOM uint32_t PWM18MODE : 2; /*!< [5..4] PWM18 output mode */ + __IOM uint32_t PWM19MODE : 2; /*!< [7..6] PWM19 output mode */ + __IOM uint32_t PWM20MODE : 2; /*!< [9..8] PWM20 output mode */ + __IOM uint32_t PWM21MODE : 2; /*!< [11..10] PWM21 output mode */ + __IOM uint32_t PWM22MODE : 2; /*!< [13..12] PWM22 output mode */ + __IOM uint32_t PWM23MODE : 2; /*!< [15..14] PWM23 output mode */ + uint32_t : 16; + } PWMCTRL2_b; + } ; + + union { + __IOM uint32_t PWMENB; /*!< (@ 0x0000009C) Offset:0x9C CT16Bn PWM Enable register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM4EN : 1; /*!< [4..4] PWM4 enable */ + __IOM uint32_t PWM5EN : 1; /*!< [5..5] PWM5 enable */ + __IOM uint32_t PWM6EN : 1; /*!< [6..6] PWM6 enable */ + __IOM uint32_t PWM7EN : 1; /*!< [7..7] PWM7 enable */ + __IOM uint32_t PWM8EN : 1; /*!< [8..8] PWM8 enable */ + __IOM uint32_t PWM9EN : 1; /*!< [9..9] PWM9 enable */ + __IOM uint32_t PWM10EN : 1; /*!< [10..10] PWM10 enable */ + __IOM uint32_t PWM11EN : 1; /*!< [11..11] PWM11 enable */ + __IOM uint32_t PWM12EN : 1; /*!< [12..12] PWM12 enable */ + __IOM uint32_t PWM13EN : 1; /*!< [13..13] PWM13 enable */ + __IOM uint32_t PWM14EN : 1; /*!< [14..14] PWM14 enable */ + __IOM uint32_t PWM15EN : 1; /*!< [15..15] PWM15 enable */ + __IOM uint32_t PWM16EN : 1; /*!< [16..16] PWM16 enable */ + __IOM uint32_t PWM17EN : 1; /*!< [17..17] PWM17 enable */ + __IOM uint32_t PWM18EN : 1; /*!< [18..18] PWM18 enable */ + __IOM uint32_t PWM19EN : 1; /*!< [19..19] PWM19 enable */ + __IOM uint32_t PWM20EN : 1; /*!< [20..20] PWM20 enable */ + __IOM uint32_t PWM21EN : 1; /*!< [21..21] PWM21 enable */ + __IOM uint32_t PWM22EN : 1; /*!< [22..22] PWM22 enable */ + __IOM uint32_t PWM23EN : 1; /*!< [23..23] PWM23 enable */ + uint32_t : 8; + } PWMENB_b; + } ; + + union { + __IOM uint32_t PWMIOENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM IO Enable register */ + + struct { + __IOM uint32_t PWM0IOEN : 1; /*!< [0..0] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [1..1] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [2..2] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [3..3] CT16Bn_PWM3/GPIO selection */ + __IOM uint32_t PWM4IOEN : 1; /*!< [4..4] CT16Bn_PWM4/GPIO selection */ + __IOM uint32_t PWM5IOEN : 1; /*!< [5..5] CT16Bn_PWM5/GPIO selection */ + __IOM uint32_t PWM6IOEN : 1; /*!< [6..6] CT16Bn_PWM6/GPIO selection */ + __IOM uint32_t PWM7IOEN : 1; /*!< [7..7] CT16Bn_PWM7/GPIO selection */ + __IOM uint32_t PWM8IOEN : 1; /*!< [8..8] CT16Bn_PWM8/GPIO selection */ + __IOM uint32_t PWM9IOEN : 1; /*!< [9..9] CT16Bn_PWM9/GPIO selection */ + __IOM uint32_t PWM10IOEN : 1; /*!< [10..10] CT16Bn_PWM10/GPIO selection */ + __IOM uint32_t PWM11IOEN : 1; /*!< [11..11] CT16Bn_PWM11/GPIO selection */ + __IOM uint32_t PWM12IOEN : 1; /*!< [12..12] CT16Bn_PWM12/GPIO selection */ + __IOM uint32_t PWM13IOEN : 1; /*!< [13..13] CT16Bn_PWM13/GPIO selection */ + __IOM uint32_t PWM14IOEN : 1; /*!< [14..14] CT16Bn_PWM14/GPIO selection */ + __IOM uint32_t PWM15IOEN : 1; /*!< [15..15] CT16Bn_PWM15/GPIO selection */ + __IOM uint32_t PWM16IOEN : 1; /*!< [16..16] CT16Bn_PWM16/GPIO selection */ + __IOM uint32_t PWM17IOEN : 1; /*!< [17..17] CT16Bn_PWM17/GPIO selection */ + __IOM uint32_t PWM18IOEN : 1; /*!< [18..18] CT16Bn_PWM18/GPIO selection */ + __IOM uint32_t PWM19IOEN : 1; /*!< [19..19] CT16Bn_PWM19/GPIO selection */ + __IOM uint32_t PWM20IOEN : 1; /*!< [20..20] CT16Bn_PWM20/GPIO selection */ + __IOM uint32_t PWM21IOEN : 1; /*!< [21..21] CT16Bn_PWM21/GPIO selection */ + __IOM uint32_t PWM22IOEN : 1; /*!< [22..22] CT16Bn_PWM22/GPIO selection */ + __IOM uint32_t PWM23IOEN : 1; /*!< [23..23] CT16Bn_PWM23/GPIO selection */ + uint32_t : 8; + } PWMIOENB_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t MR4IF : 1; /*!< [4..4] Match channel 4 interrupt flag */ + __IM uint32_t MR5IF : 1; /*!< [5..5] Match channel 5 interrupt flag */ + __IM uint32_t MR6IF : 1; /*!< [6..6] Match channel 6 interrupt flag */ + __IM uint32_t MR7IF : 1; /*!< [7..7] Match channel 7 interrupt flag */ + __IM uint32_t MR8IF : 1; /*!< [8..8] Match channel 8 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [9..9] Match channel 9 interrupt flag */ + __IM uint32_t MR10IF : 1; /*!< [10..10] Match channel 10 interrupt flag */ + __IM uint32_t MR11IF : 1; /*!< [11..11] Match channel 11 interrupt flag */ + __IM uint32_t MR12IF : 1; /*!< [12..12] Match channel 12 interrupt flag */ + __IM uint32_t MR13IF : 1; /*!< [13..13] Match channel 13 interrupt flag */ + __IM uint32_t MR14IF : 1; /*!< [14..14] Match channel 14 interrupt flag */ + __IM uint32_t MR15IF : 1; /*!< [15..15] Match channel 15 interrupt flag */ + __IM uint32_t MR16IF : 1; /*!< [16..16] Match channel 16 interrupt flag */ + __IM uint32_t MR17IF : 1; /*!< [17..17] Match channel 17 interrupt flag */ + __IM uint32_t MR18IF : 1; /*!< [18..18] Match channel 18 interrupt flag */ + __IM uint32_t MR19IF : 1; /*!< [19..19] Match channel 19 interrupt flag */ + __IM uint32_t MR20IF : 1; /*!< [20..20] Match channel 20 interrupt flag */ + __IM uint32_t MR21IF : 1; /*!< [21..21] Match channel 21 interrupt flag */ + __IM uint32_t MR22IF : 1; /*!< [22..22] Match channel 22 interrupt flag */ + __IM uint32_t MR23IF : 1; /*!< [23..23] Match channel 23 interrupt flag */ + __IM uint32_t MR24IF : 1; /*!< [24..24] Match channel 24 interrupt flag */ + uint32_t : 7; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t MR4IC : 1; /*!< [4..4] MR4IF clear bit */ + __OM uint32_t MR5IC : 1; /*!< [5..5] MR5IF clear bit */ + __OM uint32_t MR6IC : 1; /*!< [6..6] MR6IF clear bit */ + __OM uint32_t MR7IC : 1; /*!< [7..7] MR7IF clear bit */ + __OM uint32_t MR8IC : 1; /*!< [8..8] MR8IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [9..9] MR9IF clear bit */ + __OM uint32_t MR10IC : 1; /*!< [10..10] MR10IF clear bit */ + __OM uint32_t MR11IC : 1; /*!< [11..11] MR11IF clear bit */ + __OM uint32_t MR12IC : 1; /*!< [12..12] MR12IF clear bit */ + __OM uint32_t MR13IC : 1; /*!< [13..13] MR13IF clear bit */ + __OM uint32_t MR14IC : 1; /*!< [14..14] MR14IF clear bit */ + __OM uint32_t MR15IC : 1; /*!< [15..15] MR15IF clear bit */ + __OM uint32_t MR16IC : 1; /*!< [16..16] MR16IF clear bit */ + __OM uint32_t MR17IC : 1; /*!< [17..17] MR17IF clear bit */ + __OM uint32_t MR18IC : 1; /*!< [18..18] MR18IF clear bit */ + __OM uint32_t MR19IC : 1; /*!< [19..19] MR19IF clear bit */ + __OM uint32_t MR20IC : 1; /*!< [20..20] MR20IF clear bit */ + __OM uint32_t MR21IC : 1; /*!< [21..21] MR21IF clear bit */ + __OM uint32_t MR22IC : 1; /*!< [22..22] MR22IF clear bit */ + __OM uint32_t MR23IC : 1; /*!< [23..23] MR23IF clear bit */ + __OM uint32_t MR24IC : 1; /*!< [24..24] MR24IF clear bit */ + uint32_t : 7; + } IC_b; + } ; +} SN_CT16B1_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SN_SPI0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SPI0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI0 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI0 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI0 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI0 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI0 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI0 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI0 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI0 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI0 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI0 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI0 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; +} SN_SPI0_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI1 (SN_SPI1) + */ + +typedef struct { /*!< (@ 0x40058000) SN_SPI1 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI1 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + __IOM uint32_t ATEN : 1; /*!< [19..19] Auto Transmit enable bit */ + uint32_t : 12; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI1 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI1 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI1 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI1 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + __IM uint32_t AT_STATUS : 1; /*!< [7..7] Auto Transmit Status H/W flag */ + uint32_t : 24; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI1 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + __IOM uint32_t ATIE : 1; /*!< [4..4] Auto Transmit interrupt enable */ + uint32_t : 27; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI1 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + __IM uint32_t ATIF : 1; /*!< [4..4] Auto Transmit interrupt flag */ + uint32_t : 27; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI1 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + __OM uint32_t ATIC : 1; /*!< [4..4] Auto Transmit Interrupt flag Clear */ + uint32_t : 27; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI1 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI1 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI1 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x00000024) Offset:0x24 SPI1 Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 8; /*!< [9..2] SPI1 SRAM address to be read or written from/to SPI SRAM */ + uint32_t : 22; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x00000028) Offset:0x28 SPI1 Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to SPI SRAM */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x0000002C) Offset:0x2C SPI1 Number of Data Transfer Register */ + + struct { + __IOM uint32_t CNT : 10; /*!< [9..0] Number of times (CNT+1) to be transferred */ + uint32_t : 22; + } CNT_b; + } ; +} SN_SPI1_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*32*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (SN_UART0) + */ + +typedef struct { /*!< (@ 0x40016000) SN_UART0 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 27; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 28; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t IRDACTRL; /*!< (@ 0x00000024) Offset:0x24 USARTn IrDA Control Register */ + + struct { + uint32_t : 2; + __IOM uint32_t FIXPULSEEN : 1; /*!< [2..2] IrDA fix pulse width mode enable */ + __IOM uint32_t PULSEDIV : 3; /*!< [5..3] Pulse width selection */ + uint32_t : 26; + } IRDACTRL_b; + } ; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic Redundancy Check (SN_CRC) + */ + +typedef struct { /*!< (@ 0x40038000) SN_CRC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 CRC Control Register */ + + struct { + __IOM uint32_t CRC : 2; /*!< [1..0] CRC Polynomial */ + __IOM uint32_t RESET : 1; /*!< [2..2] CRC Reset bit */ + __IOM uint32_t URCRCEN : 1; /*!< [3..3] CRC calculation for the User ROM enable bit */ + __IM uint32_t BUSY : 1; /*!< [4..4] CRC calculation busy flag */ + uint32_t : 27; + } CTRL_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000004) Offset:0x4 CRC Data Register */ + + struct { + __IOM uint32_t DATA : 32; /*!< [31..0] CRC Data */ + } DATA_b; + } ; +} SN_CRC_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 6; /*!< [5..0] Flash Low Power mode selection bit */ + uint32_t : 10; + __OM uint32_t FMCKEY : 16; /*!< [31..16] FMC verify key */ + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t ERR : 1; /*!< [2..2] Erase/Error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program mode chosen bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase mode chosen bit */ + __IOM uint32_t MER : 1; /*!< [2..2] Mass erase mode chosen bit */ + uint32_t : 3; + __IOM uint32_t START : 1; /*!< [6..6] Start erase/program operation */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation chosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + + union { + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ + + struct { + __IM uint32_t UserROM : 16; /*!< [15..0] Checksum of User ROM */ + __IM uint32_t BootROM : 16; /*!< [31..16] Checksum of Boot ROM */ + } CHKSUM_b; + } ; + + union { + __IM uint32_t CHKSUM1; /*!< (@ 0x00000018) Offset:0x18 Flash Checksum Register 1 */ + + struct { + __IM uint32_t UserROM1 : 16; /*!< [15..0] Checksum of User ROM 1 */ + __IM uint32_t UserROM2 : 16; /*!< [31..16] Checksum of User ROM 2 */ + } CHKSUM1_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t WP; /*!< (@ 0x00000020) Offset:0x20 Flash Write Protect Register */ + + struct { + __IOM uint32_t WP : 16; /*!< [15..0] Flash Write protect key */ + uint32_t : 16; + } WP_b; + } ; +} SN_FLASH_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EP5_NAK_EN : 1; /*!< [4..4] EP5 NAK Interrupt Enable */ + __IOM uint32_t EP6_NAK_EN : 1; /*!< [5..5] EP6 NAK Interrupt Enable */ + __IOM uint32_t EP7_NAK_EN : 1; /*!< [6..6] EP7 NAK Interrupt Enable */ + __IOM uint32_t EPN_ACK_EN : 1; /*!< [7..7] EPN ACK Interrupt Enable */ + uint32_t : 20; + __IOM uint32_t BUSWK_IE : 1; /*!< [28..28] USB Bus Wake Up Interrupt Enable */ + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + __IM uint32_t EP5_NAK : 1; /*!< [4..4] Endpoint 5 NAK transaction flag */ + __IM uint32_t EP6_NAK : 1; /*!< [5..5] Endpoint 6 NAK transaction flag */ + __IM uint32_t EP7_NAK : 1; /*!< [6..6] Endpoint 7 NAK transaction flag */ + uint32_t : 1; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + __IM uint32_t EP5_ACK : 1; /*!< [12..12] Endpoint 5 ACK transaction flag */ + __IM uint32_t EP6_ACK : 1; /*!< [13..13] Endpoint 6 ACK transaction flag */ + __IM uint32_t EP7_ACK : 1; /*!< [14..14] Endpoint 7 ACK transaction flag */ + uint32_t : 2; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + __IM uint32_t BUS_WAKEUP : 1; /*!< [25..25] Bus Wakeup Flag */ + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + __OM uint32_t EP5_NAKC : 1; /*!< [4..4] EP5 NAK clear bit */ + __OM uint32_t EP6_NAKC : 1; /*!< [5..5] EP6 NAK clear bit */ + __OM uint32_t EP7_NAKC : 1; /*!< [6..6] EP7 NAK clear bit */ + uint32_t : 1; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + __OM uint32_t EP5_ACKC : 1; /*!< [12..12] EP5 ACK clear bit */ + __OM uint32_t EP6_ACKC : 1; /*!< [13..13] EP6 ACK clear bit */ + __OM uint32_t EP7_ACKC : 1; /*!< [14..14] EP7 ACK clear bit */ + uint32_t : 2; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + __IOM uint32_t EP5_DIR : 1; /*!< [4..4] Endpoint 5 IN/OUT direction setting */ + __IOM uint32_t EP6_DIR : 1; /*!< [5..5] Endpoint 6 IN/OUT direction setting */ + __IOM uint32_t EP7_DIR : 1; /*!< [6..6] Endpoint 7 IN/OUT direction setting */ + uint32_t : 19; + __IOM uint32_t DIS_PDEN : 1; /*!< [26..26] Enable internal D+ and D- 175k pull-down resistor */ + __IOM uint32_t ESD_EN : 1; /*!< [27..27] Enable USB anti-ESD protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + + union { + __IOM uint32_t EP5CTL; /*!< (@ 0x0000002C) Offset:0x2C USB Endpoint 5 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 5 Function enable bit */ + } EP5CTL_b; + } ; + + union { + __IOM uint32_t EP6CTL; /*!< (@ 0x00000030) Offset:0x30 USB Endpoint 6 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 6 Function enable bit */ + } EP6CTL_b; + } ; + + union { + __IOM uint32_t EP7CTL; /*!< (@ 0x00000034) Offset:0x34 USB Endpoint 7 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 7 Function enable bit */ + } EP7CTL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + __IOM uint32_t ENDP5_DATA01 : 1; /*!< [4..4] Endpoint 5 data toggle bit */ + __IOM uint32_t ENDP6_DATA01 : 1; /*!< [5..5] Endpoint 6 data toggle bit */ + __IOM uint32_t ENDP7_DATA01 : 1; /*!< [6..6] Endpoint 7 data toggle bit */ + uint32_t : 25; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP4BUFOS_b; + } ; + + union { + __IOM uint32_t EP5BUFOS; /*!< (@ 0x00000058) Offset:0x58 USB Endpoint 5 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP5BUFOS_b; + } ; + + union { + __IOM uint32_t EP6BUFOS; /*!< (@ 0x0000005C) Offset:0x5C USB Endpoint 6 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP6BUFOS_b; + } ; + + union { + __IOM uint32_t EP7BUFOS; /*!< (@ 0x00000060) Offset:0x60 USB Endpoint 7 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP7BUFOS_b; + } ; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000064) Offset:0x64 USB Frame Number Register */ + + struct { + __IM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000068) Offset:0x68 USB PHY Parameter Register */ + + struct { + __IOM uint32_t PHY_PARAM : 6; /*!< [5..0] USB PHY parameter */ + uint32_t : 26; + } PHYPRM_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t PHYPRM2; /*!< (@ 0x00000070) Offset:0x70 USB PHY Parameter Register 2 */ + + struct { + __IOM uint32_t PHY_PS : 15; /*!< [14..0] USB PHY parameter 2 */ + uint32_t : 17; + } PHYPRM2_b; + } ; + + union { + __IOM uint32_t PS2CTL; /*!< (@ 0x00000074) Offset:0x74 PS/2 Control Register */ + + struct { + __IOM uint32_t SCKM : 1; /*!< [0..0] PS/2 SCK mode control bit */ + __IOM uint32_t SDAM : 1; /*!< [1..1] PS/2 SDA mode control bit */ + __IOM uint32_t SCK : 1; /*!< [2..2] PS/2 SCK data buffer */ + __IOM uint32_t SDA : 1; /*!< [3..3] PS/2 SDA data buffer */ + uint32_t : 27; + __IOM uint32_t PS2ENB : 1; /*!< [31..31] PS/2 internal 5k ohm pull-up resistor control bit */ + } PS2CTL_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t RWSTATUS; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Status Register */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS_b; + } ; + + union { + __IOM uint32_t RWADDR2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Address Register 2 */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR2_b; + } ; + + union { + __IOM uint32_t RWDATA2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Data Register 2 */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA2_b; + } ; + + union { + __IOM uint32_t RWSTATUS2; /*!< (@ 0x00000090) Offset:0x90 USB Read/Write Status Register 2 */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS2_b; + } ; +} SN_USB_Type; /*!< Size = 148 (0x94) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2508) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t RESERVED; + __IM uint32_t H4BYTE; /*!< (@ 0x00000008) Offset:0x08 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_PFPA_BASE 0x40042000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_ADC_BASE 0x40026000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_SPI0_BASE 0x4001C000UL +#define SN_SPI1_BASE 0x40058000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_I2C1_BASE 0x4005A000UL +#define SN_UART0_BASE 0x40016000UL +#define SN_UART1_BASE 0x40014000UL +#define SN_UART2_BASE 0x40012000UL +#define SN_CRC_BASE 0x40038000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_UC_BASE 0x1FFF2508UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_PFPA ((SN_PFPA_Type*) SN_PFPA_BASE) +#define SN_GPIO1 ((SN_GPIO1_Type*) SN_GPIO1_BASE) +#define SN_GPIO2 ((SN_GPIO2_Type*) SN_GPIO2_BASE) +#define SN_GPIO3 ((SN_GPIO3_Type*) SN_GPIO3_BASE) +#define SN_GPIO0 ((SN_GPIO0_Type*) SN_GPIO0_BASE) +#define SN_ADC ((SN_ADC_Type*) SN_ADC_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B1_Type*) SN_CT16B1_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_SPI0 ((SN_SPI0_Type*) SN_SPI0_BASE) +#define SN_SPI1 ((SN_SPI1_Type*) SN_SPI1_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_I2C1 ((SN_I2C0_Type*) SN_I2C1_BASE) +#define SN_UART0 ((SN_UART0_Type*) SN_UART0_BASE) +#define SN_UART1 ((SN_UART0_Type*) SN_UART1_BASE) +#define SN_UART2 ((SN_UART0_Type*) SN_UART2_BASE) +#define SN_CRC ((SN_CRC_Type*) SN_CRC_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F240C_H */ + + +/** @} */ /* End of group SN32F240C */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h b/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h index 402a2ecaf6..7662bec5e3 100644 --- a/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h +++ b/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h @@ -20,11 +20,12 @@ application */ -#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F260) \ - && !defined (SN32F280) && !defined (SN32F290) +#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F240C) \ + && !defined (SN32F260) && !defined (SN32F280) && !defined (SN32F290) /* #define SN32F230 */ /*!< SN32F239, SN32F238, SN32F237, SN32F236,and SN32F235 Devices */ /* #define SN32F240 */ /*!< SN32F249, SN32F248, SN32F247, SN32F246 and SN32F245 Devices */ /* #define SN32F240B */ /*!< SN32F248B, SN32F247B, SN32F246B and SN32F2451B Devices */ + /* #define SN32F240C */ /*!< SN32F248C, SN32F247C, SN32F246C and SN32F2451C Devices */ /* #define SN32F260 */ /*!< SN32F268, SN32F267, SN32F265, SN32F2641, SN32F264 and SN32F263 Devices */ /* #define SN32F280 */ /*!< SN32F289, SN32F288 and SN32F287 Devices */ @@ -40,6 +41,8 @@ #include "SN32F240.h" #elif defined(SN32F240B) #include "SN32F240B.h" +#elif defined(SN32F240C) + #include "SN32F240C.h" #elif defined(SN32F260) #include "SN32F260.h" #elif defined(SN32F280) diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c index e2bc8a1da7..03ef314ede 100644 --- a/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c @@ -22,12 +22,10 @@ * ******************************************************************************/ - #include #include #include - /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ @@ -92,136 +90,142 @@ */ #ifndef SYS_CLOCK_SETUP -#define SYS_CLOCK_SETUP 1 +#define SYS_CLOCK_SETUP 1 #endif #ifndef SYS0_CLKCFG_VAL -#define SYS0_CLKCFG_VAL 0 +#define SYS0_CLKCFG_VAL PLL #endif #ifndef EHS_FREQ -#define EHS_FREQ 10 +#define EHS_FREQ 12 #endif #ifndef PLL_MSEL -#define PLL_MSEL 12 +#define PLL_MSEL 24 #endif #ifndef PLL_PSEL -#define PLL_PSEL 3 +#define PLL_PSEL 3 #endif #ifndef PLL_FSEL -#define PLL_FSEL 0 +#define PLL_FSEL 0 #endif #ifndef PLL_CLKIN -#define PLL_CLKIN 1 +#define PLL_CLKIN 0 #endif #ifndef PLL_ENABLE -#define PLL_ENABLE 0 +#define PLL_ENABLE 1 #endif #ifndef AHB_PRESCALAR -#define AHB_PRESCALAR 0x0 +#define AHB_PRESCALAR 0x0 #endif #ifndef CLKOUT_SEL_VAL -#define CLKOUT_SEL_VAL 0x0 +#define CLKOUT_SEL_VAL 0x0 #endif /* //-------- <<< end of configuration section >>> ------------------------------ */ - /*---------------------------------------------------------------------------- - DEFINES + Defines *----------------------------------------------------------------------------*/ -#ifndef IHRC -#define IHRC 0 -#endif -#ifndef ILRC -#define ILRC 1 -#endif -#ifndef EHSXTAL -#define EHSXTAL 2 -#endif -#ifndef ELSXTAL -#define ELSXTAL 3 -#endif -#ifndef PLL -#define PLL 4 -#endif +#define IHRC 0 +#define ILRC 1 +#define EHSXTAL 2 +#define ELSXTAL 3 +#define PLL 4 /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ -#define __IHRC_FREQ (12000000UL) -#define __ILRC_FREQ (32000UL) -#define __ELS_XTAL_FREQ (32768UL) +#define __IHRC_FREQ (12000000UL) +#define __ILRC_FREQ (32000UL) +#define __ELS_XTAL_FREQ (32768UL) #if (SYS_CLOCK_SETUP) -#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_FSEL<<8) | (PLL_PSEL<<5) | PLL_MSEL +#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_FSEL<<8) | (PLL_PSEL<<5) | PLL_MSEL #endif /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ - +uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock).*/ /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ +void SystemCoreClockUpdate (void) { /* Get Core Clock Frequency.*/ uint32_t AHB_prescaler = 0; uint32_t F; - switch (SN_SYS0->CLKCFG_b.SYSCLKST) - { - case 0: //IHRC + switch (SN_SYS0->CLKCFG_b.SYSCLKST) { + case 0: /* IHRC clock.*/ SystemCoreClock = __IHRC_FREQ; break; - case 1: //ILRC + case 1: /* ILRC clock.*/ SystemCoreClock = __ILRC_FREQ; break; - case 2: //EHS X'TAL -#if (SYS_CLOCK_SETUP) - SystemCoreClock = EHS_FREQ * 1000000; -#else - //TODO: User had to assign EHS X'TAL frequency. - SystemCoreClock = 10000000UL / AHB_prescaler; -#endif + case 2: /* EHS X'TAL clock.*/ + #if (SYS_CLOCK_SETUP) + SystemCoreClock = EHS_FREQ * 1000000; + #else + //TODO: User had to assign EHS X'TAL frequency. + SystemCoreClock = 10000000UL / AHB_prescaler; + #endif break; - case 3: //ELS X'TAL + case 3: /* ELS X'TAL clock.*/ SystemCoreClock = __ELS_XTAL_FREQ; break; - case 4: //PLL -#if (SYS_CLOCK_SETUP) - if (PLL_FSEL == 0) - F = 1; - else - F = 2; - if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN - SystemCoreClock = __IHRC_FREQ / F * PLL_MSEL / PLL_PSEL /2; - else - SystemCoreClock = EHS_FREQ * 1000000 / F * PLL_MSEL / PLL_PSEL /2; -#else - //TODO: User had to assign PLL output frequency. - SystemCoreClock = 50000000UL; -#endif + case 4: /* PLL clock.*/ + #if (SYS_CLOCK_SETUP) + if (PLL_FSEL == 0) + F = 1; + else + F = 2; + if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN + SystemCoreClock = __IHRC_FREQ / F * PLL_MSEL / PLL_PSEL /2; + else + SystemCoreClock = EHS_FREQ * 1000000 / F * PLL_MSEL / PLL_PSEL /2; + #else + //TODO: User had to assign PLL output frequency. + SystemCoreClock = 50000000UL; + #endif break; default: break; } - switch (SN_SYS0->AHBCP) - { - case 0: AHB_prescaler = 1; break; - case 1: AHB_prescaler = 2; break; - case 2: AHB_prescaler = 4; break; - case 3: AHB_prescaler = 8; break; - case 4: AHB_prescaler = 16; break; - case 5: AHB_prescaler = 32; break; - case 6: AHB_prescaler = 64; break; - case 7: AHB_prescaler = 128;break; - case 8: AHB_prescaler = 256;break; - case 9: AHB_prescaler = 512;break; - default: break; + switch (SN_SYS0->AHBCP) { + case 0: + AHB_prescaler = 1; + break; + case 1: + AHB_prescaler = 2; + break; + case 2: + AHB_prescaler = 4; + break; + case 3: + AHB_prescaler = 8; + break; + case 4: + AHB_prescaler = 16; + break; + case 5: + AHB_prescaler = 32; + break; + case 6: + AHB_prescaler = 64; + break; + case 7: + AHB_prescaler = 128; + break; + case 8: + AHB_prescaler = 256; + break; + case 9: + AHB_prescaler = 512; + break; + default: + break; } SystemCoreClock /= AHB_prescaler; @@ -238,63 +242,65 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) -{ +void SystemInit (void) { + SN_FLASH->LPCTRL = 0x5AFA0000; /* Disable Slow mode power saving.*/ #if (SYS_CLOCK_SETUP) + #if (SYS0_CLKCFG_VAL == IHRC) /* IHRC clock.*/ + SN_SYS0->ANBCTRL |= (1<<0); /* Enable IHRC.*/ + while ((SN_SYS0->CSST & 0x01) != 0x01); /* Check IHRC ready.*/ + SN_SYS0->CLKCFG = 0x00; + while ((SN_SYS0->CLKCFG & 0x70) != 0x00); /* Switch IHRC.*/ + #endif -#if SYS0_CLKCFG_VAL == IHRC //IHRC + #if (SYS0_CLKCFG_VAL == ILRC) /* ILRC clock.*/ + SN_SYS0->CLKCFG = 0x01; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); /* Switch ILRC.*/ + #endif -#endif + #if (SYS0_CLKCFG_VAL == EHSXTAL) /* EHS XTAL clock.*/ + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); /* Enable XTAL > 12MHz.*/ + #else + SN_SYS0->ANBCTRL &=~(1<<5); /* Enable XTAL <= 12MHz.*/ + #endif -#if SYS0_CLKCFG_VAL == ILRC //ILRC - SN_SYS0->CLKCFG = 0x1; - while ((SN_SYS0->CLKCFG & 0x70) != 0x10); -#endif + SN_SYS0->ANBCTRL |= (1<<4); /* Enable EHS XTAL.*/ + while ((SN_SYS0->CSST & 0x10) != 0x10); /* Check EHS XTAL ready.*/ + SN_SYS0->CLKCFG = 0x02; + while ((SN_SYS0->CLKCFG & 0x70) != 0x20); /* Switch EHS XTAL.*/ + #endif -#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL - #if (EHS_FREQ > 12) - SN_SYS0->ANBCTRL |= (1<<5); - #else - SN_SYS0->ANBCTRL &=~(1<<5); - #endif - SN_SYS0->ANBCTRL |= (1<<4); - while ((SN_SYS0->CSST & 0x10) != 0x10); - SN_SYS0->CLKCFG = 0x2; - while ((SN_SYS0->CLKCFG & 0x70) != 0x20); -#endif + #if (SYS0_CLKCFG_VAL == ELSXTAL) /* ELS XTAL clock.*/ + SN_SYS0->ANBCTRL |= (1<<2); /* Enable ELS XTAL.*/ + while ((SN_SYS0->CSST & 0x04) != 0x04); /* Check ELS XTAL ready.*/ + SN_SYS0->CLKCFG = 0x03; + while ((SN_SYS0->CLKCFG & 0x70) != 0x30); /* Switch ELS XTAL.*/ + #endif -#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL - SN_SYS0->ANBCTRL |=0x04; - while((SN_SYS0->CSST & 0x4) != 0x4); - SN_SYS0->CLKCFG = 0x3; - while ((SN_SYS0->CLKCFG & 0x70) != 0x30); -#endif + #if (SYS0_CLKCFG_VAL == PLL) /* PLL clock.*/ + SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; /* Enable PLL.*/ -#if (SYS0_CLKCFG_VAL == PLL) //PLL - SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; - if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN - { - //Enable EHS - #if (EHS_FREQ > 12) - SN_SYS0->ANBCTRL |= (1<<5); - #else - SN_SYS0->ANBCTRL &=~(1<<5); - #endif - SN_SYS0->ANBCTRL |= (1<<4); - while ((SN_SYS0->CSST & 0x10) != 0x10); - } + if (PLL_CLKIN == 0x01) { /* EHS XTAL as F_CLKIN.*/ + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); /* Enable XTAL > 12MHz.*/ + #else + SN_SYS0->ANBCTRL &=~(1<<5); /* Enable XTAL <= 12MHz.*/ + #endif - while ((SN_SYS0->CSST & 0x40) != 0x40); - SN_SYS0->CLKCFG = 0x4; - while ((SN_SYS0->CLKCFG & 0x70) != 0x40); -#endif + SN_SYS0->ANBCTRL |= (1<<4); /* Enable EHS XTAL.*/ + while ((SN_SYS0->CSST & 0x10) != 0x10); /* Check EHS XTAL ready.*/ + } - SN_SYS0->AHBCP = AHB_PRESCALAR; + while ((SN_SYS0->CSST & 0x40) != 0x40); /* Check PLL ready.*/ + SN_SYS0->CLKCFG = 0x04; + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); /* Switch PLL.*/ + #endif -#if (CLKOUT_SEL_VAL > 0) //CLKOUT - SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL; -#endif -#endif //(SYS_CLOCK_SETUP) + SN_SYS0->AHBCP_b.AHBPRE = AHB_PRESCALAR; -} \ No newline at end of file + #if (CLKOUT_SEL_VAL > 0) /* CLKOUT value.*/ + sys1EnableCLKOUT(CLKOUT_SEL_VAL); + #endif +#endif //(SYS_CLOCK_SETUP) +} diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F240C.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F240C.c new file mode 100644 index 0000000000..0d31634bb1 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F240C.c @@ -0,0 +1,257 @@ +/****************************************************************************** + * @file system_SN32F240C.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F240C Devices + * @version V1.0.0 + * @date 2021/09/02 + * + * @note + * Copyright (C) 2020-2024 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include +#include + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC +// <1=> ILRC +// <4=> PLL +// +// +// PLL ENABLE +// PLL Control Register (SYS0_PLLCTRL) +// F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P +// 10 MHz <= F_CLKIN <= 25 MHz +// 96 MHz <= (F_CLKIN * M) <= 144 MHz +// MSEL +// <0=> M = 4 +// <1=> M = 6 +// <2=> M = 8 +// <3=> M = 10 +// <4=> M = 12 +// PSEL +// <0=> P = 2 +// <1=> P = 4 +// +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// SYSCLK prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/1.5 +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <4=> HCLK +// <5=> IHRC +// <7=> PLL +// CLKOUT Prescaler Register (SYS1_APBCP1) +// <0=> CLKOUT selection/1 +// <1=> CLKOUT selection/2 +// <2=> CLKOUT selection/4 +// <3=> CLKOUT selection/8 +// <4=> CLKOUT selection/16 +// <5=> CLKOUT selection/32 +// <6=> CLKOUT selection/64 +// <7=> CLKOUT selection/128 +*/ + +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 4 +#endif +#ifndef PLL_ENABLE +#define PLL_ENABLE 1 +#endif +#ifndef PLL_MSEL +#define PLL_MSEL 2 +#endif +#ifndef PLL_PSEL +#define PLL_PSEL 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef AHB_1P5PRESCALAR +#define AHB_1P5PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif +#ifndef CLKOUT_PRESCALAR +#define CLKOUT_PRESCALAR 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC +#define IHRC 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif +#ifndef PLL +#define PLL 4 +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC_FREQ (12000000UL) +#define __ILRC_FREQ (32000UL) + +#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_PSEL<<5) | PLL_MSEL + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler = 0; + + switch (SN_SYS0->CLKCFG_b.SYSCLKST) + { + case 0: //IHRC + SystemCoreClock = __IHRC_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + case 4: //PLL + SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1); + break; + default: + break; + } + + switch (SN_SYS0->AHBCP_b.AHBPRE) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; +} +/** + * Initialize the Flash controller + * + * @param none + * @return none + * + * @brief Update the Flash power control. + */ +void FlashClockUpdate (void) +{ + + //;;;;;;;;; Need for SN32F240C Begin ;;;;;;;;; + if (SystemCoreClock > 48000000) + SN_FLASH->LPCTRL = 0x5AFA0039; + else if (SystemCoreClock >= 24000000) + SN_FLASH->LPCTRL = 0x5AFA0029; + else //Slow mode required for SystemCoreClock <= 24000000 + SlowModeSwitch(); + //;;;;;;;;; Need for SN32F240C End ;;;;;;;;; +} + +/** + * Switch System to Slow Mode + * @param none + * @return none + * + * @brief Special init required for SystemCoreClock <= 24000000 + */ +void SlowModeSwitch (void) +{ + SN_SYS0->CLKCFG_b.SYSCLKSEL = 0; //Switch to IHRC + SystemCoreClockUpdate(); + SN_FLASH->LPCTRL = 0x5AFA0000; +} +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if SYS0_CLKCFG_VAL == IHRC //IHRC + SN_SYS0->CLKCFG = 0x0; + while ((SN_SYS0->CLKCFG & 0x70) != 0x0); + #endif + + #if SYS0_CLKCFG_VAL == ILRC //ILRC + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); + #endif + + #if (PLL_ENABLE == 1) + SN_FLASH->LPCTRL = 0x5AFA0039; + SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; + while ((SN_SYS0->CSST & 0x40) != 0x40); + #if (SYS0_CLKCFG_VAL == PLL) //PLL + SN_SYS0->CLKCFG = 0x4; + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); + #endif + #endif + + SN_SYS0->AHBCP = AHB_PRESCALAR; + + #if (CLKOUT_SEL_VAL > 0) //CLKOUT + SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL; + SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR; + #endif +} diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c index d68c488123..6116a7287f 100644 --- a/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c @@ -96,16 +96,16 @@ #ifndef SYS0_CLKCFG_VAL -#define SYS0_CLKCFG_VAL 0 +#define SYS0_CLKCFG_VAL 4 #endif #ifndef EHS_FREQ #define EHS_FREQ 16 #endif #ifndef PLL_ENABLE -#define PLL_ENABLE 0 +#define PLL_ENABLE 1 #endif #ifndef PLL_MSEL -#define PLL_MSEL 1 +#define PLL_MSEL 2 #endif #ifndef PLL_PSEL #define PLL_PSEL 0 @@ -171,7 +171,7 @@ uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ { - uint32_t AHB_prescaler; + uint32_t AHB_prescaler = 0; switch (SN_SYS0->CLKCFG_b.SYSCLKST) { @@ -214,17 +214,41 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ if (SN_SYS0->AHBCP_b.DIV1P5 == 1) SystemCoreClock = SystemCoreClock*2/3; +} + +/** + * Initialize the Flash controller + * + * @param none + * @return none + * + * @brief Update the Flash power control. + */ +void FlashClockUpdate (void) +{ //;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;; if (SystemCoreClock > 48000000) - SN_FLASH->LPCTRL = 0x5AFA0031; + SN_FLASH->LPCTRL = 0x5AFA0039; else if (SystemCoreClock > 24000000) - SN_FLASH->LPCTRL = 0x5AFA0011; - else - SN_FLASH->LPCTRL = 0x5AFA0000; + SN_FLASH->LPCTRL = 0x5AFA0029; + else //Slow mode required for SystemCoreClock <= 24000000 + SlowModeSwitch(); //;;;;;;;;; Need for SN32F780 End ;;;;;;;;; +} - return; +/** + * Switch System to Slow Mode + * @param none + * @return none + * + * @brief Special init required for SystemCoreClock <= 24000000 + */ +void SlowModeSwitch (void) +{ + SN_SYS0->CLKCFG_b.SYSCLKSEL = 0; //Switch to IHRC + SystemCoreClockUpdate(); + SN_FLASH->LPCTRL = 0x5AFA0000; } /** @@ -251,7 +275,7 @@ void SystemInit (void) #if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL #if (EHS_FREQ > 12) SN_SYS0->ANBCTRL_b.EHSFREQ = 1; - SN_FLASH->LPCTRL = 0x5AFA0011; + SN_FLASH->LPCTRL = 0x5AFA0039; #else SN_SYS0->ANBCTRL_b.EHSFREQ = 0; #endif @@ -269,6 +293,7 @@ void SystemInit (void) #endif #if (PLL_ENABLE == 1) + SN_FLASH->LPCTRL = 0x5AFA0039; SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN { @@ -283,7 +308,6 @@ void SystemInit (void) } while ((SN_SYS0->CSST & 0x40) != 0x40); #if (SYS0_CLKCFG_VAL == PLL) //PLL - SN_FLASH->LPCTRL = 0x5AFA0031; SN_SYS0->CLKCFG = 0x4; while ((SN_SYS0->CLKCFG & 0x70) != 0x40); #endif diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c index 5b91a1ac94..54a4a5f181 100644 --- a/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c @@ -95,16 +95,16 @@ */ #ifndef SYS0_CLKCFG_VAL -#define SYS0_CLKCFG_VAL 0 +#define SYS0_CLKCFG_VAL 4 #endif #ifndef EHS_FREQ #define EHS_FREQ 16 #endif #ifndef PLL_ENABLE -#define PLL_ENABLE 0 +#define PLL_ENABLE 1 #endif #ifndef PLL_MSEL -#define PLL_MSEL 1 +#define PLL_MSEL 2 #endif #ifndef PLL_PSEL #define PLL_PSEL 0 @@ -170,7 +170,7 @@ uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ { - uint32_t AHB_prescaler; + uint32_t AHB_prescaler = 0; switch (SN_SYS0->CLKCFG_b.SYSCLKST) { @@ -213,17 +213,41 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ if (SN_SYS0->AHBCP_b.DIV1P5 == 1) SystemCoreClock = SystemCoreClock*2/3; +} + +/** + * Initialize the Flash controller + * + * @param none + * @return none + * + * @brief Update the Flash power control. + */ +void FlashClockUpdate (void) +{ //;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;; if (SystemCoreClock > 48000000) - SN_FLASH->LPCTRL = 0x5AFA0031; + SN_FLASH->LPCTRL = 0x5AFA0039; else if (SystemCoreClock > 24000000) - SN_FLASH->LPCTRL = 0x5AFA0011; - else - SN_FLASH->LPCTRL = 0x5AFA0000; + SN_FLASH->LPCTRL = 0x5AFA0029; + else //Slow mode required for SystemCoreClock <= 24000000 + SlowModeSwitch(); //;;;;;;;;; Need for SN32F780 End ;;;;;;;;; +} - return; +/** + * Switch System to Slow Mode + * @param none + * @return none + * + * @brief Special init required for SystemCoreClock <= 24000000 + */ +void SlowModeSwitch (void) +{ + SN_SYS0->CLKCFG_b.SYSCLKSEL = 0; //Switch to IHRC + SystemCoreClockUpdate(); + SN_FLASH->LPCTRL = 0x5AFA0000; } /** @@ -250,7 +274,7 @@ void SystemInit (void) #if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL #if (EHS_FREQ > 12) SN_SYS0->ANBCTRL_b.EHSFREQ = 1; - SN_FLASH->LPCTRL = 0x5AFA0011; + SN_FLASH->LPCTRL = 0x5AFA0039; #else SN_SYS0->ANBCTRL_b.EHSFREQ = 0; #endif @@ -268,6 +292,7 @@ void SystemInit (void) #endif #if (PLL_ENABLE == 1) + SN_FLASH->LPCTRL = 0x5AFA0039; SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN { @@ -282,7 +307,6 @@ void SystemInit (void) } while ((SN_SYS0->CSST & 0x40) != 0x40); #if (SYS0_CLKCFG_VAL == PLL) //PLL - SN_FLASH->LPCTRL = 0x5AFA0031; SN_SYS0->CLKCFG = 0x4; while ((SN_SYS0->CLKCFG & 0x70) != 0x40); #endif diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h b/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h index 30c2735020..f937e254ed 100644 --- a/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h @@ -56,7 +56,7 @@ extern void SystemInit (void); * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); -#if defined(SN32F240B) +#if (defined(SN32F240B) || defined(SN32F240C) || defined(SN32F280) || defined(SN32F290)) /** * Initialize the Flash controller * @@ -72,10 +72,10 @@ extern void FlashClockUpdate (void); * @param none * @return none * - * @brief Special init required for SystemCoreClock <= 8000 + * @brief Special init required for slow SystemCoreClock */ extern void SlowModeSwitch (void); -#endif /* defined(SN32F240B) */ +#endif /* defined(SN32F240B) || defined(SN32F240C) || defined(SN32F280) || defined(SN32F290) */ #ifdef __cplusplus } diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240C.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240C.ld new file mode 100644 index 0000000000..e933c45e0d --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240C.ld @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F240C memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + + +_flag_start = 0x1FFFC; + +SECTIONS +{ + .flag _flag_start : + { + KEEP(*(.flag)) ; + } > flash0 +} diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld index 60142cfd1e..843248daff 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld @@ -85,7 +85,7 @@ REGION_ALIAS("HEAP_RAM", ram0); INCLUDE rules.ld -_flag_start = 0xFFFC; +_flag_start = 0x1FFFC; SECTIONS { diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld index 17f7517e7e..08cc81ccb6 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld @@ -85,7 +85,7 @@ REGION_ALIAS("HEAP_RAM", ram0); INCLUDE rules.ld -_flag_start = 0xFFFC; +_flag_start = 0x3FFFC; SECTIONS { diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xc.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xc.mk new file mode 100644 index 0000000000..da5af94108 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xc.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F24xC startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240C.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24xC \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/devices/SN32F24xC/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F24xC/cmparams.h new file mode 100644 index 0000000000..0c4e18c0d2 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F24xC/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F24xC/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F24xC. + * + * @defgroup ARMCMx_SN32F24xC SN32F24xC Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F24xC platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F240C.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/hal/boards/SN_SN32F240/board.c b/os/hal/boards/SN_SN32F240/board.c index b1715ea6b2..802d141829 100644 --- a/os/hal/boards/SN_SN32F240/board.c +++ b/os/hal/boards/SN_SN32F240/board.c @@ -61,7 +61,3 @@ void __early_init(void) { void boardInit(void) { } - -void restart_usb_driver(USBDriver *usbp) { - // Do nothing. Restarting the USB driver on these boards breaks it. -} diff --git a/os/hal/boards/SN_SN32F240/board.h b/os/hal/boards/SN_SN32F240/board.h index 27f6f5e2ab..006091e0d5 100644 --- a/os/hal/boards/SN_SN32F240/board.h +++ b/os/hal/boards/SN_SN32F240/board.h @@ -114,6 +114,11 @@ // Define GPIO register values used by pal_default_config. // The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 16U +#define GPIOB_WIDTH 16U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 16U +#define PAL_IOPORTS_WIDTH 16U #define VAL_GPIOA_MODE \ ( PIN_MODE_INPUT(GPIOA_PIN0) \ diff --git a/os/hal/boards/SN_SN32F240/board.mk b/os/hal/boards/SN_SN32F240/board.mk index 7b974dda1b..f99dcbddd3 100644 --- a/os/hal/boards/SN_SN32F240/board.mk +++ b/os/hal/boards/SN_SN32F240/board.mk @@ -1,8 +1,8 @@ # List of all the board related files. -BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240/board.c # Required include directories -BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240 # Shared variables ALLCSRC += $(BOARDSRC) diff --git a/os/hal/boards/SN_SN32F240B/board.h b/os/hal/boards/SN_SN32F240B/board.h index 5904811f10..059b28d0ea 100644 --- a/os/hal/boards/SN_SN32F240B/board.h +++ b/os/hal/boards/SN_SN32F240B/board.h @@ -110,6 +110,11 @@ // Define GPIO register values used by pal_default_config. // The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 16U +#define GPIOB_WIDTH 16U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 16U +#define PAL_IOPORTS_WIDTH 16U #define VAL_GPIOA_MODE \ ( PIN_MODE_INPUT(GPIOA_PIN0) \ diff --git a/os/hal/boards/SN_SN32F240C/board.c b/os/hal/boards/SN_SN32F240C/board.c new file mode 100644 index 0000000000..bebefbef66 --- /dev/null +++ b/os/hal/boards/SN_SN32F240C/board.c @@ -0,0 +1,64 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + SN_FLASH->LPCTRL = 0x5AFA0031; //24 <= 48Mhz + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/SN_SN32F240C/board.h b/os/hal/boards/SN_SN32F240C/board.h new file mode 100644 index 0000000000..685796a6f9 --- /dev/null +++ b/os/hal/boards/SN_SN32F240C/board.h @@ -0,0 +1,255 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F240C Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F240C +#define BOARD_NAME "SN32F240C" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F240C + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 16U +#define GPIOB_WIDTH 16U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 16U +#define PAL_IOPORTS_WIDTH 16U + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) \ + | PIN_MODE_INPUT(GPIOB_PIN6) \ + | PIN_MODE_INPUT(GPIOB_PIN7) \ + | PIN_MODE_INPUT(GPIOB_PIN8) \ + | PIN_MODE_INPUT(GPIOB_PIN9) \ + | PIN_MODE_INPUT(GPIOB_PIN10) \ + | PIN_MODE_INPUT(GPIOB_PIN11) \ + | PIN_MODE_INPUT(GPIOB_PIN12) \ + | PIN_MODE_INPUT(GPIOB_PIN13) \ + | PIN_MODE_INPUT(GPIOB_PIN14) \ + | PIN_MODE_INPUT(GPIOB_PIN15) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) \ + | PIN_MODE_INPUT(GPIOC_PIN11) \ + | PIN_MODE_INPUT(GPIOC_PIN12) \ + | PIN_MODE_INPUT(GPIOC_PIN13) \ + | PIN_MODE_INPUT(GPIOC_PIN14) \ + | PIN_MODE_INPUT(GPIOC_PIN15) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN0) \ + | PIN_MODE_INPUT(GPIOD_PIN1) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) \ + | PIN_MODE_INPUT(GPIOD_PIN9) \ + | PIN_MODE_INPUT(GPIOD_PIN10) \ + | PIN_MODE_INPUT(GPIOD_PIN11) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN11) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F240C/board.mk b/os/hal/boards/SN_SN32F240C/board.mk new file mode 100644 index 0000000000..d013ad92b5 --- /dev/null +++ b/os/hal/boards/SN_SN32F240C/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240C/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240C + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/boards/SN_SN32F260/board.h b/os/hal/boards/SN_SN32F260/board.h index cb34734911..cf4d4220d6 100644 --- a/os/hal/boards/SN_SN32F260/board.h +++ b/os/hal/boards/SN_SN32F260/board.h @@ -95,6 +95,11 @@ // Define GPIO register values used by pal_default_config. // The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 16U +#define GPIOB_WIDTH 16U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 16U +#define PAL_IOPORTS_WIDTH 16U #define VAL_GPIOA_MODE \ ( PIN_MODE_INPUT(GPIOA_PIN0) \ diff --git a/os/hal/boards/SN_SN32F280/board.c b/os/hal/boards/SN_SN32F280/board.c index 802d141829..3e1dab278e 100644 --- a/os/hal/boards/SN_SN32F280/board.c +++ b/os/hal/boards/SN_SN32F280/board.c @@ -29,16 +29,16 @@ */ const PALConfig pal_default_config = { #if SN32_HAS_GPIOA - {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG, .cfg1 = VAL_GPIOA_CFG1}, #endif #if SN32_HAS_GPIOB - {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG, .cfg1 = VAL_GPIOB_CFG1}, #endif #if SN32_HAS_GPIOC {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, #endif #if SN32_HAS_GPIOD - {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG, .cfg1 = VAL_GPIOD_CFG1}, #endif }; #endif @@ -51,6 +51,11 @@ static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0x * and before any other initialization. */ void __early_init(void) { + SN_FLASH->LPCTRL = 0x5AFA0031; //24 <= 48Mhz + SN_SYS1->AHBCLKEN_b.LCDCLKEN =1; + SN_SYS1->AHBCLKEN_b.WDTCLKEN =1; + SN_LCD->CTRL_b.VLCD=1; + SN_SYS1->AHBCLKEN_b.LCDCLKEN =0; sn32_clock_init(); } diff --git a/os/hal/boards/SN_SN32F280/board.h b/os/hal/boards/SN_SN32F280/board.h index 57eb0ab8ac..06618f991b 100644 --- a/os/hal/boards/SN_SN32F280/board.h +++ b/os/hal/boards/SN_SN32F280/board.h @@ -24,7 +24,7 @@ /* * Board identifier. */ -#define BOARD_GENERIC_SN32_F240 +#define BOARD_GENERIC_SN32_F280 #define BOARD_NAME "SN32F280" /* @@ -124,6 +124,11 @@ // Define GPIO register values used by pal_default_config. // The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 20U +#define GPIOB_WIDTH 20U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 20U +#define PAL_IOPORTS_WIDTH 20U #define VAL_GPIOA_MODE \ ( PIN_MODE_INPUT(GPIOA_PIN0) \ @@ -162,11 +167,12 @@ | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOA_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN19) ) #define VAL_GPIOB_MODE \ ( PIN_MODE_INPUT(GPIOB_PIN0) \ @@ -205,11 +211,12 @@ | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) ) +#define VAL_GPIOB_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOB_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN19) ) #define VAL_GPIOC_MODE \ ( PIN_MODE_INPUT(GPIOC_PIN0) \ @@ -277,11 +284,12 @@ | PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) ) +#define VAL_GPIOD_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOD_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN19) ) #if !defined(_FROM_ASM_) # ifdef __cplusplus diff --git a/os/hal/boards/SN_SN32F290/board.c b/os/hal/boards/SN_SN32F290/board.c index 802d141829..3e1dab278e 100644 --- a/os/hal/boards/SN_SN32F290/board.c +++ b/os/hal/boards/SN_SN32F290/board.c @@ -29,16 +29,16 @@ */ const PALConfig pal_default_config = { #if SN32_HAS_GPIOA - {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG, .cfg1 = VAL_GPIOA_CFG1}, #endif #if SN32_HAS_GPIOB - {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG, .cfg1 = VAL_GPIOB_CFG1}, #endif #if SN32_HAS_GPIOC {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, #endif #if SN32_HAS_GPIOD - {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG, .cfg1 = VAL_GPIOD_CFG1}, #endif }; #endif @@ -51,6 +51,11 @@ static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0x * and before any other initialization. */ void __early_init(void) { + SN_FLASH->LPCTRL = 0x5AFA0031; //24 <= 48Mhz + SN_SYS1->AHBCLKEN_b.LCDCLKEN =1; + SN_SYS1->AHBCLKEN_b.WDTCLKEN =1; + SN_LCD->CTRL_b.VLCD=1; + SN_SYS1->AHBCLKEN_b.LCDCLKEN =0; sn32_clock_init(); } diff --git a/os/hal/boards/SN_SN32F290/board.h b/os/hal/boards/SN_SN32F290/board.h index 3a95eb7d25..e3e915f911 100644 --- a/os/hal/boards/SN_SN32F290/board.h +++ b/os/hal/boards/SN_SN32F290/board.h @@ -24,7 +24,7 @@ /* * Board identifier. */ -#define BOARD_GENERIC_SN32_F240 +#define BOARD_GENERIC_SN32_F290 #define BOARD_NAME "SN32F290" /* @@ -80,6 +80,8 @@ #define GPIOC_PIN0 0U #define GPIOC_PIN1 1U #define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U #define GPIOC_PIN5 5U #define GPIOC_PIN6 6U #define GPIOC_PIN7 7U @@ -92,8 +94,9 @@ #define GPIOC_PIN14 14U #define GPIOC_PIN15 15U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U #define GPIOD_PIN5 5U #define GPIOD_PIN6 6U #define GPIOD_PIN7 7U @@ -122,8 +125,17 @@ #define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating #define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. +#define PIN_CFG1_PULLUP(n) (0U << (((n-16)*2))) // Pull-up +#define PIN_CFG1_SCHMITT_EN(n) (2U << (((n-16)*2))) // Floating +#define PIN_CFG1_SCHMITT_DIS(n) (3U << (((n-16)*2))) // Input buffer disconnected, alway read as zero. + // Define GPIO register values used by pal_default_config. // The following values match the chip reset values, all GPIO pins as floating inputs. +#define GPIOA_WIDTH 20U +#define GPIOB_WIDTH 20U +#define GPIOC_WIDTH 16U +#define GPIOD_WIDTH 20U +#define PAL_IOPORTS_WIDTH 20U #define VAL_GPIOA_MODE \ ( PIN_MODE_INPUT(GPIOA_PIN0) \ @@ -162,11 +174,12 @@ | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOA_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOA_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOA_PIN19) ) #define VAL_GPIOB_MODE \ ( PIN_MODE_INPUT(GPIOB_PIN0) \ @@ -205,11 +218,12 @@ | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOB_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) ) +#define VAL_GPIOB_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOB_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOB_PIN19) ) #define VAL_GPIOC_MODE \ ( PIN_MODE_INPUT(GPIOC_PIN0) \ @@ -247,8 +261,9 @@ | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) #define VAL_GPIOD_MODE \ - ( PIN_MODE_INPUT(GPIOD_PIN3) \ - | PIN_MODE_INPUT(GPIOD_PIN4) \ + ( PIN_MODE_INPUT(GPIOD_PIN0) \ + | PIN_MODE_INPUT(GPIOD_PIN1) \ + | PIN_MODE_INPUT(GPIOD_PIN2) \ | PIN_MODE_INPUT(GPIOD_PIN5) \ | PIN_MODE_INPUT(GPIOD_PIN6) \ | PIN_MODE_INPUT(GPIOD_PIN7) \ @@ -265,8 +280,9 @@ | PIN_MODE_INPUT(GPIOD_PIN18) \ | PIN_MODE_INPUT(GPIOD_PIN19) ) #define VAL_GPIOD_CFG \ - ( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN2) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ @@ -277,11 +293,12 @@ | PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \ | PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \ - | PIN_CFG_SCHMITT_EN(GPIOD_PIN19) ) + | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) ) +#define VAL_GPIOD_CFG1 \ + ( PIN_CFG1_SCHMITT_EN(GPIOD_PIN16) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN17) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN18) \ + | PIN_CFG1_SCHMITT_EN(GPIOD_PIN19) ) #if !defined(_FROM_ASM_) # ifdef __cplusplus diff --git a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c deleted file mode 100644 index a87f2152ef..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c +++ /dev/null @@ -1,142 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: ADC related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include -#include "ADC.h" -#include "..\..\Utility\Utility.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -uint8_t bADC_StartConv; - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : ADC_Init -* Description : Initialization of ADC -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_Init(void) -{ - SN_SYS1->AHBCLKEN |= (0x01 << 11); //Enables HCLK for ADC - - //Set ADC PCLK - SN_SYS1->APBCP0 |= (0x00 << 16); //ADC PCLK = HCLK/1 - //SN_SYS1->APBCP0 |= (0x01 << 16); //ADC PCLK = HCLK/2 - //SN_SYS1->APBCP0 |= (0x02 << 16); //ADC PCLK = HCLK/4 - //SN_SYS1->APBCP0 |= (0x03 << 16); //ADC PCLK = HCLK/8 - //SN_SYS1->APBCP0 |= (0x04 << 16); //ADC PCLK = HCLK/16 - - SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC - - UT_DelayNx10us(10); //Delay 100us - - SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal VDD - - SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel - - SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit - - SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32 - - #if ADC_FUNCTION_TYPE == ADC_TYPE - - SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel - - SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt - - #endif - - #if ADC_FUNCTION_TYPE == TS_TYPE - - SN_ADC->ADM_b.TSENB = ADC_TSENB_EN; //Enable Temperature Sensor - SN_ADC->ADM_b.CHS = ADC_CHS_TS; //Set P2.14 as Temperature Sensor channel - SN_ADC->IE |= ADC_IE_TS; //Enable Temperature Sensor interrupt - - #endif - - ADC_NvicEnable(); //Enable ADC NVIC interrupt -} - -/***************************************************************************** -* Function : ADC_Read -* Description : Read ADC converted data -* Input : None -* Output : None -* Return : Data in ADB register -* Note : None -*****************************************************************************/ -uint16_t ADC_Read(void) -{ - return SN_ADC->ADB; -} - -/***************************************************************************** -* Function : ADC_IRQHandler -* Description : ISR of ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void ADC_IRQHandler(void) -{ - bADC_StartConv = 0; - - SN_ADC->RIS = 0x0; //clear interrupt flag -} - -/***************************************************************************** -* Function : ADC_NvicEnable -* Description : Enable ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_NvicEnable(void) -{ - NVIC_ClearPendingIRQ(ADC_IRQn); - NVIC_EnableIRQ(ADC_IRQn); - NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : ADC_NvicDisable -* Description : Disable ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_NvicDisable(void) -{ - NVIC_DisableIRQ(ADC_IRQn); -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h deleted file mode 100644 index 85c7168327..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __SN32F240_ADC_H -#define __SN32F240_ADC_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -//ADC function Type -#define ADC_FUNCTION_TYPE ADC_TYPE //ADC_TYPE, TS_TYPE -#define ADC_TYPE 0 //ADC function -#define TS_TYPE 1 //Temperature Sensor function - -//Temperature sensor enable bit -#define ADC_TSENB_DIS 0x0 -#define ADC_TSENB_EN 0x1 - -//ADC high reference voltage source select bit -#define ADC_AVREFHSEL_INTERNAL 0x0 -#define ADC_AVREFHSEL_EXTERNAL 0x1 - -//ADC Enable bit -#define ADC_ADENB_DIS 0x0 -#define ADC_ADENB_EN 0x1 - -//ADC Clock source divider -#define ADC_ADCKS_DIV1 0x0 -#define ADC_ADCKS_DIV2 0x1 -#define ADC_ADCKS_DIV4 0x2 -#define ADC_ADCKS_DIV8 0x3 -#define ADC_ADCKS_DIV16 0x5 -#define ADC_ADCKS_DIV32 0x6 - -//ADC resolution control bit -#define ADC_ADLEN_8BIT 0x0 -#define ADC_ADLEN_12BIT 0x1 - -//ADC start control bit -#define ADC_ADS_STOP 0x0 -#define ADC_ADS_START 0x1 - -//ADC global channel select bit -#define ADC_GCHS_DIS 0x0 -#define ADC_GCHS_EN 0x1 - -//ADC input channels select bit -#define ADC_CHS_AIN0 0x0 //P2.0 -#define ADC_CHS_AIN1 0x1 //P2.1 -#define ADC_CHS_AIN2 0x2 //P2.2 -#define ADC_CHS_AIN3 0x3 //P2.3 -#define ADC_CHS_AIN4 0x4 //P2.4 -#define ADC_CHS_AIN5 0x5 //P2.5 -#define ADC_CHS_AIN6 0x6 //P2.6 -#define ADC_CHS_AIN7 0x7 //P2.7 -#define ADC_CHS_AIN8 0x8 //P2.8 -#define ADC_CHS_AIN9 0x9 //P2.9 -#define ADC_CHS_AIN10 0xA //P2.10 -#define ADC_CHS_AIN11 0xB //P2.11 -#define ADC_CHS_AIN12 0xC //P2.12 -#define ADC_CHS_AIN13 0xD //P2.13 -#define ADC_CHS_TS 0xE //Temperature Sensor - -//ADC Interrupt Enable register(ADC_IE) -#define ADC_IE_AIN0 0x0001 -#define ADC_IE_AIN1 0x0002 -#define ADC_IE_AIN2 0x0004 -#define ADC_IE_AIN3 0x0008 -#define ADC_IE_AIN4 0x0010 -#define ADC_IE_AIN5 0x0020 -#define ADC_IE_AIN6 0x0040 -#define ADC_IE_AIN7 0x0080 -#define ADC_IE_AIN8 0x0100 -#define ADC_IE_AIN9 0x0200 -#define ADC_IE_AIN10 0x0400 -#define ADC_IE_AIN11 0x0800 -#define ADC_IE_AIN12 0x1000 -#define ADC_IE_AIN13 0x2000 -#define ADC_IE_TS 0x4000 - - -//ADC Raw Interrupt Status register(ADC_RIS) -#define mskADC_IF_AIN0 (0x1<<0) //P2.0 -#define mskADC_IF_AIN1 (0x1<<1) //P2.1 -#define mskADC_IF_AIN2 (0x1<<2) //P2.2 -#define mskADC_IF_AIN3 (0x1<<3) //P2.3 -#define mskADC_IF_AIN4 (0x1<<4) //P2.4 -#define mskADC_IF_AIN5 (0x1<<5) //P2.5 -#define mskADC_IF_AIN6 (0x1<<6) //P2.6 -#define mskADC_IF_AIN7 (0x1<<7) //P2.7 -#define mskADC_IF_AIN8 (0x1<<8) //P2.8 -#define mskADC_IF_AIN9 (0x1<<9) //P2.9 -#define mskADC_IF_AIN10 (0x1<<10) //P2.10 -#define mskADC_IF_AIN11 (0x1<<11) //P2.11 -#define mskADC_IF_AIN12 (0x1<<12) //P2.12 -#define mskADC_IF_AIN13 (0x1<<13) //P2.13 -#define mskADC_IF_TS (0x1<<14) //Temperature Sensor - -/*_____ M A C R O S ________________________________________________________*/ - - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern uint8_t bADC_StartConv; - -void ADC_Init(void); -uint16_t ADC_Read(void); -void ADC_NvicEnable(void); -void ADC_NvicDisable(void); - -#endif /*__SN32F240_ADC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h deleted file mode 100644 index 9fc2dd4822..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef __SN32F240_CT16_H -#define __SN32F240_CT16_H - - -/*_____ I N C L U D E S ____________________________________________________*/ - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4000 0000 (CT16B0) - 0x4000 2000 (CT16B1) - 0x4000 4000 (CT16B2) -*/ - -/* CT16Bn Timer Control register (0x00) */ -#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit -#define CT16_CEN_EN 1 -#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0) -#define mskCT16_CEN_EN (CT16_CEN_EN<<0) - -#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit -#define mskCT16_CRST (CT16_CRST<<1) - - //[6:4] CT16Bn counting mode selection -#define CT16_CM_EDGE_UP 0 //Edge-aligned Up-counting mode -#define CT16_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode -#define CT16_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period -#define CT16_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period -#define CT16_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. -#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4) -#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4) -#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4) -#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4) -#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4) - -/* CT16Bn Count Control register (0x10) */ - //[1:0] Count/Timer Mode selection. -#define CT16_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. -#define CT16_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. -#define CT16_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. -#define CT16_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. -#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0) -#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0) -#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0) -#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0) - -#define CT16_CIS 0 //[3:2] Count Input Select -#define mskCT16_CIS (CT16_CIS<<2) - -/* CT16Bn Match Control register (0x14) */ -#define CT16_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt -#define CT16_MR0IE_DIS 0 -#define mskCT16_MR0IE_EN (CT16_MR0IE_EN<<0) -#define mskCT16_MR0IE_DIS (CT16_MR0IE_DIS<<0) - -#define CT16_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. -#define CT16_MR0RST_DIS 0 -#define mskCT16_MR0RST_EN (CT16_MR0RST_EN<<1) -#define mskCT16_MR0RST_DIS (CT16_MR0RST_DIS<<1) - -#define CT16_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. -#define CT16_MR0STOP_DIS 0 -#define mskCT16_MR0STOP_EN (CT16_MR0STOP_EN<<2) -#define mskCT16_MR0STOP_DIS (CT16_MR0STOP_DIS<<2) - -#define CT16_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt -#define CT16_MR1IE_DIS 0 -#define mskCT16_MR1IE_EN (CT16_MR1IE_EN<<3) -#define mskCT16_MR1IE_DIS (CT16_MR1IE_DIS<<3) - -#define CT16_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. -#define CT16_MR1RST_DIS 0 -#define mskCT16_MR1RST_EN (CT16_MR1RST_EN<<4) -#define mskCT16_MR1RST_DIS (CT16_MR1RST_DIS<<4) - -#define CT16_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. -#define CT16_MR1STOP_DIS 0 -#define mskCT16_MR1STOP_EN (CT16_MR1STOP_EN<<5) -#define mskCT16_MR1STOP_DIS (CT16_MR1STOP_DIS<<5) - -#define CT16_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt -#define CT16_MR2IE_DIS 0 -#define mskCT16_MR2IE_EN (CT16_MR2IE_EN<<6) -#define mskCT16_MR2IE_DIS (CT16_MR2IE_DIS<<6) - -#define CT16_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. -#define CT16_MR2RST_DIS 0 -#define mskCT16_MR2RST_EN (CT16_MR2RST_EN<<7) -#define mskCT16_MR2RST_DIS (CT16_MR2RST_DIS<<7) - -#define CT16_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. -#define CT16_MR2STOP_DIS 0 -#define mskCT16_MR2STOP_EN (CT16_MR2STOP_EN<<8) -#define mskCT16_MR2STOP_DIS (CT16_MR2STOP_DIS<<8) - -#define CT16_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt -#define CT16_MR3IE_DIS 0 -#define mskCT16_MR3IE_EN (CT16_MR3IE_EN<<9) -#define mskCT16_MR3IE_DIS (CT16_MR3IE_DIS<<9) - -#define CT16_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. -#define CT16_MR3RST_DIS 0 -#define mskCT16_MR3RST_EN (CT16_MR3RST_EN<<10) -#define mskCT16_MR3RST_DIS (CT16_MR3RST_DIS<<10) - -#define CT16_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. -#define CT16_MR3STOP_DIS 0 -#define mskCT16_MR3STOP_EN (CT16_MR3STOP_EN<<11) -#define mskCT16_MR3STOP_DIS (CT16_MR3STOP_DIS<<11) - -/* CT16Bn Capture Control register (0x28) */ -#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. -#define CT16_CAP0RE_DIS 0 -#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0) -#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0) - -#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. -#define CT16_CAP0FE_DIS 0 -#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1) -#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1) - -#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. -#define CT16_CAP0IE_DIS 0 -#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2) -#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2) - -#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function. -#define CT16_CAP0EN_DIS 0 -#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3) -#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3) - -/* CT16Bn External Match register (0x30) */ -#define CT16_EM0 1 //[0:0] CT16Bn PWM0 drive state -#define mskCT16_EM0 (CT16_EM0<<0) -#define CT16_EM1 1 //[1:1] CT16Bn PWM1 drive state -#define mskCT16_EM1 (CT16_EM1<<1) -#define CT16_EM2 1 //[2:2] CT16Bn PWM2 drive state -#define mskCT16_EM2 (CT16_EM2<<2) - - - //[5:4] CT16Bn PWM0 functionality -#define CT16_EMC0_DO_NOTHING 0 //Do nothing. -#define CT16_EMC0_LOW 1 //CT16Bn PWM0 pin is low. -#define CT16_EMC0_HIGH 2 //CT16Bn PWM0 pin is high. -#define CT16_EMC0_TOGGLE 3 //Toggle CT16Bn PWM0 pin. -#define mskCT16_EMC0_DO_NOTHING (CT16_EMC0_LOW<<4) -#define mskCT16_EMC0_LOW (CT16_EMC0_LOW<<4) -#define mskCT16_EMC0_HIGH (CT16_EMC0_HIGH<<4) -#define mskCT16_EMC0_TOGGLE (CT16_EMC0_TOGGLE<<4) - - //[7:6] CT16Bn PWM1 functionality -#define CT16_EMC1_DO_NOTHING 0 //Do nothing. -#define CT16_EMC1_LOW 1 //CT16Bn PWM1 pin is low. -#define CT16_EMC1_HIGH 2 //CT16Bn PWM1 pin is high. -#define CT16_EMC1_TOGGLE 3 //Toggle CT16Bn PWM1 pin. -#define mskCT16_EMC1_DO_NOTHING (CT16_EMC1_LOW<<6) -#define mskCT16_EMC1_LOW (CT16_EMC1_LOW<<6) -#define mskCT16_EMC1_HIGH (CT16_EMC1_HIGH<<6) -#define mskCT16_EMC1_TOGGLE (CT16_EMC1_TOGGLE<<6) - - //[9:8] CT16Bn PWM2 functionality -#define CT16_EMC2_DO_NOTHING 0 //Do nothing. -#define CT16_EMC2_LOW 1 //CT16Bn PWM2 pin is low. -#define CT16_EMC2_HIGH 2 //CT16Bn PWM2 pin is high. -#define CT16_EMC2_TOGGLE 3 //Toggle CT16Bn PWM2 pin. -#define mskCT16_EMC2_DO_NOTHING (CT16_EMC2_LOW<<8) -#define mskCT16_EMC2_LOW (CT16_EMC2_LOW<<8) -#define mskCT16_EMC2_HIGH (CT16_EMC2_HIGH<<8) -#define mskCT16_EMC2_TOGGLE (CT16_EMC2_TOGGLE<<8) - - -/* CT16Bn PWM Control register (0x34) */ - //[0:0] CT16Bn PWM0 enable. -#define CT16_PWM0EN_EN 1 // CT16Bn PWM0 is enabled for PWM mode. -#define CT16_PWM0EN_EM0 0 // CT16Bn PWM0 is controlled by EM0. -#define mskCT16_PWM0EN_EN (CT16_PWM0EN_EN<<0) -#define mskCT16_PWM0EN_EM0 (CT16_PWM0EN_EM0<<0) - - //[1:1] CT16Bn PWM1 enable. -#define CT16_PWM1EN_EN 1 // CT16Bn PWM1 is enabled for PWM mode. -#define CT16_PWM1EN_EM1 0 // CT16Bn PWM1 is controlled by EM1. -#define mskCT16_PWM1EN_EN (CT16_PWM1EN_EN<<1) -#define mskCT16_PWM1EN_EM1 (CT16_PWM1EN_EM1<<1) - - //[2:2] CT16Bn PWM2 enable. -#define CT16_PWM2EN_EN 1 // CT16Bn PWM2 is enabled for PWM mode. -#define CT16_PWM2EN_EM2 0 // CT16Bn PWM2 is controlled by EM2. -#define mskCT16_PWM2EN_EN (CT16_PWM2EN_EN<<2) -#define mskCT16_PWM2EN_EM2 (CT16_PWM2EN_EM2<<2) - - //[5:4] CT16Bn PWM0 output mode. -#define CT16_PWM0MODE_1 0 // PWM mode 1. -#define CT16_PWM0MODE_2 1 // PWM mode 2. -#define CT16_PWM0MODE_FORCE_0 2 // Force 0. -#define CT16_PWM0MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM0MODE_1 (CT16_PWM0MODE_1<<4) -#define mskCT16_PWM0MODE_2 (CT16_PWM0MODE_2<<4) -#define mskCT16_PWM0MODE_FORCE_0 (CT16_PWM0MODE_FORCE_0<<4) -#define mskCT16_PWM0MODE_FORCE_1 (CT16_PWM0MODE_FORCE_1<<4) - - //[7:6] CT16Bn PWM1 output mode. -#define CT16_PWM1MODE_1 0 // PWM mode 1. -#define CT16_PWM1MODE_2 1 // PWM mode 2. -#define CT16_PWM1MODE_FORCE_0 2 // Force 0. -#define CT16_PWM1MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM1MODE_1 (CT16_PWM1MODE_1<<6) -#define mskCT16_PWM1MODE_2 (CT16_PWM1MODE_2<<6) -#define mskCT16_PWM1MODE_FORCE_0 (CT16_PWM1MODE_FORCE_0<<6) -#define mskCT16_PWM1MODE_FORCE_1 (CT16_PWM1MODE_FORCE_1<<6) - - //[9:8] CT16Bn PWM2 output mode. -#define CT16_PWM2MODE_1 0 // PWM mode 1. -#define CT16_PWM2MODE_2 1 // PWM mode 2. -#define CT16_PWM2MODE_FORCE_0 2 // Force 0. -#define CT16_PWM2MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM2MODE_1 (CT16_PWM2MODE_1<<8) -#define mskCT16_PWM2MODE_2 (CT16_PWM2MODE_2<<8) -#define mskCT16_PWM2MODE_FORCE_0 (CT16_PWM2MODE_FORCE_0<<8) -#define mskCT16_PWM2MODE_FORCE_1 (CT16_PWM2MODE_FORCE_1<<8) - - //[20:20] CT16Bn PWM0 IO selection. -#define CT16_PWM0IOEN_EN 1 // PWM 0 pin acts as match output. -#define CT16_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO. -#define mskCT16_PWM0IOEN_EN (CT16_PWM0IOEN_EN<<20) -#define mskCT16_PWM0IOEN_DIS (CT16_PWM0IOEN_DIS<<20) - - //[21:21] CT16Bn PWM1 IO selection. -#define CT16_PWM1IOEN_EN 1 // PWM 1 pin acts as match output. -#define CT16_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO. -#define mskCT16_PWM1IOEN_EN (CT16_PWM1IOEN_EN<<21) -#define mskCT16_PWM1IOEN_DIS (CT16_PWM1IOEN_DIS<<21) - - //[22:22] CT16Bn PWM2 IO selection. -#define CT16_PWM2IOEN_EN 1 // PWM 2 pin acts as match output. -#define CT16_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO. -#define mskCT16_PWM2IOEN_EN (CT16_PWM2IOEN_EN<<22) -#define mskCT16_PWM2IOEN_DIS (CT16_PWM2IOEN_DIS<<22) - - -/* CT16Bn Timer Raw Interrupt Status register (0x38) */ -/* CT16Bn Timer Interrupt Clear register (0x3C) */ -/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/ -#define mskCT16_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 -#define mskCT16_MR0IC mskCT16_MR0IF -#define mskCT16_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 -#define mskCT16_MR1IC mskCT16_MR1IF -#define mskCT16_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 -#define mskCT16_MR2IC mskCT16_MR2IF -#define mskCT16_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 -#define mskCT16_MR3IC mskCT16_MR3IF -#define mskCT16_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0 -#define mskCT16_CAP0IC mskCT16_CAP0IF - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - -#endif /*__SN32F240_CT16_H*/ - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c deleted file mode 100644 index c91c8e87d0..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c +++ /dev/null @@ -1,160 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT16B0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT16.h" -#include "CT16B0.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT16B0_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -void CT16B0_Init (void); -void CT16B0_NvicEnable (void); -void CT16B0_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : CT16B0_Init -* Description : Initialization of CT16B0 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_Init (void) -{ - //Enable P_CLOCK for CT16B0. - __CT16B0_ENABLE; - - //CT16B0 PCLK prescalar setting - SN_SYS1->APBCP0_b.CT16B0PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT16B0_NvicEnable -* Description : Enable CT16B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT16B0_IRQn); - NVIC_EnableIRQ(CT16B0_IRQn); - //NVIC_SetPriority(CT16B0_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT16B0_NvicEnable -* Description : Disable CT16B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_NvicDisable (void) -{ - NVIC_DisableIRQ(CT16B0_IRQn); -} - - - -/***************************************************************************** -* Function : CT16B0_IRQHandler -* Description : ISR of CT16B0 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT16B0->RIS; //Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT16B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT16_MR0IF) - { - iwCT16B0_IrqEvent |= mskCT16_MR0IF; - SN_CT16B0->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT16B0->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT16_MR1IF) - { - iwCT16B0_IrqEvent |= mskCT16_MR1IF; - SN_CT16B0->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT16B0->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT16_MR2IF) - { - iwCT16B0_IrqEvent |= mskCT16_MR2IF; - SN_CT16B0->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT16B0->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT16_MR3IF) - { - iwCT16B0_IrqEvent |= mskCT16_MR3IF; - SN_CT16B0->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status - } - } - //CAP0 - if (SN_CT16B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT16_CAP0IF) //CAP0 - { - iwCT16B0_IrqEvent |= mskCT16_CAP0IF; - SN_CT16B0->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h deleted file mode 100644 index 8faaa47f06..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT16B0_H -#define __SN32F240_CT16B0_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt - //POLLING_METHOD: Enable CT16B0 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT16B0 PCLK -#define __CT16B0_ENABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = ENABLE - // Disable CT16B0 PCLK -#define __CT16B0_DISABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -extern void CT16B0_Init(void); -extern void CT16B0_NvicEnable(void); -extern void CT16B0_NvicDisable(void); -extern void CT16B0_IRQHandler(void); -#endif /*__SN32F240_CT16B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c deleted file mode 100644 index 8bba8df511..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c +++ /dev/null @@ -1,161 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT16B1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT16.h" -#include "CT16B1.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT16B1_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -void CT16B1_Init (void); -void CT16B1_NvicEnable (void); -void CT16B1_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : CT16B1_Init -* Description : Initialization of CT16B1 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_Init (void) -{ - //Enable P_CLOCK for CT16B1. - __CT16B1_ENABLE; - - //CT16B1 PCLK prescalar setting - SN_SYS1->APBCP0_b.CT16B1PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT16B1PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT16B1PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT16B1PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT16B1PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT16B1_NvicEnable -* Description : Enable CT16B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT16B1_IRQn); - NVIC_EnableIRQ(CT16B1_IRQn); - //NVIC_SetPriority(CT16B1_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT16B1_NvicDisable -* Description : Enable CT16B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_NvicDisable (void) -{ - NVIC_DisableIRQ(CT16B1_IRQn); -} - -/***************************************************************************** -* Function : CT16B1_IRQHandler -* Description : ISR of CT16B1 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT16B1->RIS; //Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT16B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT16_MR0IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR0IF; - SN_CT16B1->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT16B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT16_MR1IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR1IF; - SN_CT16B1->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status - } - } - - //MR2 - if (SN_CT16B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT16_MR2IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR2IF; - SN_CT16B1->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status - } - } - - //MR3 - if (SN_CT16B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT16_MR3IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR3IF; - SN_CT16B1->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status - } - } - - //CAP0 - if (SN_CT16B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT16_CAP0IF) //CAP0 - { - iwCT16B1_IrqEvent |= mskCT16_CAP0IF; - SN_CT16B1->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h deleted file mode 100644 index 380119a2f0..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT16B1_H -#define __SN32F240_CT16B1_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt - //POLLING_METHOD: Enable CT16B1 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT16B1 PCLK -#define __CT16B1_ENABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = ENABLE - // Disable CT16B1 PCLK -#define __CT16B1_DISABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -extern void CT16B1_Init(void); -extern void CT16B1_NvicEnable(void); -extern void CT16B1_NvicDisable(void); -extern void CT16B1_IRQHandler(void); -#endif /*__SN32F240_CT16B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c deleted file mode 100644 index 846ede03eb..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c +++ /dev/null @@ -1,158 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT16B2 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT16.h" -#include "CT16B2.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT16B2_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -void CT16B2_Init (void); -void CT16B2_NvicEnable (void); -void CT16B2_NvicDisable (void); -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : CT16B2_Init -* Description : Initialization of CT16B2 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B2_Init (void) -{ - //Enable P_CLOCK for CT16B2. - __CT16B2_ENABLE; - - //CT16B2 PCLK prescalar setting - SN_SYS1->APBCP1_b.CT16B2PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP1_b.CT16B2PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP1_b.CT16B2PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP1_b.CT16B2PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP1_b.CT16B2PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT16B2_NvicEnable -* Description : Enable CT16B2 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B2_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT16B2_IRQn); - NVIC_EnableIRQ(CT16B2_IRQn); - NVIC_SetPriority(CT16B2_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT16B2_NvicDisable -* Description : Disable CT16B2 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B2_NvicDisable (void) -{ - NVIC_DisableIRQ(CT16B2_IRQn); -} - - -/***************************************************************************** -* Function : CT16B2_IRQHandler -* Description : ISR of CT16B2 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B2_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT16B2->RIS; // Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT16B2->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT16_MR0IF) - { - iwCT16B2_IrqEvent |= mskCT16_MR0IF; - SN_CT16B2->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT16B2->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT16_MR1IF) - { - iwCT16B2_IrqEvent |= mskCT16_MR1IF; - SN_CT16B2->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT16B2->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT16_MR2IF) - { - iwCT16B2_IrqEvent |= mskCT16_MR2IF; - SN_CT16B2->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT16B2->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT16_MR3IF) - { - iwCT16B2_IrqEvent |= mskCT16_MR3IF; - SN_CT16B2->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status - } - } - //CAP0 - if (SN_CT16B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT16_CAP0IF) //CAP0 - { - iwCT16B2_IrqEvent |= mskCT16_CAP0IF; - SN_CT16B2->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h deleted file mode 100644 index 23c4a4edbc..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT16B2_H -#define __SN32F240_CT16B2_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT16B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B2 timer and interrupt - //POLLING_METHOD: Enable CT16B2 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT16B2 PCLK -#define __CT16B2_ENABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = ENABLE - // Disable CT16B1 PCLK -#define __CT16B2_DISABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT16B2_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -extern void CT16B2_Init(void); -extern void CT16B2_NvicEnable(void); -extern void CT16B2_NvicDisable(void); -extern void CT16B2_IRQHandler(void); -#endif /*__SN32F240_CT16B2_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h deleted file mode 100644 index 48e2de98a3..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h +++ /dev/null @@ -1,278 +0,0 @@ -#ifndef __SN32F240_CT32_H -#define __SN32F240_CT32_H - - -/*_____ I N C L U D E S ____________________________________________________*/ - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4000 6000 (CT32B0) - 0x4000 8000 (CT32B1) - 0x4000 A000 (CT32B2) -*/ - -/* CT32Bn Timer Control register (0x00) */ -#define CT32_CEN_DIS 0 //[0:0] CT32Bn enable bit -#define CT32_CEN_EN 1 -#define mskCT32_CEN_DIS (CT32_CEN_DIS<<0) -#define mskCT32_CEN_EN (CT32_CEN_EN<<0) - -#define CT32_CRST 1 //[1:1] CT32Bn counter reset bit -#define mskCT32_CRST (CT32_CRST<<1) - - //[6:4] CT32Bn counting mode selection -#define CT32_CM_EDGE_UP 0 //Edge-aligned Up-counting mode -#define CT32_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode -#define CT32_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period -#define CT32_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period -#define CT32_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. -#define mskCT32_CM_EDGE_UP (CT32_CM_EDGE_UP<<4) -#define mskCT32_CM_EDGE_DOWN (CT32_CM_EDGE_DOWN<<4) -#define mskCT32_CM_CENTER_UP (CT32_CM_CENTER_UP<<4) -#define mskCT32_CM_CENTER_DOWN (CT32_CM_CENTER_DOWN<<4) -#define mskCT32_CM_CENTER_BOTH (CT32_CM_CENTER_BOTH<<4) - -/* CT32Bn Count Control register (0x10) */ - //[1:0] Count/Timer Mode selection. -#define CT32_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. -#define CT32_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. -#define CT32_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. -#define CT32_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. -#define mskCT32_CTM_TIMER (CT32_CTM_TIMER<<0) -#define mskCT32_CTM_CNTER_RISING (CT32_CTM_CNTER_RISING<<0) -#define mskCT32_CTM_CNTER_FALLING (CT32_CTM_CNTER_FALLING<<0) -#define mskCT32_CTM_CNTER_BOTH (CT32_CTM_CNTER_BOTH<<0) - -#define CT32_CIS 0 //[3:2] Count Input Select -#define mskCT32_CIS (CT32_CIS<<2) - -/* CT32Bn Match Control register (0x14) */ -#define CT32_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt -#define CT32_MR0IE_DIS 0 -#define mskCT32_MR0IE_EN (CT32_MR0IE_EN<<0) -#define mskCT32_MR0IE_DIS (CT32_MR0IE_DIS<<0) - -#define CT32_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. -#define CT32_MR0RST_DIS 0 -#define mskCT32_MR0RST_EN (CT32_MR0RST_EN<<1) -#define mskCT32_MR0RST_DIS (CT32_MR0RST_DIS<<1) - -#define CT32_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. -#define CT32_MR0STOP_DIS 0 -#define mskCT32_MR0STOP_EN (CT32_MR0STOP_EN<<2) -#define mskCT32_MR0STOP_DIS (CT32_MR0STOP_DIS<<2) - -#define CT32_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt -#define CT32_MR1IE_DIS 0 -#define mskCT32_MR1IE_EN (CT32_MR1IE_EN<<3) -#define mskCT32_MR1IE_DIS (CT32_MR1IE_DIS<<3) - -#define CT32_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. -#define CT32_MR1RST_DIS 0 -#define mskCT32_MR1RST_EN (CT32_MR1RST_EN<<4) -#define mskCT32_MR1RST_DIS (CT32_MR1RST_DIS<<4) - -#define CT32_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. -#define CT32_MR1STOP_DIS 0 -#define mskCT32_MR1STOP_EN (CT32_MR1STOP_EN<<5) -#define mskCT32_MR1STOP_DIS (CT32_MR1STOP_DIS<<5) - -#define CT32_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt -#define CT32_MR2IE_DIS 0 -#define mskCT32_MR2IE_EN (CT32_MR2IE_EN<<6) -#define mskCT32_MR2IE_DIS (CT32_MR2IE_DIS<<6) - -#define CT32_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. -#define CT32_MR2RST_DIS 0 -#define mskCT32_MR2RST_EN (CT32_MR2RST_EN<<7) -#define mskCT32_MR2RST_DIS (CT32_MR2RST_DIS<<7) - -#define CT32_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. -#define CT32_MR2STOP_DIS 0 -#define mskCT32_MR2STOP_EN (CT32_MR2STOP_EN<<8) -#define mskCT32_MR2STOP_DIS (CT32_MR2STOP_DIS<<8) - -#define CT32_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt -#define CT32_MR3IE_DIS 0 -#define mskCT32_MR3IE_EN (CT32_MR3IE_EN<<9) -#define mskCT32_MR3IE_DIS (CT32_MR3IE_DIS<<9) - -#define CT32_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. -#define CT32_MR3RST_DIS 0 -#define mskCT32_MR3RST_EN (CT32_MR3RST_EN<<10) -#define mskCT32_MR3RST_DIS (CT32_MR3RST_DIS<<10) - -#define CT32_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. -#define CT32_MR3STOP_DIS 0 -#define mskCT32_MR3STOP_EN (CT32_MR3STOP_EN<<11) -#define mskCT32_MR3STOP_DIS (CT32_MR3STOP_DIS<<11) - -/* CT32Bn Capture Control register (0x28) */ -#define CT32_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. -#define CT32_CAP0RE_DIS 0 -#define mskCT32_CAP0RE_EN (CT32_CAP0RE_EN<<0) -#define mskCT32_CAP0RE_DIS (CT32_CAP0RE_DIS<<0) - -#define CT32_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. -#define CT32_CAP0FE_DIS 0 -#define mskCT32_CAP0FE_EN (CT32_CAP0FE_EN<<1) -#define mskCT32_CAP0FE_DIS (CT32_CAP0FE_DIS<<1) - -#define CT32_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. -#define CT32_CAP0IE_DIS 0 -#define mskCT32_CAP0IE_EN (CT32_CAP0IE_EN<<2) -#define mskCT32_CAP0IE_DIS (CT32_CAP0IE_DIS<<2) - -#define CT32_CAP0EN_EN 1 //[3:3] Enable CAP0 function. -#define CT32_CAP0EN_DIS 0 -#define mskCT32_CAP0EN_EN (CT32_CAP0EN_EN<<3) -#define mskCT32_CAP0EN_DIS (CT32_CAP0EN_DIS<<3) - -/* CT32Bn External Match register (0x30) */ -#define CT32_EM0 1 //[0:0] CT32Bn PWM0 drive state -#define mskCT32_EM0 (CT32_EM0<<0) -#define CT32_EM1 1 //[1:1] CT32Bn PWM1 drive state -#define mskCT32_EM1 (CT32_EM1<<1) -#define CT32_EM2 1 //[2:2] CT32Bn PWM2 drive state -#define mskCT32_EM2 (CT32_EM2<<2) -#define CT32_EM3 1 //[3:3] CT32Bn PWM3 drive state -#define mskCT32_EM3 (CT32_EM3<<3) - - //[5:4] CT32Bn PWM0 functionality -#define CT32_EMC0_DO_NOTHING 0 //Do nothing. -#define CT32_EMC0_LOW 1 //CT32Bn PWM0 pin is low. -#define CT32_EMC0_HIGH 2 //CT32Bn PWM0 pin is high. -#define CT32_EMC0_TOGGLE 3 //Toggle CT32Bn PWM0 pin. -#define mskCT32_EMC0_DO_NOTHING (CT32_EMC0_LOW<<4) -#define mskCT32_EMC0_LOW (CT32_EMC0_LOW<<4) -#define mskCT32_EMC0_HIGH (CT32_EMC0_HIGH<<4) -#define mskCT32_EMC0_TOGGLE (CT32_EMC0_TOGGLE<<4) - - //[7:6] CT32Bn PWM1 functionality -#define CT32_EMC1_DO_NOTHING 0 //Do nothing. -#define CT32_EMC1_LOW 1 //CT32Bn PWM1 pin is low. -#define CT32_EMC1_HIGH 2 //CT32Bn PWM1 pin is high. -#define CT32_EMC1_TOGGLE 3 //Toggle CT32Bn PWM1 pin. -#define mskCT32_EMC1_DO_NOTHING (CT32_EMC1_LOW<<6) -#define mskCT32_EMC1_LOW (CT32_EMC1_LOW<<6) -#define mskCT32_EMC1_HIGH (CT32_EMC1_HIGH<<6) -#define mskCT32_EMC1_TOGGLE (CT32_EMC1_TOGGLE<<6) - - //[9:8] CT32Bn PWM2 functionality -#define CT32_EMC2_DO_NOTHING 0 //Do nothing. -#define CT32_EMC2_LOW 1 //CT32Bn PWM2 pin is low. -#define CT32_EMC2_HIGH 2 //CT32Bn PWM2 pin is high. -#define CT32_EMC2_TOGGLE 3 //Toggle CT32Bn PWM2 pin. -#define mskCT32_EMC2_DO_NOTHING (CT32_EMC2_LOW<<8) -#define mskCT32_EMC2_LOW (CT32_EMC2_LOW<<8) -#define mskCT32_EMC2_HIGH (CT32_EMC2_HIGH<<8) -#define mskCT32_EMC2_TOGGLE (CT32_EMC2_TOGGLE<<8) - - //[11:10] CT32Bn PWM3 functionality -#define CT32_EMC3_DO_NOTHING 0 //Do nothing. -#define CT32_EMC3_LOW 1 //CT32Bn PWM3 pin is low. -#define CT32_EMC3_HIGH 2 //CT32Bn PWM3 pin is high. -#define CT32_EMC3_TOGGLE 3 //Toggle CT32Bn PWM3 pin. -#define mskCT32_EMC3_DO_NOTHING (CT32_EMC2_LOW<<10) -#define mskCT32_EMC3_LOW (CT32_EMC2_LOW<<10) -#define mskCT32_EMC3_HIGH (CT32_EMC2_HIGH<<10) -#define mskCT32_EMC3_TOGGLE (CT32_EMC2_TOGGLE<<10) - -/* CT32Bn PWM Control register (0x34) */ - //[0:0] CT32Bn PWM0 enable. -#define CT32_PWM0EN_EN 1 // CT32Bn PWM0 is enabled for PWM mode. -#define CT32_PWM0EN_EM0 0 // CT32Bn PWM0 is controlled by EM0. -#define mskCT32_PWM0EN_EN (CT32_PWM0EN_EN<<0) -#define mskCT32_PWM0EN_EM0 (CT32_PWM0EN_EM0<<0) - - //[1:1] CT32Bn PWM1 enable. -#define CT32_PWM1EN_EN 1 // CT32Bn PWM1 is enabled for PWM mode. -#define CT32_PWM1EN_EM1 0 // CT32Bn PWM1 is controlled by EM1. -#define mskCT32_PWM1EN_EN (CT32_PWM1EN_EN<<1) -#define mskCT32_PWM1EN_EM1 (CT32_PWM1EN_EM1<<1) - - //[2:2] CT32Bn PWM2 enable. -#define CT32_PWM2EN_EN 1 // CT32Bn PWM2 is enabled for PWM mode. -#define CT32_PWM2EN_EM2 0 // CT32Bn PWM2 is controlled by EM2. -#define mskCT32_PWM2EN_EN (CT32_PWM2EN_EN<<2) -#define mskCT32_PWM2EN_EM2 (CT32_PWM2EN_EM2<<2) - - //[3:3] CT32Bn PWM3 enable. -#define CT32_PWM3EN_EN 1 // CT32Bn PWM3 is enabled for PWM mode. -#define CT32_PWM3EN_EM3 0 // CT32Bn PWM3 is controlled by EM3. -#define mskCT32_PWM3EN_EN (CT32_PWM3EN_EN<<3) -#define mskCT32_PWM3EN_EM3 (CT32_PWM3EN_EM3<<3) - - //[5:4] CT32Bn PWM0 output mode. -#define CT32_PWM0MODE_1 0 // PWM mode 1. -#define CT32_PWM0MODE_2 1 // PWM mode 2. -#define CT32_PWM0MODE_FORCE_0 2 // Force 0. -#define CT32_PWM0MODE_FORCE_1 3 // Force 1. -#define mskCT32_PWM0MODE_1 (CT32_PWM0MODE_1<<4) -#define mskCT32_PWM0MODE_2 (CT32_PWM0MODE_2<<4) -#define mskCT32_PWM0MODE_FORCE_0 (CT32_PWM0MODE_FORCE_0<<4) -#define mskCT32_PWM0MODE_FORCE_1 (CT32_PWM0MODE_FORCE_1<<4) - - //[7:6] CT32Bn PWM1 output mode. -#define CT32_PWM1MODE_1 0 // PWM mode 1. -#define CT32_PWM1MODE_2 1 // PWM mode 2. -#define CT32_PWM1MODE_FORCE_0 2 // Force 0. -#define CT32_PWM1MODE_FORCE_1 3 // Force 1. -#define mskCT32_PWM1MODE_1 (CT32_PWM1MODE_1<<6) -#define mskCT32_PWM1MODE_2 (CT32_PWM1MODE_2<<6) -#define mskCT32_PWM1MODE_FORCE_0 (CT32_PWM1MODE_FORCE_0<<6) -#define mskCT32_PWM1MODE_FORCE_1 (CT32_PWM1MODE_FORCE_1<<6) - - //[9:8] CT32Bn PWM2 output mode. -#define CT32_PWM2MODE_1 0 // PWM mode 1. -#define CT32_PWM2MODE_2 1 // PWM mode 2. -#define CT32_PWM2MODE_FORCE_0 2 // Force 0. -#define CT32_PWM2MODE_FORCE_1 3 // Force 1. -#define mskCT32_PWM2MODE_1 (CT32_PWM2MODE_1<<8) -#define mskCT32_PWM2MODE_2 (CT32_PWM2MODE_2<<8) -#define mskCT32_PWM2MODE_FORCE_0 (CT32_PWM2MODE_FORCE_0<<8) -#define mskCT32_PWM2MODE_FORCE_1 (CT32_PWM2MODE_FORCE_1<<8) - - //[20:20] CT32Bn PWM0 IO selection. -#define CT32_PWM0IOEN_EN 1 // PWM 0 pin acts as match output. -#define CT32_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO. -#define mskCT32_PWM0IOEN_EN (CT32_PWM0IOEN_EN<<20) -#define mskCT32_PWM0IOEN_DIS (CT32_PWM0IOEN_DIS<<20) - - //[21:21] CT32Bn PWM1 IO selection. -#define CT32_PWM1IOEN_EN 1 // PWM 1 pin acts as match output. -#define CT32_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO. -#define mskCT32_PWM1IOEN_EN (CT32_PWM1IOEN_EN<<21) -#define mskCT32_PWM1IOEN_DIS (CT32_PWM1IOEN_DIS<<21) - - //[22:22] CT32Bn PWM2 IO selection. -#define CT32_PWM2IOEN_EN 1 // PWM 2 pin acts as match output. -#define CT32_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO. -#define mskCT32_PWM2IOEN_EN (CT32_PWM2IOEN_EN<<22) -#define mskCT32_PWM2IOEN_DIS (CT32_PWM2IOEN_DIS<<22) - - //[23:23] CT32Bn PWM3 IO selection. -#define CT32_PWM3IOEN_EN 1 // PWM 3 pin acts as match output. -#define CT32_PWM3IOEN_DIS 0 // PWM 3 pin acts as GPIO. -#define mskCT32_PWM3IOEN_EN (CT32_PWM3IOEN_EN<<23) -#define mskCT32_PWM3IOEN_DIS (CT32_PWM3IOEN_DIS<<23) - -/* CT32Bn Timer Raw Interrupt Status register (0x38) */ -/* CT32Bn Timer Interrupt Clear register (0x3C) */ -/* The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS*/ -#define mskCT32_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 -#define mskCT32_MR0IC mskCT32_MR0IF -#define mskCT32_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 -#define mskCT32_MR1IC mskCT32_MR1IF -#define mskCT32_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 -#define mskCT32_MR2IC mskCT32_MR2IF -#define mskCT32_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 -#define mskCT32_MR3IC mskCT32_MR3IF -#define mskCT32_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0 -#define mskCT32_CAP0IC mskCT32_CAP0IF - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -#endif /*__SN32F240_CT32_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c deleted file mode 100644 index 099a19637f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c +++ /dev/null @@ -1,160 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT32B0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT32.h" -#include "CT32B0.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT32B0_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -void CT32B0_Init (void); -void CT32B0_NvicEnable (void); -void CT32B0_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : CT32B0_Init -* Description : Initialization of CT32B0 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B0_Init (void) -{ - //Enable P_CLOCK for CT32B0. - __CT32B0_ENABLE; - - //CT32B0 PCLK prescalar setting - SN_SYS1->APBCP0_b.CT32B0PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT32B0PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT32B0PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT32B0PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT32B0PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT32B0_NvicEnable -* Description : Enable CT32B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B0_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT32B0_IRQn); - NVIC_EnableIRQ(CT32B0_IRQn); - //NVIC_SetPriority(CT32B0_IRQn,0); //Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT32B0_NvicDisable -* Description : Disable CT32B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B0_NvicDisable (void) -{ - NVIC_DisableIRQ(CT32B0_IRQn); -} - - -/***************************************************************************** -* Function : TIMER32_0_IRQHandler -* Description : ISR of CT32B0 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B0_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT32B0->RIS; // Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT32B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT32_MR0IF) - { - iwCT32B0_IrqEvent |= mskCT32_MR0IF; - SN_CT32B0->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT32B0->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT32_MR1IF) - { - iwCT32B0_IrqEvent |= mskCT32_MR1IF; - SN_CT32B0->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT32B0->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT32_MR2IF) - { - iwCT32B0_IrqEvent |= mskCT32_MR2IF; - SN_CT32B0->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT32B0->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT32_MR3IF) - { - iwCT32B0_IrqEvent |= mskCT32_MR3IF; - SN_CT32B0->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status - } - } - //CAP0 - if (SN_CT32B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT32_CAP0IF) //CAP0 - { - iwCT32B0_IrqEvent |= mskCT32_CAP0IF; - SN_CT32B0->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h deleted file mode 100644 index 9973f45c36..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT32B0_H -#define __SN32F240_CT32B0_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT32B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B0 timer and interrupt - //POLLING_METHOD: Enable CT32B0 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT32B0 PCLK -#define __CT32B0_ENABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = ENABLE - // Disable CT32B0 PCLK -#define __CT32B0_DISABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT32B0_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -extern void CT32B0_Init(void); -extern void CT32B0_NvicEnable(void); -extern void CT32B0_NvicDisable(void); -extern void CT32B0_IRQHandler(void); -#endif /*__SN32F240_CT32B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c deleted file mode 100644 index 88b9372b6b..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c +++ /dev/null @@ -1,160 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT32B1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT32.h" -#include "CT32B1.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT32B1_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -void CT32B1_Init (void); -void CT32B1_NvicEnable (void); -void CT32B1_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : CT32B1_Init -* Description : Initialization of CT32B1 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B1_Init (void) -{ - //Enable P_CLOCK for CT32B1. - __CT32B1_ENABLE; - - //CT32B1 PCLK prescalar setting - SN_SYS1->APBCP0_b.CT32B1PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT32B1PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT32B1PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT32B1PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT32B1PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT32B1_NvicEnable -* Description : Enable CT32B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B1_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT32B1_IRQn); - NVIC_EnableIRQ(CT32B1_IRQn); - //NVIC_SetPriority(CT32B1_IRQn,0); //Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT32B1_NvicDisable -* Description : Disable CT32B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B1_NvicDisable (void) -{ - NVIC_DisableIRQ(CT32B1_IRQn); -} - - -/***************************************************************************** -* Function : TIMER32_0_IRQHandler -* Description : ISR of CT32B1 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B1_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT32B1->RIS; // Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT32B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT32_MR0IF) - { - iwCT32B1_IrqEvent |= mskCT32_MR0IF; - SN_CT32B1->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT32B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT32_MR1IF) - { - iwCT32B1_IrqEvent |= mskCT32_MR1IF; - SN_CT32B1->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT32B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT32_MR2IF) - { - iwCT32B1_IrqEvent |= mskCT32_MR2IF; - SN_CT32B1->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT32B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT32_MR3IF) - { - iwCT32B1_IrqEvent |= mskCT32_MR3IF; - SN_CT32B1->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status - } - } - //CAP0 - if (SN_CT32B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT32_CAP0IF) //CAP0 - { - iwCT32B1_IrqEvent |= mskCT32_CAP0IF; - SN_CT32B1->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h deleted file mode 100644 index 278a60e0bb..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT32B1_H -#define __SN32F240_CT32B1_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT32B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B1 timer and interrupt - //POLLING_METHOD: Enable CT32B1 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT32B1 PCLK -#define __CT32B1_ENABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = ENABLE - // Disable CT32B1 PCLK -#define __CT32B1_DISABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT32B1_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -extern void CT32B1_Init(void); -extern void CT32B1_NvicEnable(void); -extern void CT32B1_NvicDisable(void); -extern void CT32B1_IRQHandler(void); -#endif /*__SN32F240_CT32B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c deleted file mode 100644 index b405284c1d..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c +++ /dev/null @@ -1,160 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT32B2 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "CT32.h" -#include "CT32B2.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT32B2_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -void CT32B2_Init (void); -void CT32B2_NvicEnable (void); -void CT32B2_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : CT32B2_Init -* Description : Initialization of CT32B2 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B2_Init (void) -{ - //Enable P_CLOCK for CT32B2. - __CT32B2_ENABLE; - - //CT32B2 PCLK prescalar setting - SN_SYS1->APBCP0_b.CT32B2PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT32B2PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT32B2PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT32B2PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT32B2PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT32B2_NvicEnable -* Description : Enable CT32B2 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B2_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT32B2_IRQn); - NVIC_EnableIRQ(CT32B2_IRQn); - //NVIC_SetPriority(CT32B2_IRQn,0); //Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT32B2_NvicDisable -* Description : Disable CT32B2 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B2_NvicDisable (void) -{ - NVIC_DisableIRQ(CT32B2_IRQn); -} - - -/***************************************************************************** -* Function : TIMER32_0_IRQHandler -* Description : ISR of CT32B2 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT32B2_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT32B2->RIS; // Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT32B2->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT32_MR0IF) - { - iwCT32B2_IrqEvent |= mskCT32_MR0IF; - SN_CT32B2->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT32B2->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT32_MR1IF) - { - iwCT32B2_IrqEvent |= mskCT32_MR1IF; - SN_CT32B2->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT32B2->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT32_MR2IF) - { - iwCT32B2_IrqEvent |= mskCT32_MR2IF; - SN_CT32B2->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT32B2->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT32_MR3IF) - { - iwCT32B2_IrqEvent |= mskCT32_MR3IF; - SN_CT32B2->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status - } - } - //CAP0 - if (SN_CT32B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT32_CAP0IF) //CAP0 - { - iwCT32B2_IrqEvent |= mskCT32_CAP0IF; - SN_CT32B2->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h deleted file mode 100644 index bcbd721131..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __SN32F240_CT32B2_H -#define __SN32F240_CT32B2_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT32B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B2 timer and interrupt - //POLLING_METHOD: Enable CT32B2 timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ - // Enable CT32B2 PCLK -#define __CT32B2_ENABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = ENABLE - // Disable CT32B2 PCLK -#define __CT32B2_DISABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = DISABLE - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT32B2_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS - -extern void CT32B2_Init(void); -extern void CT32B2_NvicEnable(void); -extern void CT32B2_NvicDisable(void); -extern void CT32B2_IRQHandler(void); -#endif /*__SN32F240_CT32B2_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk deleted file mode 100644 index bb1de87c0f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk +++ /dev/null @@ -1,16 +0,0 @@ -ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c -endif -else -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c -endif - -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c - -PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c deleted file mode 100644 index 951dc5dd82..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c +++ /dev/null @@ -1,90 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: Flash related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "Flash.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -uint32_t wFLASH_PGRAM[2]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : FLASH_EraseSector -* Description : Erase assigned sector address in Flash ROM -* Input : adr - Sector start address -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void FLASH_EraseSector (uint32_t adr) -{ - SN_FLASH->CTRL = FLASH_PER; // Page Erase Enabled - SN_FLASH->ADDR = adr; // Page Address - SN_FLASH->CTRL |= FLASH_STARTE; // Start Erase - - while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY); -} - - -/***************************************************************************** -* Function : Flash_ProgramPage -* Description : Program assigned page in Flash ROM -* Input : adr - Page start address (word-alignment) of Flash -* sz - Content size to be programmed (Bytes) -* pBuf - pointer to the Source data -* Output : None -* Return : OK or FAIL -* Note : None -*****************************************************************************/ -uint32_t FLASH_ProgramPage (uint32_t adr, uint32_t sz, uint8_t *pBuf) -{ - while (sz){ - - SN_FLASH->CTRL = FLASH_PG; // Programming Enabled - SN_FLASH->ADDR = adr; - SN_FLASH->DATA = *((uint32_t *)pBuf); - - __nop();__nop();__nop();__nop();__nop();__nop(); //Must add to avoid Hard Fault!!!!!! - - while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY); - - // Check for Errors - if ((SN_FLASH->STATUS & FLASH_PGERR) == FLASH_PGERR) { - SN_FLASH->STATUS &= ~FLASH_PGERR; - return (FAIL); - } - - // Go to next Word - adr += 4; - pBuf += 4; - sz -= 4; - } - - return (OK); -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h deleted file mode 100644 index 9b2acb4a8c..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __SN32F240_FLASH_H -#define __SN32F240_FLASH_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "SN32F240.h" -#include "SN32F200_Def.h" - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -//FLASH HW -#define FLASH_PAGE_SIZE 1024 -#define FLASH_F240_MAX_ROM_SIZE 0xFFFF -#define FLASH_F230_MAX_ROM_SIZE 0x7FFF -#define FLASH_F220_MAX_ROM_SIZE 0x3FFF - - -// Flash Control Register definitions -#define FLASH_PG 0x00000001 -#define FLASH_PER 0x00000002 -#define FLASH_STARTE 0x00000040 - -// Flash Status Register definitions -#define FLASH_BUSY 0x00000001 -#define FLASH_PGERR 0x00000004 - - -/*_____ M A C R O S ________________________________________________________*/ - -//Flash Low Power Mode -#define __FLASH_LPM_DISABLE SN_FLASH->LPCTRL = 0x5AFA0000 -#define __FLASH_LPM_SLOW_MODE SN_FLASH->LPCTRL = 0x5AFA0002 - -//Flash Status -#define __FLASH_CLEAR_ERROR_STATUS SN_FLASH->STATUS &= ~FLASH_PGERR - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern uint32_t wFLASH_PGRAM[2]; - -void FLASH_EraseSector (uint32_t); -uint32_t FLASH_ProgramPage (uint32_t, uint32_t, uint8_t *); - - -#endif /* __SN32F240_FLASH_H */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c deleted file mode 100644 index 9d415472be..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c +++ /dev/null @@ -1,827 +0,0 @@ -/******************** (C) COPYRIGHT 2014 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2014/02 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: GPIO related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* 1.1 2014/02/27 SA1 1. Fix error in GPIO_Interrupt. -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "GPIO.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : GPIO_Init -* Description : GPIO Init -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_Init (void) -{ - //P2.0 as Input Pull-down - GPIO_Mode (GPIO_PORT2, GPIO_PIN0, GPIO_MODE_INPUT); - GPIO_Config (GPIO_PORT2, GPIO_PIN0, GPIO_CFG_PULL_DOWN); - //P2.0 as rising edge - GPIO_P2Trigger(GPIO_PIN0, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); - GPIO_Interrupt(GPIO_PORT2, GPIO_PIN0, GPIO_IE_EN); - - //P2.1 as Input Pull-up - GPIO_Mode (GPIO_PORT2, GPIO_PIN1, GPIO_MODE_INPUT); - GPIO_Config (GPIO_PORT2, GPIO_PIN1, GPIO_CFG_PULL_UP); - //P2.1 as falling edge - GPIO_P2Trigger(GPIO_PIN1, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); - GPIO_Interrupt(GPIO_PORT2, GPIO_PIN1, GPIO_IE_EN); - - //P2.2 as Input Repeater-mode - GPIO_Mode (GPIO_PORT2, GPIO_PIN2, GPIO_MODE_INPUT); - GPIO_Config (GPIO_PORT2, GPIO_PIN2, GPIO_CFG_REPEATER_MODE); - //P2.2 as both edge - GPIO_P2Trigger(GPIO_PIN2, GPIO_IS_EDGE, GPIO_IBS_BOTH_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); - GPIO_Interrupt(GPIO_PORT2, GPIO_PIN2, GPIO_IE_EN); - - //P2.3 as Input Pull-down - GPIO_Mode (GPIO_PORT2, GPIO_PIN3, GPIO_MODE_INPUT); - GPIO_Config (GPIO_PORT2, GPIO_PIN3, GPIO_CFG_PULL_DOWN); - //P2.3 as high level - GPIO_P2Trigger(GPIO_PIN3, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); - GPIO_Interrupt(GPIO_PORT2, GPIO_PIN3, GPIO_IE_EN); - - //P2.4 as Input Pullup - GPIO_Mode (GPIO_PORT2, GPIO_PIN4, GPIO_MODE_INPUT); - GPIO_Config (GPIO_PORT2, GPIO_PIN4, GPIO_CFG_PULL_UP); - //P2.4 as low level trigger - GPIO_P2Trigger(GPIO_PIN4, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); - GPIO_Interrupt(GPIO_PORT2, GPIO_PIN4, GPIO_IE_EN); - - //P2.5 as Output Low - GPIO_Mode (GPIO_PORT2, GPIO_PIN5, GPIO_MODE_OUTPUT); - GPIO_Clr (GPIO_PORT2, GPIO_PIN5); -} - -/***************************************************************************** -* Function : GPIO_Mode -* Description : set GPIO as input or output -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 - mode - 0 as Input - 1 as output -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode) -{ - uint32_t wGpiomode=0; - switch(port_number){ - case 0: - wGpiomode=(uint32_t)SN_GPIO0->MODE; - wGpiomode&=~(1<<(uint32_t) pin_number); - wGpiomode|=(mode<<(uint32_t) pin_number); - SN_GPIO0->MODE=wGpiomode; - wGpiomode=SN_GPIO0->MODE; //for checlk - break; - case 1: - wGpiomode=(uint32_t)SN_GPIO1->MODE; - wGpiomode&=~(1<<(uint32_t) pin_number); - wGpiomode|=(mode<<(uint32_t) pin_number); - SN_GPIO1->MODE=wGpiomode; - wGpiomode=SN_GPIO1->MODE; //for checlk - break; - case 2: - wGpiomode=(uint32_t)SN_GPIO2->MODE; - wGpiomode&=~(1<<(uint32_t) pin_number); - wGpiomode|=(mode<<(uint32_t) pin_number); - SN_GPIO2->MODE=wGpiomode; - wGpiomode=SN_GPIO2->MODE; //for checlk - break; - case 3: - wGpiomode=(uint32_t)SN_GPIO3->MODE; - wGpiomode&=~(1<<(uint32_t) pin_number); - wGpiomode|=(mode<<(uint32_t) pin_number); - SN_GPIO3->MODE=wGpiomode; - wGpiomode=SN_GPIO3->MODE; //for checlk - break; - default: - break; - } - return; -} - -/***************************************************************************** -* Function : GPIO_Set -* Description : set GPIO high -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_Set(uint32_t port_number, uint32_t pin_number) -{ - switch(port_number){ - case 0: - SN_GPIO0->BSET|=(1<BSET|=(1<BSET|=(1<BSET|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<IS; - wGpiovalue&=~(1<IS=wGpiovalue; - wGpiovalue=SN_GPIO0->IBS; - wGpiovalue&=~(1<IBS=wGpiovalue; - wGpiovalue=SN_GPIO0->IEV; - wGpiovalue&=~(1<IEV=wGpiovalue; -} - -/***************************************************************************** -* Function : GPIO_P1Trigger -* Description : set GPIO as edge or level trigger -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 - is - 0: edge sensitive - 1: event sensitive - ibs - 0: edge trigger - 1: both edge trigger - iev - 0: Rising edges or HIGH level trigger - 1: Falling edges or LOW level trigger -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) -{ - uint32_t wGpiovalue=0; - - wGpiovalue=SN_GPIO1->IS; - wGpiovalue&=~(1<IS=wGpiovalue; - wGpiovalue=SN_GPIO1->IBS; - wGpiovalue&=~(1<IBS=wGpiovalue; - wGpiovalue=SN_GPIO1->IEV; - wGpiovalue&=~(1<IEV=wGpiovalue; -} - -/***************************************************************************** -* Function : GPIO_P2Trigger -* Description : set GPIO as edge or level trigger -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 - is - 0: edge sensitive - 1: event sensitive - ibs - 0: edge trigger - 1: both edge trigger - iev - 0: Rising edges or HIGH level trigger - 1: Falling edges or LOW level trigger -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) -{ - uint32_t wGpiovalue=0; - - wGpiovalue=SN_GPIO2->IS; - wGpiovalue&=~(1<IS=wGpiovalue; - wGpiovalue=SN_GPIO2->IBS; - wGpiovalue&=~(1<IBS=wGpiovalue; - wGpiovalue=SN_GPIO2->IEV; - wGpiovalue&=~(1<IEV=wGpiovalue; -} - -/***************************************************************************** -* Function : GPIO_P3Trigger -* Description : set GPIO as edge or level trigger -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 - is - 0: edge sensitive - 1: event sensitive - ibs - 0: edge trigger - 1: both edge trigger - iev - 0: Rising edges or HIGH level trigger - 1: Falling edges or LOW level trigger -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) -{ - uint32_t wGpiovalue=0; - - wGpiovalue=SN_GPIO3->IS; - wGpiovalue&=~(1<IS=wGpiovalue; - wGpiovalue=SN_GPIO3->IBS; - wGpiovalue&=~(1<IBS=wGpiovalue; - wGpiovalue=SN_GPIO3->IEV; - wGpiovalue&=~(1<IEV=wGpiovalue; -} - -/***************************************************************************** -* Function : GPIO_Interrupt -* Description : set GPIO interrupt and NVIC -* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 - pin_number - GPIO_PIN0, 1, 2, ...,15 - enable - 0 as disable - 1 as enable -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable) -{ - switch(port_number){ - case 0: - //check SWD pin - if ((pin_number == GPIO_PIN8) || (pin_number == GPIO_PIN9)){ - if(SN_SYS0->SWDCTRL!=0x1) return; - } - SN_GPIO0->IC=0xFFFF; - SN_GPIO0->IE&=~(1<IE|=(enable<IE&=~(1<IE|=(enable<IC=0xFFFF; - NVIC_ClearPendingIRQ(P1_IRQn); - NVIC_EnableIRQ(P1_IRQn); - break; - case 2: - SN_GPIO2->IC=0xFFFF; - SN_GPIO2->IE&=~(1<IE|=(enable<EXRSTCTRL!=1) return; - } - SN_GPIO3->IC=0xFFFF; - SN_GPIO3->IE&=~(1<IE|=(enable<IC=(1<IC=(1<IC=(1<IC=(1<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<ODCTRL&=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<RIS >>pin_number); - break; - case 1: - wreturn_value=(SN_GPIO1->RIS >>pin_number); - break; - case 2: - wreturn_value=(SN_GPIO2->RIS >>pin_number); - break; - case 3: - wreturn_value=(SN_GPIO3->RIS >>pin_number); - break; - default: - break; - } - wreturn_value&=0x01; - return wreturn_value; -} - - -/***************************************************************************** -* Function : P0_IRQHandler -* Description : Set GPIO P0 IRQ -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void P0_IRQHandler(void) -{ - if (GPIO_IntStatus(GPIO_PORT0,GPIO_PIN0)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN0); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN1)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN1); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN2)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN2); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN3)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN3); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN4)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN4); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN5)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN5); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN6)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN6); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN7)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN7); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN8)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN8); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN9)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN9); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN10)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN10); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN11)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN11); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN12)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN12); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN13)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN13); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN14)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN14); - } - else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN15)==1) - { - GPIO_IntClr(GPIO_PORT0,GPIO_PIN15); - } -} - -/***************************************************************************** -* Function : P1_IRQHandler -* Description : Set GPIO P1 IRQ -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void P1_IRQHandler(void) -{ - if (GPIO_IntStatus(GPIO_PORT1,GPIO_PIN0)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN0); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN1)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN1); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN2)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN2); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN3)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN3); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN4)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN4); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN5)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN5); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN6)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN6); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN7)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN7); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN8)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN8); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN9)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN9); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN10)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN10); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN11)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN11); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN12)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN12); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN13)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN13); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN14)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN14); - } - else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN15)==1) - { - GPIO_IntClr(GPIO_PORT1,GPIO_PIN15); - } -} - -/***************************************************************************** -* Function : P2_IRQHandler -* Description : Set GPIO P2 IRQ -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void P2_IRQHandler(void) -{ - if (GPIO_IntStatus(GPIO_PORT2,GPIO_PIN0)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN0); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN1)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN1); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN2)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN2); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN3)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN3); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN4)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN4); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN5)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN5); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN6)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN6); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN7)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN7); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN8)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN8); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN9)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN9); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN10)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN10); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN11)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN11); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN12)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN12); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN13)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN13); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN14)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN14); - } - else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN15)==1) - { - GPIO_IntClr(GPIO_PORT2,GPIO_PIN15); - } -} - -/***************************************************************************** -* Function : P3_IRQHandler -* Description : Set GPIO P3 IRQ -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void P3_IRQHandler(void) -{ - if (GPIO_IntStatus(GPIO_PORT3,GPIO_PIN0)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN0); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN1)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN1); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN2)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN2); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN3)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN3); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN4)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN4); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN5)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN5); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN6)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN6); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN7)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN7); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN8)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN8); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN9)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN9); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN10)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN10); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN11)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN11); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN12)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN12); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN13)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN13); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN14)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN14); - } - else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN15)==1) - { - GPIO_IntClr(GPIO_PORT3,GPIO_PIN15); - } -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h deleted file mode 100644 index 86fb277d42..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef __SN32F240_GPIO_H -#define __SN32F240_GPIO_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4004 4000 (GPIO 0) - 0x4004 6000 (GPIO 1) - 0x4004 8000 (GPIO 2) - 0x4004 A000 (GPIO 3) -*/ - -/* GPIO Port n Data register (0x00) */ - - -/* GPIO Port n Mode register (0x04) */ -#define GPIO_MODE_INPUT 0 -#define GPIO_MODE_OUTPUT 1 - -#define GPIO_CURRENT_10MA 0 -#define GPIO_CURRENT_20MA 1 - -/* GPIO Port n Configuration register (0x08) */ -#define GPIO_CFG_PULL_UP 0 -#define GPIO_CFG_PULL_DOWN 1 -#define GPIO_CFG_PULL_INACTIVE 2 -#define GPIO_CFG_REPEATER_MODE 3 - -/* GPIO Port n Interrupt Sense register (0x0C) */ -#define GPIO_IS_EDGE 0 -#define GPIO_IS_EVENT 1 - - -/* GPIO Port n Interrupt Both-edge Sense registe (0x10) */ -#define GPIO_IBS_EDGE_TRIGGER 0 -#define GPIO_IBS_BOTH_EDGE_TRIGGER 1 - - -/* GPIO Port n Interrupt Event register (0x14) */ -#define GPIO_IEV_RISING_EDGE 0 -#define GPIO_IEV_FALLING_EDGE 1 - - -/* GPIO Port n Interrupt Enable register (0x18) */ -#define GPIO_IE_DIS 0 -#define GPIO_IE_EN 1 - - -/* GPIO Port n Raw Interrupt Status register (0x1C/0x20) */ -#define mskPIN0IF (0x1<<0) -#define mskPIN1IF (0x1<<1) -#define mskPIN2IF (0x1<<2) -#define mskPIN3IF (0x1<<3) -#define mskPIN4IF (0x1<<4) -#define mskPIN5IF (0x1<<5) -#define mskPIN6IF (0x1<<6) -#define mskPIN7IF (0x1<<7) -#define mskPIN8IF (0x1<<8) -#define mskPIN9IF (0x1<<9) -#define mskPIN10IF (0x1<<10) -#define mskPIN11IF (0x1<<11) -#define mskPIN12IF (0x1<<12) -#define mskPIN13IF (0x1<<13) -#define mskPIN14IF (0x1<<14) -#define mskPIN15IF (0x1<<15) - - -/* GPIO Port Name Define */ -//GPIO name define -#define GPIO_PORT0 0 -#define GPIO_PORT1 1 -#define GPIO_PORT2 2 -#define GPIO_PORT3 3 - -/* GPIO Pin Name Define */ -#define GPIO_PIN0 0 -#define GPIO_PIN1 1 -#define GPIO_PIN2 2 -#define GPIO_PIN3 3 -#define GPIO_PIN4 4 -#define GPIO_PIN5 5 -#define GPIO_PIN6 6 -#define GPIO_PIN7 7 -#define GPIO_PIN8 8 -#define GPIO_PIN9 9 -#define GPIO_PIN10 10 -#define GPIO_PIN11 11 -#define GPIO_PIN12 12 -#define GPIO_PIN13 13 -#define GPIO_PIN14 14 -#define GPIO_PIN15 15 - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void GPIO_Init (void); -void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode); -void GPIO_Set(uint32_t port_number, uint32_t pin_number); -void GPIO_Clr(uint32_t port_number, uint32_t pin_number); -void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); -void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); -void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); -void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); -void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable); -void GPIO_IntClr(uint32_t port_number, uint32_t pin_number); -void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value); -void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value); -uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number); -#endif /*__SN32F240_GPIO_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk deleted file mode 100644 index 24d83b0878..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk +++ /dev/null @@ -1,9 +0,0 @@ -ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c -endif -else -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c -endif - -PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h deleted file mode 100644 index ba73799838..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIOv3/hal_pal_lld.h - * @brief SN32 PAL low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef HAL_PAL_LLD_H -#define HAL_PAL_LLD_H - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -// /* Specifies palInit() without parameter, required until all platforms will -// be updated to the new style.*/ -// // #define PAL_NEW_INIT - - -/* Discarded definitions from the ST headers, the PAL driver uses its own - definitions in order to have an unified handling for all devices. - Unfortunately the ST headers have no uniform definitions for the same - objects across the various sub-families.*/ -#undef GPIOA -#undef GPIOB -#undef GPIOC -#undef GPIOD - -/** - * @name GPIO ports definitions - * @{ - */ -#define GPIOA ((SN_GPIO0_Type *)SN_GPIO0_BASE)// SN_GPIO0// -#define GPIOB ((SN_GPIO0_Type *)SN_GPIO1_BASE)// SN_GPIO1// -#define GPIOC ((SN_GPIO0_Type *)SN_GPIO2_BASE)// SN_GPIO2// -#define GPIOD ((SN_GPIO0_Type *)SN_GPIO3_BASE)// SN_GPIO3// - -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) -/** @} */ - -// GPIO0 = 40044000 -// pad = 5 - -// line = 40044005 - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of - * the GPIO address which are guaranteed to be zero. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((SN_GPIO0_Type *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for DATA register.*/ - uint32_t data; - /** Initial value for MODE register.*/ - uint32_t mode; - /** Initial value for CFG register.*/ - uint32_t cfg; - /** Initial value for IS register.*/ - uint32_t is; - /** Initial value for IBS register.*/ - uint32_t ibs; - /** Initial value for IEV register.*/ - uint32_t iev; - /** Initial value for IE register.*/ - uint32_t ie; - /** Initial value for RIS register.*/ - uint32_t ris; - /** Initial value for IC register.*/ - uint32_t ic; - /** Initial value for BSET register.*/ - uint32_t bset; - /** Initial value for BCLR register.*/ - uint32_t bclr; -} sn32_gpio_setup_t; - -/** - * @brief SN32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if SN32_HAS_GPIOA || defined(__DOXYGEN__) - /** @brief Port A setup data.*/ - sn32_gpio_setup_t PAData; -#endif -#if SN32_HAS_GPIOB || defined(__DOXYGEN__) - /** @brief Port B setup data.*/ - sn32_gpio_setup_t PBData; -#endif -#if SN32_HAS_GPIOC || defined(__DOXYGEN__) - /** @brief Port C setup data.*/ - sn32_gpio_setup_t PCData; -#endif -#if SN32_HAS_GPIOD || defined(__DOXYGEN__) - /** @brief Port D setup data.*/ - sn32_gpio_setup_t PDData; -#endif -} PALConfig; - -/** - * @brief Type of digital I/O port sized unsigned integer. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Type of digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef SN_GPIO0_Type * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the SN32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if SN32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if SN32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if SN32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if SN32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -// #define pal_lld_readlatch(port) ((port)->RIS) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (uint16_t)(bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSET = (uint16_t)(bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint16_t)(bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSET register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) { \ - uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ - ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ - (port)->DATA = w; \ -} - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) (((port)->DATA >> pad) & 1) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) ((port)->DATA = (bit << pad)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) ((port)->BSET = (0x1 << pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) ((port)->BCLR = (0x1 << pad)) - -/** - * @brief Toggles a pad logical state. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -// #define pal_lld_togglepad(port, pad) - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - * - * @notapi - */ -// #define pal_lld_setpadmode(port, pad, mode) ((port)->MODE |= mode << pad) - -#define pal_lld_setpadmode(port, pad, mode) \ - _pal_lld_setpadmode(port, pad, mode) - -#ifdef __cplusplus -extern "C" { -#endif - extern const PALConfig pal_default_config; - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setpadmode(ioportid_t port, - uint32_t pad, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* HAL_PAL_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk deleted file mode 100644 index 74bc4b733e..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk +++ /dev/null @@ -1,9 +0,0 @@ -ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c -endif -else -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c -endif - -PLATFORMINC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3 diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c deleted file mode 100644 index 2804ef6bcf..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIOv3/hal_pal_lld.c - * @brief SN32 PAL low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if defined(SN32F240B) -#define AHB2_EN_MASK SN32_GPIO_EN_MASK -#define AHB2_LPEN_MASK 0 - -#else -#error "missing or unsupported platform for GPIOv3 PAL driver" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void initgpio(sn32_gpio_t *gpiop, const sn32_gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SN32 I/O ports configuration. - * @details Ports A-D(E, F, G, H) clocks enabled. - * - * @param[in] config the SN32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ -#if defined(SN32L4XX) - RCC->AHB2ENR |= AHB2_EN_MASK; -#endif - - /* - * Initial GPIO setup. - */ -#if SN32_HAS_GPIOA - initgpio(GPIOA, &config->PAData); -#endif -#if SN32_HAS_GPIOB - initgpio(GPIOB, &config->PBData); -#endif -#if SN32_HAS_GPIOC - initgpio(GPIOC, &config->PCData); -#endif -#if SN32_HAS_GPIOD - initgpio(GPIOD, &config->PDData); -#endif -#if SN32_HAS_GPIOE - initgpio(GPIOE, &config->PEData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum - * speed. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - uint32_t moder = (mode & PAL_SN32_MODE_MASK) >> 0; - uint32_t otyper = (mode & PAL_SN32_OTYPE_MASK) >> 2; - uint32_t ospeedr = (mode & PAL_SN32_OSPEED_MASK) >> 3; - uint32_t pupdr = (mode & PAL_SN32_PUPDR_MASK) >> 5; - uint32_t altr = (mode & PAL_SN32_ALTERNATE_MASK) >> 7; - uint32_t ascr = (mode & PAL_SN32_ASCR_MASK) >> 11; - uint32_t lockr = (mode & PAL_SN32_LOCKR_MASK) >> 12; - uint32_t bit = 0; - while (true) { - if ((mask & 1) != 0) { - uint32_t altrmask, m1, m2, m4; - - altrmask = altr << ((bit & 7) * 4); - m1 = 1 << bit; - m2 = 3 << (bit * 2); - m4 = 15 << ((bit & 7) * 4); - port->OTYPER = (port->OTYPER & ~m1) | otyper; - port->ASCR = (port->ASCR & ~m1) | ascr; - port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; - port->PUPDR = (port->PUPDR & ~m2) | pupdr; - if ((mode & PAL_SN32_MODE_MASK) == PAL_SN32_MODE_ALTERNATE) { - /* If going in alternate mode then the alternate number is set - before switching mode in order to avoid glitches.*/ - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - port->MODER = (port->MODER & ~m2) | moder; - } - else { - /* If going into a non-alternate mode then the mode is switched - before setting the alternate mode in order to avoid glitches.*/ - port->MODER = (port->MODER & ~m2) | moder; - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - } - port->LOCKR = (port->LOCKR & ~m1) | lockr; - } - mask >>= 1; - if (!mask) - return; - otyper <<= 1; - ospeedr <<= 2; - pupdr <<= 2; - moder <<= 2; - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h deleted file mode 100644 index 9e118a6da4..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h +++ /dev/null @@ -1,480 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIOv3/hal_pal_lld.h - * @brief SN32 PAL low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef HAL_PAL_LLD_H -#define HAL_PAL_LLD_H - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name SN32-specific I/O mode flags - * @{ - */ -#define PAL_SN32_MODE_MASK (3U << 0U) -#define PAL_SN32_MODE_INPUT (0U << 0U) -#define PAL_SN32_MODE_OUTPUT (1U << 0U) -#define PAL_SN32_MODE_ALTERNATE (2U << 0U) -#define PAL_SN32_MODE_ANALOG (3U << 0U) - -#define PAL_SN32_OTYPE_MASK (1U << 2U) -#define PAL_SN32_OTYPE_PUSHPULL (0U << 2U) -#define PAL_SN32_OTYPE_OPENDRAIN (1U << 2U) - -#define PAL_SN32_OSPEED_MASK (3U << 3U) -#define PAL_SN32_OSPEED_LOW (0U << 3U) -#define PAL_SN32_OSPEED_MEDIUM (1U << 3U) -#define PAL_SN32_OSPEED_FAST (2U << 3U) -#define PAL_SN32_OSPEED_HIGH (3U << 3U) - -#define PAL_SN32_PUPDR_MASK (3U << 5U) -#define PAL_SN32_PUPDR_FLOATING (0U << 5U) -#define PAL_SN32_PUPDR_PULLUP (1U << 5U) -#define PAL_SN32_PUPDR_PULLDOWN (2U << 5U) - -#define PAL_SN32_ALTERNATE_MASK (15U << 7U) -#define PAL_SN32_ALTERNATE(n) ((n) << 7U) - -#define PAL_SN32_ASCR_MASK (1U << 11U) -#define PAL_SN32_ASCR_OFF (0U << 11U) -#define PAL_SN32_ASCR_ON (1U << 11U) - -#define PAL_SN32_LOCKR_MASK (1U << 12U) -#define PAL_SN32_LOCKR_OFF (0U << 12U) -#define PAL_SN32_LOCKR_ON (1U << 12U) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_SN32_MODE_ALTERNATE | \ - PAL_SN32_ALTERNATE(n)) -/** @} */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief Implemented as input. - */ -#define PAL_MODE_RESET PAL_SN32_MODE_INPUT - -/** - * @brief Implemented as analog with analog switch disabled and lock. - */ -#define PAL_MODE_UNCONNECTED (PAL_SN32_MODE_ANALOG | \ - PAL_SN32_ASCR_OFF | \ - PAL_SN32_LOCKR_ON) - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT PAL_SN32_MODE_INPUT - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_SN32_MODE_INPUT | \ - PAL_SN32_PUPDR_PULLUP) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_SN32_MODE_INPUT | \ - PAL_SN32_PUPDR_PULLDOWN) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG (PAL_SN32_MODE_ANALOG | \ - PAL_SN32_ASCR_ON) - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SN32_MODE_OUTPUT | \ - PAL_SN32_OTYPE_PUSHPULL) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SN32_MODE_OUTPUT | \ - PAL_SN32_OTYPE_OPENDRAIN) -/** @} */ - -/* Discarded definitions from the ST headers, the PAL driver uses its own - definitions in order to have an unified handling for all devices. - Unfortunately the ST headers have no uniform definitions for the same - objects across the various sub-families.*/ -#undef GPIOA -#undef GPIOB -#undef GPIOC -#undef GPIOD - -/** - * @name GPIO ports definitions - * @{ - */ -#define GPIOA ((sn32_gpio_t *)GPIOA_BASE) -#define GPIOB ((sn32_gpio_t *)GPIOB_BASE) -#define GPIOC ((sn32_gpio_t *)GPIOC_BASE) -#define GPIOD ((sn32_gpio_t *)GPIOD_BASE) -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) -/** @} */ - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of - * the GPIO address which are guaranteed to be zero. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((sn32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief SN32 GPIO registers block. - */ -typedef struct { - - volatile uint32_t MODER; - volatile uint32_t OTYPER; - volatile uint32_t OSPEEDR; - volatile uint32_t PUPDR; - volatile uint32_t IDR; - volatile uint32_t ODR; - volatile union { - uint32_t W; - struct { - uint16_t set; - uint16_t clear; - } H; - } BSRR; - volatile uint32_t LOCKR; - volatile uint32_t AFRL; - volatile uint32_t AFRH; - volatile uint32_t BRR; - volatile uint32_t ASCR; -} sn32_gpio_t; - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for MODER register.*/ - uint32_t moder; - /** Initial value for OTYPER register.*/ - uint32_t otyper; - /** Initial value for OSPEEDR register.*/ - uint32_t ospeedr; - /** Initial value for PUPDR register.*/ - uint32_t pupdr; - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for AFRL register.*/ - uint32_t afrl; - /** Initial value for AFRH register.*/ - uint32_t afrh; - /** Initial value for ASCR register.*/ - uint32_t ascr; - /** Initial value for LOCKR register.*/ - uint32_t lockr; -} sn32_gpio_setup_t; - -/** - * @brief SN32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if SN32_HAS_GPIOA || defined(__DOXYGEN__) - /** @brief Port A setup data.*/ - sn32_gpio_setup_t PAData; -#endif -#if SN32_HAS_GPIOB || defined(__DOXYGEN__) - /** @brief Port B setup data.*/ - sn32_gpio_setup_t PBData; -#endif -#if SN32_HAS_GPIOC || defined(__DOXYGEN__) - /** @brief Port C setup data.*/ - sn32_gpio_setup_t PCData; -#endif -#if SN32_HAS_GPIOD || defined(__DOXYGEN__) - /** @brief Port D setup data.*/ - sn32_gpio_setup_t PDData; -#endif -} PALConfig; - -/** - * @brief Type of digital I/O port sized unsigned integer. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Type of digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef sn32_gpio_t * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the SN32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if SN32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if SN32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if SN32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if SN32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* HAL_PAL_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h deleted file mode 100644 index 8bcf6daec1..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h +++ /dev/null @@ -1,274 +0,0 @@ -#ifndef __SN32F240_I2C_H -#define __SN32F240_I2C_H - -/*_____ I N C L U D E S ____________________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4001 8000 (I2C0) - 0x4005 A000 (I2C1) -*/ - -/* I2C n Control register (0x00) */ - //[1:1]Assert NACK (HIGH level to SDA) flag -#define I2C_NACK_NOFUNCTION 0 //No function -#define I2C_NACK 1 //An NACK will be returned during the acknowledge clock pulse on SCLn -#define mskI2C_NACK_NOFUNCTION (I2C_NACK_NOFUNCTION<<1) -#define mskI2C_NACK (I2C_NACK<<1) - - //[2:2]Assert ACK (Low level to SDA) flag -#define I2C_ACK_NOFUNCTION 0 //No function -#define I2C_ACK 1 //An ACK will be returned during the acknowledge clock pulse on SCLn -#define mskI2C_ACK_NOFUNCTION (I2C_ACK_NOFUNCTION<<2) -#define mskI2C_ACK (I2C_ACK<<2) - - //[4:4]STOP flag -#define I2C_STO_IDLE 0 //Stop condition idle -#define I2C_STO_STOP 1 //Transmit a STOP condition in master mode, or recover from an error condition in slave mode. -#define mskI2C_STO_IDLE (I2C_STO_IDLE<<4) -#define mskI2C_STO_STOP (I2C_STO_STOP<<4) - - //[5:5]START bit -#define I2C_STA_IDLE 0 //No START condition or Repeated START condition will be generated -#define I2C_STA_START 1 //transmit a START or a Repeated START condition -#define mskI2C_STA_IDLE (I2C_STA_IDLE<<5) -#define mskI2C_STA_START (I2C_STA_START<<5) - -#define I2C_I2CEN_DIS 0 //[8:8]I2C Interface enable bit -#define I2C_I2CEN_EN 1 -#define mskI2C_I2CEN_DIS (I2C_I2CEN_DIS<<8) -#define mskI2C_I2CEN_EN (I2C_I2CEN_EN<<8) - - -/* I2C n Status register (0x04) */ - //[0:0]RX done status -#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer -#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done -#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0) -#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0) - - //[1:1]ACK done status -#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK -#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK -#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1) -#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1) - - - //[2:2]NACK done status -#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK -#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK -#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2) -#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2) - - //[3:3]Stop done status -#define I2C_STOP_DN_NO_STOP 0 //No STOP bit -#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued - //SLAVE mode, a STOP condition was received -#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3) -#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3) - - //[4:4]Start done status -#define I2C_START_DN_NO_START 0 //No START bit -#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued - //SLAVE mode, a START bit was received -#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4) -#define mskI2C_START_DN_START (I2C_START_DN_START<<4) - - -#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status -#define I2C_MST_MASTER 1 -#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5) -#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5) - -#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) -#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) - - - //[6:6]Slave address check -#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address -#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode -#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6) -#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6) - - //[7:7]Slave address check -#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address -#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode. -#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7) -#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7) - - //[8:8]Lost arbitration -#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration -#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration -#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8) -#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8) - - //[9:9]Time-out status -#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout -#define I2C_TIMEOUT_TIMEOUT 1 //Timeout -#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9) -#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9) - - //[15:15]I2C Interrupt flag -#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change -#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes - //Write, Clear this flag -#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15) -#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15) - - -/* I2C n TX Data register (0x08) */ - - -/* I2C n RX Data register (0x0C) */ - - -/* I2C n Slave Address 0 register (0x10) */ - //[9:0]The I2C slave address -#define I2C_ADDR_SLAVE_ADDR0 0x07 //ADD[9:0] is valid when ADD_MODE = 1 - //ADD[7:1] is valid when ADD_MODE = 0 - - //[30:30]General call address enable bit -#define I2C_GCEN_DIS 0 //Disable -#define I2C_GCEN_EN 1 //Enable general call address (0x0) -#define mskI2C_GCEN_DIS (I2C_GCEN_DIS<<30) -#define mskI2C_GCEN_EN (I2C_GCEN_EN<<30) - - //[31:31]Slave address mode -#define I2C_ADD_MODE_7BIT 0 //7-bit address mode -#define I2C_ADD_MODE_10BIT 1 //10-bit address mode -#define mskI2C_ADD_MODE_7BIT (I2C_ADD_MODE_7BIT<<31) -#define mskI2C_ADD_MODE_10BIT (I2C_ADD_MODE_10BIT<<31) - - -/* I2C n Slave Address 1~3 register (0x14/0x18/0x1C) */ - //The I2C slave address 1~3 - //ADD[9:0] is valid when ADD_MODE = 1 - //ADD[7:1] is valid when ADD_MODE = 0 -#define I2C_ADDR_SLAVE_ADDR1 0x0A //The I2C slave address 1 -#define I2C_ADDR_SLAVE_ADDR2 0 //The I2C slave address 2 -#define I2C_ADDR_SLAVE_ADDR3 0 //The I2C slave address 3 - -#define I2C_SLAVE0 0 //Slave Number 0 -#define I2C_SLAVE1 1 //Slave Number 1 -#define I2C_SLAVE2 2 //Slave Number 2 -#define I2C_SLAVE3 3 //Slave Number 3 - -/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */ -#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time -#define I2C1_SCLHT 4 //SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle - - -/* I2C n SCL Low Time register <(I2Cn_SCLLT> (0x24) */ -#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time -#define I2C1_SCLLT 4 //SCL Loq Period Time = (SCLH+1) * I2C0_PCLK cycle - - -/* I2C n Timeout Control register (0x2C) */ -#define I2C_TO_DIS 0 //[15:0], Count for checking Timeout -#define I2C_TO_PERIOD_TIME 0 //N: Timeout period time = N*I2Cn_PCLK cycle - - -/* I2C n Monitor Mode Control register (0x30) */ -#define I2C_MMEN_MONITOR_DIS 0 //[0:0]Monitor mode enable bit -#define I2C_MMEN_MONITOR_EN 1 -#define mskI2C_MMEN_MONITOR_DIS (I2C_MMEN_MONITOR_DIS<<0) //Monitor mode enable bit -#define mskI2C_MMEN_MONITOR_EN (I2C_MMEN_MONITOR_EN<<0) - - //[1:1]SCL output enable bit -#define I2C_SCLOEN_DIS 0 //SCL output will be forced high -#define I2C_SCLOEN_EN 1 //I2C holds the clock line low until it has had time to respond to an I2C interrupt -#define mskI2C_SCLOEN_DIS (I2C_SCLOEN_DIS<<1) //SCL output enable bit -#define mskI2C_SCLOEN_EN (I2C_SCLOEN_EN<<1) - - //[2:2]Match address selection -#define I2C_MATCH_ALL_ADDR0_3 0 //Interrupt will only be generated when the address matches -#define I2C_MATCH_ALL_ANY_ADDR 1 //In monitor mode, an interrupt will be generated on ANY address received -#define mskI2C_MATCH_ALL_ADDR0_3 (I2C_MATCH_ALL_ADDR0_3<<2) -#define mskI2C_MATCH_ALL_ANY_ADDR (I2C_MATCH_ALL_ANY_ADDR<<2) - - -#define I2C_ERROR 0x00001 - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - -//------------------I2C------------------------- -//Address -extern uint16_t hwI2C_Device_Addr_I2C0; -extern uint16_t hwI2C_Device_Addr_I2C1; - -//Check Flag -extern uint32_t wI2C_TimeoutFlag; -extern uint32_t wI2C_ArbitrationFlag; - -//Error Flag -extern uint32_t wI2C_RegisterCheckError; -extern uint32_t wI2C_TotalError; - -//------------------Master Tx------------------------- -//TX FIFO -extern uint8_t bI2C_MasTxData[10]; - -//Control Flag -extern uint8_t bI2C_MasTxPointer; -extern uint32_t wI2C_MasTxCtr; - -//------------------Master Rx------------------------- -//RX FIFO -extern uint8_t bI2C_MasRxData[10]; - -//Rx Control Flag -extern uint8_t bI2C_MasRxPointer; -extern uint32_t wI2C_ReturnNackFlag; -extern uint32_t wI2C_RxControlFlag; - -//------------------Slave Rx------------------------- -//RX FIFO -extern uint8_t bI2C_SlaRxData[10]; -//Rx Control Flag -extern uint8_t bI2C_SlaRxPointer; -//extern volatile uint8_t bEndSRxFlagI2C; - -//------------------Slave Tx------------------------- -//TX FIFO -extern uint8_t bI2C_SlaTxData[10]; -//Tx Control Flag -extern uint8_t bI2C_SlaTxPointer; -//extern volatile uint8_t bEndSTxFlagI2C; - -void I2C0_Init(void); -void I2C1_Init(void); -void I2C0_Timeout_Ctrl(uint32_t wI2CTo); -void I2C1_Timeout_Ctrl(uint32_t wI2CTo); -void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen); -void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen); -void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable); -void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable); - -extern void I2C0_Enable(void); -extern void I2C0_Disable(void); -extern void I2C1_Enable(void); -extern void I2C1_Disable(void); - -void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum); -void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum); -void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum); -void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum); - - - -void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack); -void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); - -void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); - -void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack); -void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); - -void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); - - -#endif /*__SN32F240_I2C_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c deleted file mode 100644 index 882418a314..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c +++ /dev/null @@ -1,720 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: I2C0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "I2C.h" -#include "..\..\Utility\Utility.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -//------------------I2C------------------------- -//Address -uint16_t hwI2C_Device_Addr_I2C0 = 0x00; -uint16_t hwI2C_Device_Addr_I2C1 = 0x00; - -//Check Flag -uint32_t wI2C_TimeoutFlag = 0; -uint32_t wI2C_ArbitrationFlag = 0; - -//Error Flag -uint32_t wI2C_RegisterCheckError = 0; -uint32_t wI2C_TotalError = 0; - -//------------------Master Tx------------------------- -//TX FIFO -uint8_t bI2C_MasTxData[10]; - -//Tx Control Flag -uint8_t bI2C_MasTxPointer=0; -uint32_t wI2C_MasTxCtr=0; - -//------------------Master Rx------------------------- -//RX FIFO -uint8_t bI2C_MasRxData[10]; -//Rx Control Flag -uint8_t bI2C_MasRxPointer=0; -uint32_t wI2C_ReturnNackFlag=0; -uint32_t wI2C_RxControlFlag=0; - -//------------------Slave Rx------------------------- -//RX FIFO -uint8_t bI2C_SlaRxData[10]; -//Rx Control Flag -uint8_t bI2C_SlaRxPointer=0; - -//------------------Slave Tx------------------------- -//TX FIFO -uint8_t bI2C_SlaTxData[10]; -//Tx Control Flag -uint8_t bI2C_SlaTxPointer=0; - -//Mointer Mode -uint8_t bI2C0_MointerAddress = 0x00; - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : I2C0_Init -* Description : Set specified value to specified bits of assigned register -* Input : wI2C0SCLH - SCL High Time -* wI2C0SCLL - SCL Low Time -* wI2C0Mode - 0: Standard/Fast mode.1: Fast-mode Plus -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Init(void) -{ - //I2C0 interrupt enable - NVIC_ClearPendingIRQ(I2C0_IRQn); - NVIC_EnableIRQ(I2C0_IRQn); - NVIC_SetPriority(I2C0_IRQn,0); - - //Enable HCLK for I2C0 - SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0 - - //I2C speed - SN_I2C0->SCLHT = I2C0_SCLHT; - SN_I2C0->SCLLT = I2C0_SCLLT; - - //Mointer mode - //SN_I2C0->MMCTRL = 0x00; - SN_I2C0->MMCTRL = mskI2C_MATCH_ALL_ADDR0_3| - mskI2C_SCLOEN_DIS| - mskI2C_MMEN_MONITOR_DIS; - - //I2C enable - SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; -} - -/***************************************************************************** -* Function : I2C0_Timeout_Ctrl -* Description : Set specified value to specified bits of assigned register -* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Timeout_Ctrl(uint32_t wI2CTo) -{ - SN_I2C0->TOCTRL = wI2CTo; -} - -/***************************************************************************** -* Function : I2C0_Monitor_Mode_Ctrl -* Description : Set specified value to specified bits of assigned register -* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received. -* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data. -* wI2Cmmen - 0: No use. 1: Monitor mode enable bit. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen) -{ - SN_I2C0->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0); -} - -/***************************************************************************** -* Function : Set_I2C0_Address -* Description : Set specified value to specified bits of assigned register -* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1 -* bSlaveNo - Slave address number 0, 1, 2, 3 -* bSlaveAddr - Slave value -* bGCEnable - Genral call enable is 1 -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable) -{ - volatile uint16_t hwAddressCom=0; - - - if(bI2CaddMode == 0) - { - hwAddressCom = bSlaveAddr << 1; - } - else - { - hwAddressCom = bSlaveAddr; - } - - if(bGCEnable == 1) - { - SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_EN; - } - else - { - SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_DIS; - } - - if(bI2CaddMode == 1) - { - SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT; - } - else - { - SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT; - } - - switch (bSlaveNo) - { - case 0: - SN_I2C0->SLVADDR0 = hwAddressCom; - break; - - case 1: - SN_I2C0->SLVADDR1 = hwAddressCom; - break; - - case 2: - SN_I2C0->SLVADDR2 = hwAddressCom; - break; - - case 3: - SN_I2C0->SLVADDR3 = hwAddressCom; - break; - - default: - break; - } -} - -/***************************************************************************** -* Function : I2C0_Enable -* Description : I2C0 enable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Enable(void) -{ - //Enable HCLK for I2C0 - SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0 - - SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C enable -} - -/***************************************************************************** -* Function : I2C0_Disable -* Description : I2C0 disable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Disable(void) -{ - SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C disable - - //Disable HCLK for I2C0 - SN_SYS1->AHBCLKEN &=~ (0x1 << 21); //Disable clock for I2C0 -} - -/***************************************************************************** -* Function : I2C0_Master_Tx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare TX FIFO Register -* *bPointerFIFO - Declare TX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* bSlaveAddress - Set the Slave adress -* wTxNum - Set the Number of sending Data -* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer. -* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum) -{ - - //wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice - - //if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State - if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bPointerFIFO = 0x00; - wI2C_MasTxCtr = 0x00; - *bCommStop = 1; - } - else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - SN_I2C0->TXDATA = (bSlaveAddress << 0x01); - } - else - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C0->STAT) - { - /* START has been transmitted and prepare SLA+W */ - case (mskI2C_MST_MASTER|mskI2C_START_DN_START): - SN_I2C0->TXDATA = (bSlaveAddress << 0x01); - break; - - /* SLA+W or Data has been transmitted and ACK has been received */ - case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): - if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - SN_I2C0->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - } - else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - if(wRepeatTX == 0) //No Repeat - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatTX == 1) //Repeat Start - { - SN_I2C0->CTRL |= mskI2C_STA_START; - wI2C_MasTxCtr++; - } - else if(wRepeatTX == 2) //Repeat Both - { - SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - wI2C_MasTxCtr++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - } - else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C0->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - } - else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /* SLA+W or Data has been transmitted and NACK has been received */ - case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK): - if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - if(wRepeatTX == 0) //No Repeat - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatTX == 1) //Repeat Start - { - SN_I2C0->CTRL |= mskI2C_STA_START; - wI2C_MasTxCtr++; - } - else if(wRepeatTX == 2) //Repeat Both - { - SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - wI2C_MasTxCtr++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - } - else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C0_Master_Rx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* bSlaveAddress - Set the Slave adress -* wRxNum - Set the Number of getting Data -* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer. -* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum) -{ - uint32_t wDeboundNum = 0; - - //if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State - if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if(((SN_I2C0->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bPointerFIFO = 0x00; - wI2C_MasTxCtr = 0x00; - *bCommStop = 1; - wI2C_RxControlFlag = 0x00; - wI2C_ReturnNackFlag = 0x00; - } - else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01; - } - else - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C0->STAT) - { - /* START has been transmitted and prepare to send address */ - case (mskI2C_MST_MASTER|mskI2C_START_DN_START): - SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01; - break; - - /* Received an ACK */ - case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): - if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0)) - { - SN_I2C0->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1)) - { - SN_I2C0->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else - { - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - } - break; - - /* RX with ACK/NACK transfer is down */ - case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE): - *bDataFIFO = SN_I2C0->RXDATA; - *bPointerFIFO = *bPointerFIFO + 1; - - if(wI2C_ReturnNackFlag == 0x00) - { - wDeboundNum = wRxNum-1; - } - else if(wI2C_ReturnNackFlag == 0x01) - { - wDeboundNum = wRxNum+wReRxNum; - } - - if(wI2C_ReturnNackFlag == 0x02) - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00)) - { - - if(wRepeatRX == 0) //No Repeat - { - SN_I2C0->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatRX == 1) //Repeat Start - { - SN_I2C0->CTRL |= mskI2C_STA_START; - } - else if(wRepeatRX == 2) //Repeat Both - { - SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - wI2C_RxControlFlag = 1; - } - else if((*bPointerFIFO < (wDeboundNum))) - { - //Return ACK - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - } - else if((*bPointerFIFO >= (wDeboundNum))) - { - //Return NACK - SN_I2C0->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - - -/***************************************************************************** -* Function : I2C0_Slave_Rx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* wNumForNack - Return NACK when getting the number of data is wNumForNack. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack) -{ - - if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C0->STAT) - { - /* Slave addess hit for Rx */ - case mskI2C_SLV_RX_MATCH_ADDR: - if(wNumForNack == 0) - { - SN_I2C0->CTRL |= mskI2C_ACK;; //ACK - } - else if(wNumForNack == 1) - { - SN_I2C0->CTRL |= mskI2C_NACK; //NACK - } - else - { - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - } - break; - - /* DATA has been received and ACK/NACK has been returned */ - case mskI2C_RX_DN_HANDSHAKE: - *bDataFIFO = SN_I2C0->RXDATA ; - *bPointerFIFO = *bPointerFIFO + 1; - - if(wNumForNack == 0) - { - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - } - else if(*bPointerFIFO == (wNumForNack-1)) - { - SN_I2C0->CTRL |= mskI2C_NACK; //NACK - } - else - { - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C0_Slave_Tx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare TX FIFO Register -* *bPointerFIFO - Declare TX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) -{ - if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C0->STAT) - { - /* Slave addess hit for Tx */ - case mskI2C_SLV_TX_MATCH_ADDR: - SN_I2C0->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - break; - - /* Received ACK */ - case mskI2C_ACK_STAT_RECEIVED_ACK: - SN_I2C0->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - break; - - /* Received NACK */ - case mskI2C_NACK_STAT_RECEIVED_NACK: - SN_I2C0->CTRL |= mskI2C_ACK; //For release SCL and SDA - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C0_Mointer_Mode -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) -{ - if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C0->STAT) - { - /* Slave addess hit for Rx */ - case mskI2C_SLV_RX_MATCH_ADDR: - bI2C0_MointerAddress = SN_I2C0->RXDATA; - bI2C0_MointerAddress = bI2C0_MointerAddress >> 1; - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - - break; - - /* Slave addess hit for Tx */ - case mskI2C_SLV_TX_MATCH_ADDR: - bI2C0_MointerAddress = SN_I2C0->RXDATA; - bI2C0_MointerAddress = bI2C0_MointerAddress >> 1; - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - - break; - /* DATA has been received*/ - case I2C_RX_DN_HANDSHAKE: - *bDataFIFO = SN_I2C0->RXDATA; - *bPointerFIFO = *bPointerFIFO + 1; - SN_I2C0->CTRL |= mskI2C_ACK; //ACK - - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c deleted file mode 100644 index 583cce98ae..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c +++ /dev/null @@ -1,675 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: I2C1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "I2C.h" -#include "..\..\Utility\Utility.h" -/*_____ D E C L A R A T I O N S ____________________________________________*/ -//Mointer Mode -uint8_t bI2C1_MointerAddress = 0x00; - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - - -/***************************************************************************** -* Function : I2C1_Init -* Description : Set specified value to specified bits of assigned register -* Input : wI2C1SCLH - SCL High Time -* wI2C1SCLL - SCL Low Time -* wI2C1Mode - 0: Standard/Fast mode.1: Fast-mode Plus -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Init(void) -{ - //I2C1 interrupt enable - NVIC_ClearPendingIRQ(I2C1_IRQn); - NVIC_EnableIRQ(I2C1_IRQn); - NVIC_SetPriority(I2C1_IRQn,0); - - //Enable HCLK for I2C1 - SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1 - - //I2C speed - SN_I2C1->SCLHT = I2C1_SCLHT; - SN_I2C1->SCLLT = I2C1_SCLLT; - - - //I2C enable - SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; - - //I2C1 address set - Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE0, I2C_ADDR_SLAVE_ADDR0, I2C_GCEN_DIS); - Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE1, I2C_ADDR_SLAVE_ADDR1, I2C_GCEN_DIS); -} - -/***************************************************************************** -* Function : I2C1_Timeout_Ctrl -* Description : Set specified value to specified bits of assigned register -* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C01_Timeout_Ctrl(uint32_t wI2CTo) -{ - SN_I2C1->TOCTRL = wI2CTo; -} - -/***************************************************************************** -* Function : I2C1_Monitor_Mode_Ctrl -* Description : Set specified value to specified bits of assigned register -* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received. -* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data. -* wI2Cmmen - 0: No use. 1: Monitor mode enable bit. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen) -{ - SN_I2C1->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0); -} - -/***************************************************************************** -* Function : Set_I2C1_Address -* Description : Set specified value to specified bits of assigned register -* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1 -* bSlaveNo - Slave address number 0, 1, 2, 3 -* bSlaveAddr - Slave value -* bGCEnable - Genral call enable is 1 -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable) -{ - volatile uint16_t hwAddressCom=0; - - - if(bI2CaddMode == 0) - { - hwAddressCom = bSlaveAddr << 1; - } - else - { - hwAddressCom = bSlaveAddr; - } - - if(bGCEnable == 1) - { - SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_EN; - } - else - { - SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_DIS; - } - - if(bI2CaddMode == 1) - { - SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT; - } - else - { - SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT; - } - - switch (bSlaveNo) - { - case 0: - SN_I2C1->SLVADDR0 = hwAddressCom; - break; - - case 1: - SN_I2C1->SLVADDR1 = hwAddressCom; - break; - - case 2: - SN_I2C1->SLVADDR2 = hwAddressCom; - break; - - case 3: - SN_I2C1->SLVADDR3 = hwAddressCom; - break; - - default: - break; - } -} - -/***************************************************************************** -* Function : I2C1_Enable -* Description : I2C1 enable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Enable(void) -{ - //Enable HCLK for I2C1 - SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1 - - SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C1 enable -} - -/***************************************************************************** -* Function : I2C1_Disable -* Description : I2C1 disable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Disable(void) -{ - SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C1 disable - - //Disable HCLK for I2C1 - SN_SYS1->AHBCLKEN &=~ (0x1 << 20); //Disable clock for I2C1 -} - -/***************************************************************************** -* Function : I2C1_Master_Tx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare TX FIFO Register -* *bPointerFIFO - Declare TX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* bSlaveAddress - Set the Slave adress -* wTxNum - Set the Number of sending Data -* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer. -* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum) -{ - - //wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice - - if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bPointerFIFO = 0x00; - wI2C_MasTxCtr = 0x00; - *bCommStop = 1; - } - else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - SN_I2C1->TXDATA = (bSlaveAddress << 0x01); - } - else - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C1->STAT) - { - /* START has been transmitted and prepare SLA+W */ - case (mskI2C_MST_MASTER|mskI2C_START_DN_START): - SN_I2C1->TXDATA = (bSlaveAddress << 0x01); - break; - - /* SLA+W or Data has been transmitted and ACK has been received */ - case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): - if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - SN_I2C1->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - } - else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - if(wRepeatTX == 0) //No Repeat - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatTX == 1) //Repeat Start - { - SN_I2C1->CTRL |= mskI2C_STA_START; - wI2C_MasTxCtr++; - } - else if(wRepeatTX == 2) //Repeat Both - { - SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - wI2C_MasTxCtr++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - } - else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C1->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - } - else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /* SLA+W or Data has been transmitted and NACK has been received */ - case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK): - if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) - { - if(wRepeatTX == 0) //No Repeat - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatTX == 1) //Repeat Start - { - SN_I2C1->CTRL |= mskI2C_STA_START; - wI2C_MasTxCtr++; - } - else if(wRepeatTX == 2) //Repeat Both - { - SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - wI2C_MasTxCtr++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - } - else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C1_Master_Rx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* bSlaveAddress - Set the Slave adress -* wRxNum - Set the Number of getting Data -* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer. -* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum) -{ - uint32_t wDeboundNum = 0; - - if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if(((SN_I2C1->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bPointerFIFO = 0x00; - wI2C_MasTxCtr = 0x00; - *bCommStop = 1; - wI2C_RxControlFlag = 0x00; - wI2C_ReturnNackFlag = 0x00; - } - else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01; - } - else - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C1->STAT) - { - /* START has been transmitted and prepare to send address */ - case (mskI2C_MST_MASTER|mskI2C_START_DN_START): - SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01; - break; - - /* Received an ACK */ - case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): - if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0)) - { - SN_I2C1->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1)) - { - SN_I2C1->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else - { - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - } - break; - - /* RX with ACK/NACK transfer is down */ - case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE): - *bDataFIFO = SN_I2C1->RXDATA; - *bPointerFIFO = *bPointerFIFO + 1; - - if(wI2C_ReturnNackFlag == 0x00) - { - wDeboundNum = wRxNum-1; - } - else if(wI2C_ReturnNackFlag == 0x01) - { - wDeboundNum = wRxNum+wReRxNum; - } - - if(wI2C_ReturnNackFlag == 0x02) - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00)) - { - - if(wRepeatRX == 0) //No Repeat - { - SN_I2C1->CTRL |= mskI2C_STO_STOP; - } - else if(wRepeatRX == 1) //Repeat Start - { - SN_I2C1->CTRL |= mskI2C_STA_START; - } - else if(wRepeatRX == 2) //Repeat Both - { - SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - wI2C_RxControlFlag = 1; - } - else if((*bPointerFIFO < (wDeboundNum))) - { - //Return ACK - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - } - else if((*bPointerFIFO >= (wDeboundNum))) - { - //Return NACK - SN_I2C1->CTRL |= mskI2C_NACK; //NACK - wI2C_ReturnNackFlag++; - } - else - { - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C1_Slave_Rx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* wNumForNack - Return NACK when getting the number of data is wNumForNack. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack) -{ - - if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C1->STAT) - { - /* Slave addess hit for Rx */ - case mskI2C_SLV_RX_MATCH_ADDR: - if(wNumForNack == 0) - { - SN_I2C1->CTRL |= mskI2C_ACK;; //ACK - } - else if(wNumForNack == 1) - { - SN_I2C1->CTRL |= mskI2C_NACK; //NACK - } - else - { - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - } - break; - - /* DATA has been received and ACK/NACK has been returned */ - case mskI2C_RX_DN_HANDSHAKE: - *bDataFIFO = SN_I2C1->RXDATA ; - *bPointerFIFO = *bPointerFIFO + 1; - - if(wNumForNack == 0) - { - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - } - else if(*bPointerFIFO == (wNumForNack-1)) - { - SN_I2C1->CTRL |= mskI2C_NACK; //NACK - } - else - { - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - } - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C1_Slave_Tx -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare TX FIFO Register -* *bPointerFIFO - Declare TX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) -{ - if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C1->STAT) - { - /* Slave addess hit for Tx */ - case mskI2C_SLV_TX_MATCH_ADDR: - SN_I2C1->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - break; - - /* Received ACK */ - case mskI2C_ACK_STAT_RECEIVED_ACK: - SN_I2C1->TXDATA = *bDataFIFO; - *bPointerFIFO = *bPointerFIFO + 1; - break; - - /* Received NACK */ - case mskI2C_NACK_STAT_RECEIVED_NACK: - SN_I2C1->CTRL |= mskI2C_ACK; //For release SCL and SDA - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} - -/***************************************************************************** -* Function : I2C1_Mointer_Mode -* Description : Set specified value to specified bits of assigned register -* Input : *bDataFIFO - Declare RX FIFO Register -* *bPointerFIFO - Declare RX FIFO Pointer Register -* *bCommStop - Declare the Register when get the STOP information -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) -{ - if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_TimeoutFlag = 1; - } - else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - wI2C_ArbitrationFlag = 1; - } - else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - *bCommStop = 0x01; - } - else - { - SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag - - switch (SN_I2C1->STAT) - { - /* Slave addess hit for Rx */ - case mskI2C_SLV_RX_MATCH_ADDR: - bI2C1_MointerAddress = SN_I2C1->RXDATA; - bI2C1_MointerAddress = bI2C1_MointerAddress >> 1; - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - - break; - - /* Slave addess hit for Tx */ - case mskI2C_SLV_TX_MATCH_ADDR: - bI2C1_MointerAddress = SN_I2C1->RXDATA; - bI2C1_MointerAddress = bI2C1_MointerAddress >> 1; - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - - break; - /* DATA has been received*/ - case I2C_RX_DN_HANDSHAKE: - *bDataFIFO = SN_I2C1->RXDATA; - *bPointerFIFO = *bPointerFIFO + 1; - SN_I2C1->CTRL |= mskI2C_ACK; //ACK - - break; - - /*Error State Check*/ - default: - wI2C_RegisterCheckError |= I2C_ERROR; - wI2C_TotalError++; - break; - } - } -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c deleted file mode 100644 index 0c5bd87772..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c +++ /dev/null @@ -1,153 +0,0 @@ -/******************** (C) COPYRIGHT 2014 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2014/02 -* AUTHOR: SA1 -* IC: SN32F240/730/220 -* DESCRIPTION: I2S related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* 2.0 2014/02/27 SA1 1. Update I2S functions. -* 3.2 2019/05/31 SA1 1. Fix I2S_Master_Init and I2S_Slave_Init. -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "I2S.h" -#include "..\..\Utility\Utility.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/************************************************************** -* Function : I2S_Master_INIT -* Description : Set I2S as master -* Input : None -* Output : None -* Return : None -* Note : None -****************************************************************/ -void I2S_Master_Init(void) -{ - __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S - - SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN; //I2S enable bit - SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] - SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level - SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; //TX FIFO Threshold level - - SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length - __I2S_RESET_RXFIFO; //Clear I2S RX FIFO - __I2S_RESET_TXFIFO; //Clear I2S TX FIFO - SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit - SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; //Transmit enable bit - - SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format - SN_I2S->CTRL_b.MS=I2S_MS_MASTER_MODE; //Master selection bit - SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit - SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; //Mute enable bit - - //I2S clk - SN_I2S->CLK = mskI2S_CLKSEL_HCLK| //I2S clock source selection - mskI2S_BCLKDIV_DIV| //MCLK/n, n = 2, 4, 6, 8, ...,512 - mskI2S_MCLKSEL_I2S_PCLK| //MCLK source of master is from I2S_PCLK - mskI2S_MCLKOEN_OUTPUT_DIS| //MCLK output enable bit - mskI2S_MCLKDIV_DIV3; //MCLK = MCLK source / 6 -} - -/************************************************************** -* Function : I2S_Slave_Init -* Description : Set I2S as slave -* Input : None -* Output : None -* Return : None -* Note : None -****************************************************************/ -void I2S_Slave_Init(void) -{ - __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S - - SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit - SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] - SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level - SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; - - SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length - __I2S_RESET_RXFIFO; //Clear I2S RX FIFO - __I2S_RESET_TXFIFO; //Clear I2S TX FIFO - SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit - SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; - - SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format - SN_I2S->CTRL_b.MS=I2S_MS_SLAVE_MODE; //Master selection bit - SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit - SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; -} - -/***************************************************************************** -* Function : I2S_Enable -* Description : I2S enable -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2S_Enable(void) -{ - __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S - - SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit - __I2S_RESET_TXFIFO; - __I2S_RESET_RXFIFO; -} - -/***************************************************************************** -* Function : I2S_Disable -* Description : I2S disable -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void I2S_Disable(void) -{ - SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_DIS; //I2S disable bit - - __I2S_DISABLE_I2SHCLK; //Disable HCLK for I2S -} - -/********************************** -* Function : I2S_Interrupt_Enable -* Description : I2S interrupt enable -* Input : None -* Output : None -* Return : None -* Note : None -**********************************/ -void I2S_Interrupt_Enable(void) -{ - SN_I2S->IC = mskI2S_RXFIFOTHIC| //Clear RXFIFOTHIF bit - mskI2S_TXFIFOTHIC| //Clear TXFIFOTHIF bit - mskI2S_RXFIFOUDIC| //Clear RXFIFOOUDIF bit - mskI2S_TXFIFOOVIC; //Clear TXFIFOOVIF bit - - SN_I2S->IE = mskI2S_TXFIFOOVFIEN_EN| //TX FIFO overflow interrupt enable bit - mskI2S_RXFIFOUDFIEN_EN| //RX FIFO underflow interrupt enable bit - mskI2S_TXFIFOTHIEN_EN| //TX FIFO threshold interrupt enable bit - mskI2S_RXFIFOTHIEN_EN; //RX FIFO threshold interrupt enable bit -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h deleted file mode 100644 index 8a54e4439e..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h +++ /dev/null @@ -1,216 +0,0 @@ -#ifndef __SN32F240_I2S_H -#define __SN32F240_I2S_H - -/*_____ I N C L U D E S ____________________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4001 A000 -*/ - -/* I2S Control register (0x00) */ - -#define I2S_START_DIS 0 //[0:0]Start Transmit/Receive bit -#define I2S_START_EN 1 -#define mskI2S_START_DIS (mskI2S_START_DIS<<0) -#define mskI2S_START_EN (mskI2S_START_EN<<0) - -#define I2S_MUTE_DIS 0 //[1:1]Mute enable bit -#define I2S_MUTE_EN 1 -#define mskI2S_MUTE_DIS (I2S_MUTE_DIS<<1) -#define mskI2S_MUTE_EN (I2S_MUTE_EN<<1) - -#define I2S_MONO_STERO 0 //[2:2]Mono/Stereo selection bit -#define I2S_MONO_MONO 1 -#define mskI2S_MONO_STERO (I2S_MONO_STERO<<2) -#define mskI2S_MONO_MONO (I2S_MONO_MONO<<2) - -#define I2S_MS_MASTER_MODE 0 //[3:3]Master/Slave selection bit -#define I2S_MS_SLAVE_MODE 1 -#define mskI2S_MS_MASTER_MODE (I2S_MS_MASTER_MODE<<3) -#define mskI2S_MS_SLAVE_MODE (I2S_MS_SLAVE_MODE<<3) - - //[5:4]I2S operation format -#define I2S_FORMAT_STANDARD 0 //Standard I2S format -#define I2S_FORMAT_LEFTJUST 1 //Left-justified format -#define I2S_FORMAT_RIGHTJUST 2 //Right(MSB)-justified format -#define mskI2S_FORMAT_STANDARD (I2S_FORMAT_STANDARD<<4) -#define mskI2S_FORMAT_LEFTJUST (I2S_FORMAT_LEFTJUST<<4) -#define mskI2S_FORMAT_RIGHTJUST (I2S_FORMAT_RIGHTJUST<<4) - -#define I2S_TXEN_DIS 0 //[6:6]Transmit enable bit -#define I2S_TXEN_EN 1 -#define mskI2S_TXEN_DIS (I2S_TXEN_DIS<<6) -#define mskI2S_TXEN_EN (I2S_TXEN_EN<<6) - -#define I2S_RXEN_DIS 0 //[7:7]Receiver enable bit -#define I2S_RXEN_EN 1 -#define mskI2S_RXEN_DIS (I2S_RXEN_DIS<<7) -#define mskI2S_RXEN_EN (I2S_RXEN_EN<<7) - -#define I2S_CLRTXFIFO_RESET_TXFIFO 1 //[8:8]Clear I2S TX FIFO -#define I2S_CLRRXFIFO_RESET_RXFIFO 1 //[9:9]Clear I2S TX FIFO - -#define I2S_DL_8BITS 0 //[11:10]I2S Data Length -#define I2S_DL_16BITS 1 -#define I2S_DL_24BITS 2 -#define I2S_DL_32BITS 3 - -#define I2S_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level[2:0] -#define I2S_TXFIFOTH_1 1 -#define I2S_TXFIFOTH_2 2 -#define I2S_TXFIFOTH_3 3 -#define I2S_TXFIFOTH_4 4 -#define I2S_TXFIFOTH_5 5 -#define I2S_TXFIFOTH_6 6 -#define I2S_TXFIFOTH_7 7 - -#define I2S_RXFIFOTH_0 0 //[18:16]RX FIFO Threshold level[2:0] -#define I2S_RXFIFOTH_1 1 -#define I2S_RXFIFOTH_2 2 -#define I2S_RXFIFOTH_3 3 -#define I2S_RXFIFOTH_4 4 -#define I2S_RXFIFOTH_5 5 -#define I2S_RXFIFOTH_6 6 -#define I2S_RXFIFOTH_7 7 - -#define I2S_CHLENGTH_8BITS 7 //[24:20]Bit number of single channel[4:0] -#define I2S_CHLENGTH_9BITS 8 -#define I2S_CHLENGTH_10BITS 9 -#define I2S_CHLENGTH_11BITS 10 -#define I2S_CHLENGTH_12BITS 11 -#define I2S_CHLENGTH_13BITS 12 -#define I2S_CHLENGTH_14BITS 13 -#define I2S_CHLENGTH_15BITS 14 -#define I2S_CHLENGTH_16BITS 15 -#define I2S_CHLENGTH_17BITS 16 -#define I2S_CHLENGTH_18BITS 17 -#define I2S_CHLENGTH_19BITS 18 -#define I2S_CHLENGTH_20BITS 19 -#define I2S_CHLENGTH_21BITS 20 -#define I2S_CHLENGTH_22BITS 21 -#define I2S_CHLENGTH_23BITS 22 -#define I2S_CHLENGTH_24BITS 23 -#define I2S_CHLENGTH_25BITS 24 -#define I2S_CHLENGTH_26BITS 25 -#define I2S_CHLENGTH_27BITS 26 -#define I2S_CHLENGTH_28BITS 27 -#define I2S_CHLENGTH_29BITS 28 -#define I2S_CHLENGTH_30BITS 29 -#define I2S_CHLENGTH_31BITS 30 -#define I2S_CHLENGTH_32BITS 31 - -#define I2S_I2SEN_DIS 0 //[31:31]I2S enable bit -#define I2S_I2SEN_EN 1 -#define mskI2S_I2SEN_DIS (I2S_I2SEN_DIS<<31) -#define mskI2S_I2SEN_EN (I2S_I2SEN_EN<<31) - -/* I2S Clock register (0x04) */ - //[2:0]MCLK divider -#define I2S_MCLKDIV_DIV0 0 //MCLK = MCLK source -#define mskI2S_MCLKDIV_DIV0 (I2S_MCLKDIV_DIV0<<0) -#define I2S_MCLKDIV_DIV1 1 //MCLK = MCLK source / 2 -#define mskI2S_MCLKDIV_DIV1 (I2S_MCLKDIV_DIV1<<0) -#define I2S_MCLKDIV_DIV2 2 //MCLK = MCLK source / 4 -#define mskI2S_MCLKDIV_DIV2 (I2S_MCLKDIV_DIV2<<0) -#define I2S_MCLKDIV_DIV3 3 //MCLK = MCLK source / 6 -#define mskI2S_MCLKDIV_DIV3 (I2S_MCLKDIV_DIV3<<0) -#define I2S_MCLKDIV_DIV4 4 //MCLK = MCLK source / 8 -#define mskI2S_MCLKDIV_DIV4 (I2S_MCLKDIV_DIV4<<0) -#define I2S_MCLKDIV_DIV5 5 //MCLK = MCLK source / 10 -#define mskI2S_MCLKDIV_DIV5 (I2S_MCLKDIV_DIV5<<0) -#define I2S_MCLKDIV_DIV6 6 //MCLK = MCLK source / 12 -#define mskI2S_MCLKDIV_DIV6 (I2S_MCLKDIV_DIV6<<0) -#define I2S_MCLKDIV_DIV7 7 //MCLK = MCLK source / 14 -#define mskI2S_MCLKDIV_DIV7 (I2S_MCLKDIV_DIV7<<0) - - -#define I2S_MCLKOEN_OUTPUT_DIS 0 //[3:3]MCLK output enable bit -#define I2S_MCLKOEN_OUTPUT_EN 1 -#define mskI2S_MCLKOEN_OUTPUT_DIS (I2S_MCLKOEN_OUTPUT_DIS<<3) -#define mskI2S_MCLKOEN_OUTPUT_EN (I2S_MCLKOEN_OUTPUT_EN<<3) - - //[4:4]MCLK source selection bit -#define I2S_MCLKSEL_I2S_PCLK 0 //MCLK source of master is from I2S_PCLK -#define I2S_MCLKSEL_GPIO 1 //MCLK source of master is from GPIO -#define mskI2S_MCLKSEL_I2S_PCLK (I2S_MCLKSEL_I2S_PCLK<<4) -#define mskI2S_MCLKSEL_GPIO (I2S_MCLKSEL_GPIO<<4) - - //[15:8]BCLK divider -#define I2S_BCLKDIV_DIV 0 // MCLK/n, n = 2, 4, 6, 8, ...,512 -#define mskI2S_BCLKDIV_DIV (I2S_BCLKDIV_DIV<<8) - //[16:16]I2S clock source selection -#define I2S_CLKSEL_HCLK 0 //HCLK -#define I2S_CLKSEL_EHS 1 //EHS -#define mskI2S_CLKSEL_HCLK (I2S_CLKSEL_HCLK<<16) -#define mskI2S_CLKSEL_EHS (I2S_CLKSEL_EHS<<16) - - -/* I2S Status register (0x08) */ -#define mskI2S_I2SINT (0x1<<0) //I2S interrupt flag -#define mskI2S_RIGHTCH (0x1<<1) //Current channel status -#define mskI2S_TXFIFOTHF (0x1<<6) //TX FIFO threshold flag -#define mskI2S_RXFIFOTHF (0x1<<7) //RX FIFO threshold flag -#define mskI2S_TXFIFOFULL (0x1<<8) //TX FIFO full flag -#define mskI2S_RXFIFOFULL (0x1<<9) //RX FIFO full flag -#define mskI2S_TXFIFOEMPTY (0x1<<10) //TX FIFO empty flag -#define mskI2S_RXFIFOEMPTY (0x1<<11) //RX FIFO empty flag -#define mskI2S_TXFIFOLV (0xf<<12) //TX FIFO used level -#define mskI2S_RXFIFOLV (0xf<<17) //RX FIFO used level - - -/* I2S Interrupt Enable register (0x0C) */ -#define I2S_TXFIFOOVFIEN_DIS 0 //[4:4]TX FIFO overflow interrupt enable bit -#define I2S_TXFIFOOVFIEN_EN 1 -#define mskI2S_TXFIFOOVFIEN_DIS (I2S_TXFIFOOVFIEN_DIS<<4) -#define mskI2S_TXFIFOOVFIEN_EN (I2S_TXFIFOOVFIEN_EN<<4) - -#define I2S_RXFIFOUDFIEN_DIS 0 //[5:5]RX FIFO underflow interrupt enable bit -#define I2S_RXFIFOUDFIEN_EN 1 -#define mskI2S_RXFIFOUDFIEN_DIS (I2S_RXFIFOUDFIEN_DIS<<5) -#define mskI2S_RXFIFOUDFIEN_EN (I2S_RXFIFOUDFIEN_EN<<5) - -#define I2S_TXFIFOTHIEN_DIS 0 //[6:6]TX FIFO threshold interrupt enable bit -#define I2S_TXFIFOTHIEN_EN 1 -#define mskI2S_TXFIFOTHIEN_DIS (I2S_TXFIFOTHIEN_DIS<<6) -#define mskI2S_TXFIFOTHIEN_EN (I2S_TXFIFOTHIEN_EN<<6) - -#define I2S_RXFIFOTHIEN_DIS 0 //[7:7]RX FIFO threshold interrupt enable bit -#define I2S_RXFIFOTHIEN_EN 1 -#define mskI2S_RXFIFOTHIEN_DIS (I2S_RXFIFOTHIEN_DIS<<7) -#define mskI2S_RXFIFOTHIEN_EN (I2S_RXFIFOTHIEN_EN<<7) - - -/* I2S Raw Interrupt Status register (0x10) */ -/* I2S Interrupt Clear register (0x14) */ -#define mskI2S_TXFIFOOVIF (0x1<<4) //TX FIFO overflow interrupt flag -#define mskI2S_TXFIFOOVIC mskI2S_TXFIFOOVIF -#define mskI2S_RXFIFOUDIF (0x1<<5) //RX FIFO underflow interrupt flag -#define mskI2S_RXFIFOUDIC mskI2S_RXFIFOUDIF -#define mskI2S_TXFIFOTHIF (0x1<<6) //TX FIFO threshold interrupt flag -#define mskI2S_TXFIFOTHIC mskI2S_TXFIFOTHIF -#define mskI2S_RXFIFOTHIF (0x1<<7) //RX FIFO threshold interrupt flag -#define mskI2S_RXFIFOTHIC mskI2S_RXFIFOTHIF - - -/*_____ M A C R O S ________________________________________________________*/ -//I2S HCLK Enable/Disable -#define __I2S_ENABLE_I2SHCLK SN_SYS1->AHBCLKEN |= (1<<22) -#define __I2S_DISABLE_I2SHCLK SN_SYS1->AHBCLKEN &= ~(1<<22) - -//Reset I2S FIFO -#define __I2S_RESET_TXFIFO (SN_I2S->CTRL_b.CLRTXFIFO = I2S_CLRTXFIFO_RESET_TXFIFO) -#define __I2S_RESET_RXFIFO (SN_I2S->CTRL_b.CLRRXFIFO = I2S_CLRRXFIFO_RESET_RXFIFO) - -//I2S Start -#define __I2S_START (SN_I2S->CTRL_b.START = 1) - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void I2S_Master_Init(void); -void I2S_Slave_Init(void); -void I2S_Enable(void); -void I2S_Disable(void); -void I2S_Interrupt_Enable(void); - -#endif /*__SN32F240_I2S_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c deleted file mode 100644 index 68c47767cc..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c +++ /dev/null @@ -1,181 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: LCD related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "LCD.h" -#include "..\..\System\SYS_con_drive.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -#if LCD_TYPE == LCD_R_TYPE -/*********************************************************************************** -* Function : LCD_RtypeInit -* Description : Initialization of R-type LCD driver -* Input : None -* Output : None -* Return : None -* Note : User shall follow the notice in 16.6 R-TYPE LCD APPLICATION CIRCUIT -* to take care of the circuit. -***********************************************************************************/ -void LCD_RtypeInit(void) -{ - __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD - - //<-------------------- TODO: User modify on demand BEGIN --------------------> - //Setup LCD Driving ability, Clock rate, Duty, Bias, Type - SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|mskLCD_ONE_THIRD_BIAS|mskLCD_R_TYPE); - - LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source - - //Setup ITB bit, R-type resistance - SN_LCD->CTRL1 = (0|mskLCD_REF_400K); //Only value 0 is allowed for ITB bit - - __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins - __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins - //<-------------------- TODO: User modify on demand END --------------------> - - __LCD_ENABLE; //Enable LCD -} -#endif -#if LCD_TYPE == LCD_1C_TYPE -/*********************************************************************************** -* Function : LCD_1CtypeInit -* Description : Initialization of 1C-type LCD driver -* Input : None -* Output : None -* Return : None -* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT -* to take care of the circuit. -***********************************************************************************/ -void LCD_1CtypeInit(void) -{ - __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD - - //<-------------------- TODO: User modify on demand BEGIN --------------------> - //Setup LCD Driving ability, Clock rate, Duty, Bias, Type - SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY| - mskLCD_ONE_THIRD_BIAS|mskLCD_1C_TYPE); - - LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source - - //Setup IT1 bits, IT2 bits, VCP - SN_LCD->CCTRL1 = (0x44020000|mskLCD_1C_VCP_3P3V); - - __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins - __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins - //<-------------------- TODO: User modify on demand END --------------------> - - SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed - __LCD_ENABLE; //Enable LCD -} -#endif -#if LCD_TYPE == LCD_4C_TYPE -/*********************************************************************************** -* Function : LCD_4CtypeInit -* Description : Initialization of 4C-type LCD driver -* Input : None -* Output : None -* Return : None -* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT -* to take care of the circuit. -***********************************************************************************/ -void LCD_4CtypeInit(void) -{ - __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD - - //<-------------------- TODO: User modify on demand BEGIN --------------------> - //Setup LCD Driving ability, Clock rate, Duty, Bias, Type - SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY| - mskLCD_ONE_THIRD_BIAS|mskLCD_4C_TYPE); - - LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source - - //Setup IT1 bits, IT2 bits, VCP - SN_LCD->CCTRL1 = (0x44020000|mskLCD_4C_VCP_3P0V); - - __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins - __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins - //<-------------------- TODO: User modify on demand END --------------------> - - SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed - __LCD_ENABLE; //Enable LCD -} -#endif - -/*********************************************************************************** -* Function : LCD_SelectClockSource -* Description : Select LCD clcok source -* Input : LCD clock source - LCD_CLOCK_ILRC or LCD_CLOCK_ELS -* Output : None -* Return : None -* Note : None -***********************************************************************************/ -void LCD_SelectClockSource(uint32_t src) -{ - if (src == LCD_CLOCK_ELS) - SYS0_EnableELSXtal(); - - SN_LCD->CTRL_b.LCDCLK = src; -} - - -/*********************************************************************************** -* Function : LCD_FrameInterruptEnable -* Description : LCD Frame interrupt enable function -* Input : CEN - Enable/Disable counter (ENABLE or DISABLE) -* FCT - Frame counter threshold value -* IE - LCD interrupt Enable/Disable (ENABLE or DISABLE) -* Output : None -* Return : None -* Note : 0 < FCT < 32 -***********************************************************************************/ -void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE) -{ - if (IE == ENABLE) - { - NVIC_ClearPendingIRQ(LCD_IRQn); - NVIC_EnableIRQ(LCD_IRQn); - } - - SN_LCD->FCC = (CEN | (FCT<<1) | (IE<<7)); -} - - -/***************************************************************************** -* Function : LCD_IRQHandler -* Description : ISR of LCD frame interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void LCD_IRQHandler(void) -{ - SN_LCD->RIS = 0; //Write 0 to clear LCD interurpt flag -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h deleted file mode 100644 index 13004fef40..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h +++ /dev/null @@ -1,140 +0,0 @@ -#ifndef __SN32F240_LCD_H -#define __SN32F240_LCD_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define LCD_TYPE LCD_R_TYPE //LCD_R_TYPE, LCD_1C_TYPE, or LCD_4C_TYPE - -//LCD Panel driving ability -#define LCD_DRIVEP_STRONG 0 -#define LCD_DRIVEP_MEDIUM 1 -#define LCD_DRIVEP_LOW 3 -#define mskLCD_DRIVEP_STRONG (LCD_DRIVEP_STRONG<<28) -#define mskLCD_DRIVEP_MEDIUM (LCD_DRIVEP_MEDIUM<<28) -#define mskLCD_DRIVEP_LOW (LCD_DRIVEP_LOW<<28) - -//LCD_PCLK rate -#define LCD_RATE_DIV64 0 -#define LCD_RATE_DIV128 1 -#define mskLCD_RATE_DIV64 (LCD_RATE_DIV64<<11) -#define mskLCD_RATE_DIV128 (LCD_RATE_DIV128<<11) - -//LCD Clock source -#define LCD_CLOCK_ILRC 0 -#define LCD_CLOCK_ELS 1 -#define mskLCD_CLOCK_ILRC (LCD_CLOCK_ILRC<<10) -#define mskLCD_CLOCK_ELS (LCD_CLOCK_ELS<<10) - -//LCD Duty -#define LCD_HALF_DUTY 1 // 1/2 duty -#define LCD_ONE_THIRD_DUTY 2 // 1/3 duty -#define LCD_ONE_FOURTH_DUTY 3 // 1/4 duty -#define mskLCD_HALF_DUTY (LCD_HALF_DUTY<<8) -#define mskLCD_ONE_THIRD_DUTY (LCD_ONE_THIRD_DUTY<<8) -#define mskLCD_ONE_FOURTH_DUTY (LCD_ONE_FOURTH_DUTY<<8) - -//LCD Bias -#define LCD_ONE_THIRD_BIAS 0 // 1/3 bias -#define LCD_HALF_BIAS 1 // 1/2 bias -#define mskLCD_ONE_THIRD_BIAS (LCD_ONE_THIRD_BIAS<<4) -#define mskLCD_HALF_BIAS (LCD_HALF_BIAS<<4) - -//LCD Type -#define LCD_R_TYPE 0 -#define LCD_4C_TYPE 1 -#define LCD_1C_TYPE 2 -#define mskLCD_R_TYPE (LCD_R_TYPE<<2) -#define mskLCD_4C_TYPE (LCD_4C_TYPE<<2) -#define mskLCD_1C_TYPE (LCD_1C_TYPE<<2) - -//LCD R-type resistance -#define LCD_REF_400K 0 -#define LCD_REF_200K 1 -#define LCD_REF_100K 2 -#define LCD_REF_35K 3 -#define mskLCD_REF_400K (LCD_REF_400K<<1) -#define mskLCD_REF_200K (LCD_REF_200K<<1) -#define mskLCD_REF_100K (LCD_REF_100K<<1) -#define mskLCD_REF_35K (LCD_REF_35K<<1) - -//LCD 1C-type VCP -#define mskLCD_1C_VCP_2P7V 0 -#define mskLCD_1C_VCP_2P8V 1 -#define mskLCD_1C_VCP_2P9V 2 -#define mskLCD_1C_VCP_3P0V 3 -#define mskLCD_1C_VCP_3P1V 4 -#define mskLCD_1C_VCP_3P2V 5 -#define mskLCD_1C_VCP_3P3V 6 -#define mskLCD_1C_VCP_3P4V 7 - -//LCD 4C-type VCP -#define mskLCD_4C_VCP_2P7V 0 -#define mskLCD_4C_VCP_2P8V 1 -#define mskLCD_4C_VCP_2P9V 2 -#define mskLCD_4C_VCP_3P0V 3 -#define mskLCD_4C_VCP_3P06V 4 -#define mskLCD_4C_VCP_3P14V 5 -#define mskLCD_4C_VCP_3P2V 6 -#define mskLCD_4C_VCP_3P3V 7 -#define mskLCD_4C_VCP_3P4V 8 -#define mskLCD_4C_VCP_3P6V 9 -#define mskLCD_4C_VCP_3P8V 10 -#define mskLCD_4C_VCP_4P0V 11 -#define mskLCD_4C_VCP_4P2V 12 -#define mskLCD_4C_VCP_4P4V 13 -#define mskLCD_4C_VCP_4P7V 14 -#define mskLCD_4C_VCP_5P0V 15 - -//LCD Frame Interrupt Enable/Disable -#define LCD_FRAME_IE_ENABLE 1 -#define LCD_FRAME_IE_DISABLE 0 -#define mskLCD_FRAME_IE_ENABLE (LCD_FRAME_IE_ENABLE<<7) -#define mskLCD_FRAME_IE_DISABLE (LCD_FRAME_IE_DISABLE<<7) - -//LCD Frame Counter Enable/Disable -#define LCD_FRAME_COUNTER_ENABLE 1 -#define LCD_FRAME_COUNTER_DISABLE 0 -#define mskLCD_FRAME_COUNTER_ENABLE LCD_FRAME_COUNTER_ENABLE -#define mskLCD_FRAME_COUNTER_DISABLE LCD_FRAME_COUNTER_DISABLE - -//LCD Frame Counter Threshold -#define LCD_FRAME_COUNTER_THRESHOLD 31 //0 < LCD_FRAME_COUNTER_THRESHOLD < 32 - - -/*_____ M A C R O S ________________________________________________________*/ - -//LCD HCLK Enable/Disable -#define __LCD_ENABLE_LCDHCLK SN_SYS1->AHBCLKEN |= (1<<2) -#define __LCD_DISABLE_LCDHCLK SN_SYS1->AHBCLKEN &= ~(1<<2) - -//LCD Driver Enable/Disable -#define __LCD_ENABLE SN_LCD->CTRL |= 0x1 -#define __LCD_DISENABLE SN_LCD->CTRL &= ~0x1 - -//LCD SEGMENT Group 2 Enable/Disable -#define __LCD_SEGMENT_GROUP2_ENABLE SN_LCD->CTRL_b.SEGSEL2 = ENABLE -#define __LCD_SEGMENT_GROUP2_DISABLE SN_LCD->CTRL_b.SEGSEL2 = DISABLE - -//LCD SEGMENT Group 1 Enable/Disable -#define __LCD_SEGMENT_GROUP1_ENABLE SN_LCD->CTRL_b.SEGSEL1 = ENABLE -#define __LCD_SEGMENT_GROUP1_DISABLE SN_LCD->CTRL_b.SEGSEL1 = DISABLE - -//LCD Blank mode Enable/Disable -#define __LCD_DISPLAY_BLANK_ENABLE SN_LCD->CTRL1_b.LCDBNK = ENABLE -#define __LCD_DISPLAY_BLANK_DISABLE SN_LCD->CTRL1_b.LCDBNK = DISABLE - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - -void LCD_RtypeInit(void); -void LCD_1CtypeInit(void); -void LCD_4CtypeInit(void); -void LCD_SelectClockSource(uint32_t src); -void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE); - - -#endif /*__SN32F760_PMU_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c deleted file mode 100644 index ad0c2dc121..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c +++ /dev/null @@ -1,153 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: RTC related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "RTC.h" -#include "..\..\System\SYS_con_drive.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - -/*_____ D E F I N I T I O N S ______________________________________________*/ - -/*_____ M A C R O S ________________________________________________________*/ - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : RTC_IRQHandler -* Description : None -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void RTC_IRQHandler(void) -{ - if(SN_RTC->RIS & mskRTC_SECIF) - { - SN_GPIO0->DATA_b.DATA0 = ~SN_GPIO0->DATA_b.DATA0; - - SN_RTC->IC = mskRTC_SECIC; //Clear Second interrupt status - } - - if(SN_RTC->RIS & mskRTC_ALMIF) - { - - SN_GPIO0->DATA_b.DATA1 = ~SN_GPIO0->DATA_b.DATA1; - - SN_RTC->IC = mskRTC_ALMIC; //Clear Alarm interrupt status - } - - if(SN_RTC->RIS & mskRTC_OVFIF) - { - SN_GPIO0->DATA_b.DATA2 = ~SN_GPIO0->DATA_b.DATA2; - - SN_RTC->IC = mskRTC_OVFIC; //Clear Overflow interrupt status - } -} - - -/***************************************************************************** -* Function : RTC_Initial -* Description : RTC initial set -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void RTC_Init(void) -{ - __RTC_ENABLE_RTCHCLK; //Enable HCLK for RTC - - #if RTC_MODE == SECOND //Second will occur every 1 second - RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select - SN_RTC->IE = mskRTC_SECIE_ENABLE; //Enable Second Interrupt - __RTC_SECCNTV(32767); //Second counter reload value - - #endif - - #if RTC_MODE == ALARM //Alarm will occur after 10 seconds - RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select - SN_RTC->IE = mskRTC_ALMIE_ENABLE; //Enable Alarm Interrupt - __RTC_SECCNTV(32767); //Second counter reload value - __RTC_ALMCNTV(9); //Alarm counter reload value - #endif - - #if RTC_MODE == OVERFLOW //Overflow will occur in 54975.58139 seconds(15.271 hours) - RTC_SelectClockSource(RTC_CLKSEL_EHS); //Clock Source select - SN_RTC->IE = - (mskRTC_OVFIE_ENABLE | mskRTC_ALMIE_ENABLE); //Enable Overflow Interrupt - __RTC_SECCNTV(1); //Second counter reload value & Second will occur in 12.8u second - __RTC_ALMCNTV(75000000); //Alarm counter reload value & Alarm will occur in 960 seconds(16 minutes) - #endif - - //Enable RTC NVIC interrupt - RTC_NvicEnable(); - - __RTC_ENABLE; //Enable RTC -} -/*********************************************************************************** -* Function : RTC_SelectClockSource -* Description : Select RTC clcok source -* Input : RTC clock source - - RTC_CLKSEL_ILRC or RTC_CLKSEL_ELS or RTC_CLKSEL_EHS -* Output : None -* Return : None -* Note : None -***********************************************************************************/ -void RTC_SelectClockSource(uint32_t src) -{ - if (src == RTC_CLKSEL_ELS) - SYS0_EnableELSXtal(); - else if (src == RTC_CLKSEL_EHS) - SYS0_EnableEHSXtal(SYS0_EHS_FREQ_DRIVE_HIGH); - - SN_RTC->CLKS = src; //clock source select -} -/***************************************************************************** -* Function : RTC_NvicEnable -* Description : Enable RTC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void RTC_NvicEnable(void) -{ - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_EnableIRQ(RTC_IRQn); - NVIC_SetPriority(RTC_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : RTC_NvicDisable -* Description : Disable RTC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void RTC_NvicDisable(void) -{ - NVIC_DisableIRQ(RTC_IRQn); -} - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h deleted file mode 100644 index 05a9642e12..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __SN32F240_RTC_H -#define __SN32F240_RTC_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define SECOND 0 -#define ALARM 1 -#define OVERFLOW 2 -#define RTC_MODE SECOND //SECOND, ALARM, OVERFLOW - -//RTC enable -#define mskRTC_RTCEN_DISABLE 0 -#define mskRTC_RTCEN_ENABLE 1 - -//RTC Clock source -#define RTC_CLKSEL_ILRC 0 -#define RTC_CLKSEL_ELS 1 -#define RTC_CLKSEL_EHS 3 - -//RTC Interrupt Enable/Disable -#define RTC_IE_ENABLE 1 -#define RTC_IE_DISABLE 0 - -#define mskRTC_SECIE_ENABLE RTC_IE_ENABLE -#define mskRTC_SECIE_DISABLE RTC_IE_DISABLE - -#define mskRTC_ALMIE_ENABLE (RTC_IE_ENABLE<<1) -#define mskRTC_ALMIE_DISABLE (RTC_IE_DISABLE<<1) - -#define mskRTC_OVFIE_ENABLE (RTC_IE_ENABLE<<2) -#define mskRTC_OVFIE_DISABLE (RTC_IE_DISABLE<<2) - -#define mskRTC_SECIF (0x1<<0) //Interrupt flag for Second -#define mskRTC_ALMIF (0x1<<1) //Interrupt flag for Alarm -#define mskRTC_OVFIF (0x1<<2) //Interrupt flag for Overflow - -#define mskRTC_SECIC mskRTC_SECIF -#define mskRTC_ALMIC mskRTC_ALMIF -#define mskRTC_OVFIC mskRTC_OVFIF - -/*_____ M A C R O S ________________________________________________________*/ -//LCD HCLK Enable/Disable -#define __RTC_ENABLE_RTCHCLK (SN_SYS1->AHBCLKEN |= (1<<23)) -#define __RTC_DISABLE_RTCHCLK (SN_SYS1->AHBCLKEN &= ~(1<<23)) - -//RTC Enable/Disable -#define __RTC_ENABLE (SN_RTC->CTRL |= mskRTC_RTCEN_ENABLE) - -#define __RTC_SECCNTV(value) (SN_RTC->SECCNTV = value) - -#define __RTC_ALMCNTV(value) (SN_RTC->ALMCNTV = value) - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void RTC_Init(void); - -void RTC_SelectClockSource(uint32_t src); - -void RTC_NvicEnable(void); - -void RTC_NvicDisable(void); - -#endif /*__SN32F240_RTC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h deleted file mode 100644 index 0a0812616f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h +++ /dev/null @@ -1,188 +0,0 @@ -#ifndef __SN32F240_SSP_H -#define __SN32F240_SSP_H - - -/*_____ I N C L U D E S ____________________________________________________*/ - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4001 C000 (SSP0) - 0x4005 8000 (SSP1) -*/ - -/* SSP n Control register 0 (0x00) */ -#define SSP_SSPEN_DIS 0 //[0:0] SSP enable bit -#define SSP_SSPEN_EN 1 -#define mskSSP_SSPEN_DIS (SSP_SSPEN_DIS<<0) -#define mskSSP_SSPEN_EN (SSP_SSPEN_EN<<0) - - //[1:1] Loop back mode disable -#define SSP_LOOPBACK_DIS 0 //Disable -#define SSP_LOOPBACK_EN 1 //Data input from data output -#define mskSSP_LOOPBACK_DIS (SSP_LOOPBACK_DIS<<1) -#define mskSSP_LOOPBACK_EN (SSP_LOOPBACK_EN<<1) - - //[2:2] Slave data output disable bit (ONLY used in slave mode) -#define SSP_SDODIS_EN 0 //Enable slave data output -#define SSP_SDODIS_DIS 1 //Disable slave data output. (MISO=0) -#define mskSSP_SDODIS_EN (SSP_SDODIS_EN<<2) -#define mskSSP_SDODIS_DIS (SSP_SDODIS_DIS<<2) - -#define SSP_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit -#define SSP_MS_SLAVE_MODE 1 -#define mskSSP_MS_MASTER_MODE (SSP_MS_MASTER_MODE<<3) -#define mskSSP_MS_SLAVE_MODE (SSP_MS_SLAVE_MODE<<3) - -#define SSP_FORMAT_SPI_MODE 0 //[4:4] Interface format -#define SSP_FORMAT_SSP_MODE 1 -#define mskSSP_FORMAT_SPI_MODE (SSP_FORMAT_SPI_MODE<<4) -#define mskSSP_FORMAT_SSP_MODE (SSP_FORMAT_SSP_MODE<<4) - - //[7:6] SSP FSM and FIFO Reset bit -#define SSP_FRESET_DO_NOTHING 0 //Do nothing -#define SSP_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO -#define mskSSP_FRESET_DO_NOTHING (SSP_FRESET_DO_NOTHING<<6) -#define mskSSP_FRESET_RESET_FIFO (SSP_FRESET_RESET_FIFO<<6) - -#define SSP_DL_3 2 //[11:8] Data Length = DL[3:0]+1 -#define SSP_DL_4 3 -#define SSP_DL_5 4 -#define SSP_DL_6 5 -#define SSP_DL_7 6 -#define SSP_DL_8 7 -#define SSP_DL_9 8 -#define SSP_DL_10 9 -#define SSP_DL_11 10 -#define SSP_DL_12 11 -#define SSP_DL_13 12 -#define SSP_DL_14 13 -#define SSP_DL_15 14 -#define SSP_DL_16 15 - -#define SSP_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level -#define SSP_TXFIFOTH_1 1 -#define SSP_TXFIFOTH_2 2 -#define SSP_TXFIFOTH_3 3 -#define SSP_TXFIFOTH_4 4 -#define SSP_TXFIFOTH_5 5 -#define SSP_TXFIFOTH_6 6 -#define SSP_TXFIFOTH_7 7 - -#define SSP_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level -#define SSP_RXFIFOTH_1 1 -#define SSP_RXFIFOTH_2 2 -#define SSP_RXFIFOTH_3 3 -#define SSP_RXFIFOTH_4 4 -#define SSP_RXFIFOTH_5 5 -#define SSP_RXFIFOTH_6 6 -#define SSP_RXFIFOTH_7 7 - - //[18:18]Auto-SEL disable bit. For SPI mode only. -#define SSP_SELDIS_EN 0 //Enable Auto-SEL flow control -#define SSP_SELDIS_DIS 1 //Disable Auto-SEL flow control -#define mskSSP_SELDIS_EN (SSP_SELDIS_EN<<18) -#define mskSSP_SELDIS_DIS (SSP_SELDIS_DIS<<18) - - -/* SSP n Control register 1 (0x04) */ - //[0:0]MSB/LSB selection bit -#define SSP_MLSB_MSB 0 //MSB transmit first -#define SSP_MLSB_LSB 1 //LSB transmit first -#define mskSSP_MLSB_MSB (SSP_MLSB_MSB<<0) -#define mskSSP_MLSB_LSB (SSP_MLSB_LSB<<0) - - //[1:1]Clock polarity selection bit -#define SSP_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level -#define SSP_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level -#define mskSSP_CPOL_SCK_IDLE_LOW (SSP_CPOL_SCK_IDLE_LOW<<1) -#define mskSSP_CPOL_SCK_IDLE_HIGH (SSP_CPOL_SCK_IDLE_HIGH<<1) - - //[2:2]Clock phase for edge sampling -#define SSP_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge -#define SSP_CPHA_RISING_EDGE 1 //Data changes at clock rising edge -#define mskSSP_CPHA_FALLING_EDGE (SSP_CPHA_FALLING_EDGE<<2) -#define mskSSP_CPHA_RISING_EDGE (SSP_CPHA_RISING_EDGE<<2) - - -/* SSP n Clock Divider register (0x08) */ - //[7:0]SSPn clock divider -#define SSP_DIV 6 //MCLK/n, n = 2, 4, 6, 8, ...,512 - - -/* SSP n Status register (0x0C) */ -#define mskSSP_TX_EMPTY (0x1<<0) //TX FIFO empty flag -#define mskSSP_TX_FULL (0x1<<1) //TX FIFO full flag -#define mskSSP_RX_EMPTY (0x1<<2) //RX FIFO empty flag -#define mskSSP_RX_FULL (0x1<<3) //RX FIFO full flag -#define mskSSP_BUSY (0x1<<4) //Busy flag -#define mskSSP_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag -#define mskSSP_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag - - -/* SSP n Interrupt Enable register (0x10) */ -#define SSP_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable -#define SSP_RXOVFIE_EN 1 -#define mskSSP_RXOVFIE_DIS (SSP_RXOVFIE_DIS<<0) -#define mskSSP_RXOVFIE_EN (SSP_RXOVFIE_EN<<0) - -#define SSP_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable -#define SSP_RXTOIE_EN 1 -#define mskSSP_RXTOIE_DIS (SSP_RXTOIE_DIS<<1) -#define mskSSP_RXTOIE_EN (SSP_RXTOIE_EN<<1) - -#define SSP_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable -#define SSP_RXFIFOTHIE_EN 1 -#define mskSSP_RXFIFOTHIE_DIS (SSP_RXFIFOTHIE_DIS<<2) -#define mskSSP_RXFIFOTHIE_EN (SSP_RXFIFOTHIE_EN <<2) - -#define SSP_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable -#define SSP_TXFIFOTHIE_EN 1 -#define mskSSP_TXFIFOTHIE_DIS (SSP_TXFIFOTHIE_DIS<<3) -#define mskSSP_TXFIFOTHIE_EN (SSP_TXFIFOTHIE_EN<<3) - - -/* SSP n Raw Interrupt Status register (0x14) */ -/* SSP n Interrupt Clear register (0x18) */ -#define mskSSP_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag -#define mskSSP_RXOVFIC mskSSP_RXOVFIF - -#define mskSSP_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag -#define mskSSP_RXTOIC mskSSP_RXTOIF - -#define mskSSP_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag -#define mskSSP_RXFIFOTHIC mskSSP_RXFIFOTHIF - -#define mskSSP_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag -#define mskSSP_TXFIFOTHIC mskSSP_TXFIFOTHIF - - -/* SSP n Data Fetch register (0x20) */ - //[0:0]SSP data fetch control bit -#define SSP_DF_DIS 0 //Disable -#define SSP_DF_EN 1 //Enable when SCKn frequency > 6MHz -#define mskSSP_DF_DIS (SSP_DF_DIS<<0) -#define mskSSP_SSP_DF_EN (SSP_DF_EN<<0) - - -/*_____ M A C R O S ________________________________________________________*/ -#define __SPI0_FIFO_RESET (SN_SSP0->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO) -#define __SPI1_FIFO_RESET (SN_SSP1->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO) -#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA15=0) -#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA15=1) -#define __SPI1_CLR_SEL1 (SN_GPIO2->DATA_b.DATA14=0) -#define __SPI1_SET_SEL1 (SN_GPIO2->DATA_b.DATA14=1) -//SSP Data Fetch speed (High: SCK>6MHz) -#define __SSP0_DATA_FETCH_HIGH_SPEED (SN_SSP0->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x4001C020) = 1 -#define __SSP1_DATA_FETCH_HIGH_SPEED (SN_SSP1->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x40058020) = 1 - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern void SPI0_Init(void); -extern void SPI0_Enable(void); -extern void SPI0_Disable(void); - -extern void SPI1_Init(void); -extern void SPI1_Enable(void); -extern void SPI1_Disable(void); -#endif /*__SN32F760_SSP_H*/ - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c deleted file mode 100644 index b27d760d67..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c +++ /dev/null @@ -1,124 +0,0 @@ -/******************** (C) COPYRIGHT 2014 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2014/05 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: SPI0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "SPI.h" -#include "..\..\Utility\Utility.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : SPI0_Init -* Description : Initialization of SPI0 init -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI0_Init(void) -{ - //Enable HCLK for SSP0 - SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0. - - //SSP0 PCLK - SN_SYS1->APBCP0 |= (0x00 << 20); //PCLK = HCLK/1 - //SN_SYS1->APBCP0 |= (0x01 << 20); //PCLK = HCLK/2 - //SN_SYS1->APBCP0 |= (0x02 << 20); //PCLK = HCLK/4 - //SN_SYS1->APBCP0 |= (0x03 << 20); //PCLK = HCLK/8 - //SN_SYS1->APBCP0 |= (0x04 << 20); //PCLK = HCLK/16 - - //SSP0 setting - SN_SSP0->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length - SN_SSP0->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format - SN_SSP0->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit - SN_SSP0->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode - SN_SSP0->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output - //(ONLY used in slave mode) - - SN_SSP0->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider - - //SSP0 SPI mode - SN_SSP0->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling - SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit - SSP_MLSB_MSB; //MSB/LSB selection bit - - //SSP0 SEL0 setting - SN_SSP0->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit - SN_GPIO2->MODE_b.MODE15=1; //SEL(P2.15) is outout high - __SPI0_SET_SEL0; - - //SSP0 Fifo reset - __SPI0_FIFO_RESET; - - //SSP0 interrupt enable - NVIC_ClearPendingIRQ(SSP0_IRQn); - NVIC_EnableIRQ(SSP0_IRQn); - //NVIC_SetPriority(SSP0_IRQn,0); - - //__SSP0_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz - - //SSP0 enable - SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit -} - -/***************************************************************************** -* Function : SPI0_Enable -* Description : SPI0 enable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI0_Enable(void) -{ - //Enable HCLK for SSP0 - SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0. - - SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit - __SPI0_FIFO_RESET; -} - -/***************************************************************************** -* Function : SPI0_Disable -* Description : SPI0 disable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI0_Disable(void) -{ - SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit - - //Disable HCLK for SSP0 - SN_SYS1->AHBCLKEN &=~ (0x1 << 12); //Disable clock for SSP0. -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c deleted file mode 100644 index f327399a57..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c +++ /dev/null @@ -1,123 +0,0 @@ -/******************** (C) COPYRIGHT 2014 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2014/05 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: SPI1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 1. First release -* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "SPI.h" -#include "..\..\Utility\Utility.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : SPI1_Init -* Description : Initialization of SPI1 init -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI1_Init(void) -{ - //Enable HCLK for SSP1 - SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP1. - - //SSP1 PCLK - SN_SYS1->APBCP0 |= (0x00 << 24); //PCLK = HCLK/1 - //SN_SYS1->APBCP0 |= (0x01 << 24); //PCLK = HCLK/2 - //SN_SYS1->APBCP0 |= (0x02 << 24); //PCLK = HCLK/4 - //SN_SYS1->APBCP0 |= (0x03 << 24); //PCLK = HCLK/8 - //SN_SYS1->APBCP0 |= (0x04 << 24); //PCLK = HCLK/16 - - //SSP1 setting - SN_SSP1->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length - SN_SSP1->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format - SN_SSP1->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit - SN_SSP1->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode - SN_SSP1->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output - - SN_SSP1->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider - - //SSP1 SPI mode - SN_SSP1->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling - SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit - SSP_MLSB_MSB; //MSB/LSB selection bit - - //SSP1 SEL1 Setting - SN_SSP1->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit - SN_GPIO2->MODE_b.MODE14=1; //SEL1(P2.14) is outout high - __SPI1_SET_SEL1; - - //SSP1 Fifo reset - __SPI1_FIFO_RESET; - - //SSP1 interrupt enable - NVIC_ClearPendingIRQ(SSP1_IRQn); - NVIC_EnableIRQ(SSP1_IRQn); - //NVIC_SetPriority(SSP1_IRQn,0); - - //__SSP1_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz - - //SSP1 enable - SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit -} - -/***************************************************************************** -* Function : SPI1_Enable -* Description : SPI1 enable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI1_Enable(void) -{ - //Enable HCLK for SSP1 - SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP0. - - SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit - __SPI1_FIFO_RESET; -} - -/***************************************************************************** -* Function : SPI1_Disable -* Description : SPI1 disable setting -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SPI1_Disable(void) -{ - SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit - - //Disable HCLK for SSP1 - SN_SYS1->AHBCLKEN &=~ (0x1 << 13); //Disable clock for SSP0. -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c deleted file mode 100644 index 809651e77f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c +++ /dev/null @@ -1,71 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: SysTick related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "SysTick.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : SysTick_Init -* Description : Initialization of SysTick timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SysTick_Init (void) -{ - SystemCoreClockUpdate(); - - __SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1 - - __SYSTICK_CLEAR_COUNTER_AND_FLAG; - -#if SYSTICK_IRQ == INTERRUPT_METHOD - SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt -#else - SysTick->CTRL = 0x5; //Enable SysTick timer ONLY -#endif -} - - -/***************************************************************************** -* Function : SysTick_Handler -* Description : ISR of SysTick interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void SysTick_Handler(void) -{ - __SYSTICK_CLEAR_COUNTER_AND_FLAG; -} - - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h deleted file mode 100644 index 2cc5884453..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __SN32F240_SYSTICK_H -#define __SN32F240_SYSTICK_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt - //POLLING_METHOD: Enable SysTick timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ -#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1 -#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF - - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void SysTick_Init(void); - -#endif /*__SN32F240_SYSTICK_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h deleted file mode 100644 index fce22108b4..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h +++ /dev/null @@ -1,233 +0,0 @@ -#ifndef __SN32F240_USART_H -#define __SN32F240_USART_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4001 6000 (USART0) - 0x4005 6000 (USART1) -*/ -#define USART0_CLK_EN (0x01<<16) -#define USART1_CLK_EN (0x01<<17) - -#define USART0_PLKSEL_DIV1 (0x00) -#define USART0_PLKSEL_DIV2 (0x01) -#define USART0_PLKSEL_DIV4 (0x02) -#define USART0_PLKSEL_DIV8 (0x03) -#define USART0_PLKSEL_DIV16 (0x04) - -#define USART1_PLKSEL_DIV1 (0x00<<4) -#define USART1_PLKSEL_DIV2 (0x01<<4) -#define USART1_PLKSEL_DIV4 (0x02<<4) -#define USART1_PLKSEL_DIV8 (0x03<<4) -#define USART1_PLKSEL_DIV16 (0x04<<4) -/**************Line Control Define******/ -#define USART_CHARACTER_LEN5BIT (0x00) -#define USART_CHARACTER_LEN6BIT (0x01) -#define USART_CHARACTER_LEN7BIT (0x02) -#define USART_CHARACTER_LEN8BIT (0x03) -/***********************/ -#define USART_STOPBIT_1BIT (0x0<<2) -#define USART_STOPBIT_2BIT (0x1<<2) -/***********************/ -#define USART_PARITY_BIT_DISEN (0x0<<3) -#define USART_PARITY_BIT_EN (0x1<<3) -/***********************/ -#define USART_PARITY_SELECTODD (0x00<<4) -#define USART_PARITY_SELECTEVEN (0x01<<4) -#define USART_PARITY_SELECTFORC1 (0x02<<4) -#define USART_PARITY_SELECTFORC0 (0x03<<4) -/***********************/ -#define USART_BREAK_DISEN (0x0<<6) -#define USART_BREAK_EN (0x1<<6) -/***********************/ -#define USART_DIVISOR_DISEN (0x0<<7) -#define USART_DIVISOR_EN (0x1<<7) - -#define USART_OVER_SAMPLE_16 (0x0<<8) -#define USART_OVER_SAMPLE_8 (0x1<<8) -/***Baud rate pre-scaler multilier = MULVAL+1***/ -#define USART_MULVAL_0 (0x0000<<4) -#define USART_MULVAL_1 (0x0001<<4) -#define USART_MULVAL_2 (0x0002<<4) -#define USART_MULVAL_3 (0x0003<<4) -#define USART_MULVAL_4 (0x0004<<4) -#define USART_MULVAL_5 (0x0005<<4) -#define USART_MULVAL_6 (0x0006<<4) -#define USART_MULVAL_7 (0x0007<<4) -#define USART_MULVAL_8 (0x0008<<4) -#define USART_MULVAL_9 (0x0009<<4) -#define USART_MULVAL_10 (0x000A<<4) -#define USART_MULVAL_11 (0x000B<<4) -#define USART_MULVAL_12 (0x000C<<4) -#define USART_MULVAL_13 (0x000D<<4) -#define USART_MULVAL_14 (0x000E<<4) -#define USART_MULVAL_15 (0x000F<<4) -/***Buad rate pre-scaler divisor value********/ -#define USART_DIVADDVAL_0 (0x000) -#define USART_DIVADDVAL_1 (0x001) -#define USART_DIVADDVAL_2 (0x002) -#define USART_DIVADDVAL_3 (0x003) -#define USART_DIVADDVAL_4 (0x004) -#define USART_DIVADDVAL_5 (0x005) -#define USART_DIVADDVAL_6 (0x006) -#define USART_DIVADDVAL_7 (0x007) -#define USART_DIVADDVAL_8 (0x008) -#define USART_DIVADDVAL_9 (0x009) -#define USART_DIVADDVAL_10 (0x00A) -#define USART_DIVADDVAL_11 (0x00B) -#define USART_DIVADDVAL_12 (0x00C) -#define USART_DIVADDVAL_13 (0x00D) -#define USART_DIVADDVAL_14 (0x00E) -#define USART_DIVADDVAL_15 (0x00F) -/***USART divisor latch MSB reg[7:0]. determines the baud rate***/ - - -/***USART divisor latch LSB reg[7:0]. determines the baud rate***/ - - -#define USART_FIFO_ENABLE (0x01) -#define USART_RXFIFO_RESET (0x01<<1) -#define USART_TXFIFO_RESET (0x01<<2) - -#define USART_RXTRIGGER_LEVEL1 (0x00<<6) -#define USART_RXTRIGGER_LEVEL4 (0x01<<6) -#define USART_RXTRIGGER_LEVEL8 (0x02<<6) -#define USART_RXTRIGGER_LEVEL14 (0x03<<6) - -/***USART Interrupt Enable register***/ -#define USART_TXERRIE_EN (0x01<<10) //Tx error flag INT -#define USART_ABTOIE_EN (0x01<<9) //auto-buad time out INT -#define USART_ABEOIE_EN (0x01<<8) //End of auto-buad INT -#define USART_TEMTIE_EN (0x01<<4) //Transmitter empty flag -#define USART_MSIE_EN (0x01<<3) //Modem status INT -#define USART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT -#define USART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT -#define USART_RDAIE_EN (0x01) //character receive(RDA) time-out INT - -/*** USARTn_CTRL************/ -#define USART_EN (0x01) -#define USART_MODE_UART (0x00<<1) -#define USART_MODE_MODEN (0x01<<1) -#define USART_MODE_SMARTCARD (0x03<<1) -#define USART_MODE_SYNCH (0x04<<1) -#define USART_MODE_RS485 (0x05<<1) -#define USART_RX_EN (0x01<<6) -#define USART_TX_EN (0x01<<7) -#define USART_CTRL_EN 1 -#define USART_CTRL_DIS 0 -#define USART_FIFOCTRL_RESET 1 - -/*** USARTn_ABCCTRL************/ -#define USART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running) -#define USART_ABCCTRL_MODE0 (0x00<<1) -#define USART_ABCCTRL_MODE1 (0x01<<1) -#define USART_ABCCTRL_RESTART (0x01<<2) -#define USART_ABEO_EN (0x01<<8) -#define USART_ABTO_EN (0x01<<9) - -/*** USARTn_MC(modem contro)************/ -#define USART_MC_RTSCTRL (0x01<<1) //Source for modem output pin RTS -#define USART_MCCTS_EN (0x01<<6) //Auto-CTS 1:enable 0:disable -#define USART_MCRTS_EN (0x01<<7) //Auto-RTS 1:enable 0:disable - -/*** USARTn_RS485(modem contro)************/ -#define USART_NMM_EN (0x01) //Normal Multidrop Mode(NMM) 1:enable 0:disable -#define USART_485RX_EN (0x01<<1) //RS-485 Receiver bit 1:enalbe 0:disable -#define USART_AAD_EN (0x01<<2) //Auto address detect(AAD) bit 1:enable 0:disable -#define USART_ADC_EN (0x01<<4) //Auto Direction control bit 1:enable 0:disable -#define USART_OINV_SEL1 (0x01<<5) -#define USART_OINV_SEL0 (0x00<<5) -#define RS485_ADDRESS 40 -#define RS485_DELAY_TIME 40 - -/*** USARTn_Synchronous Mode(modem contro)************/ -#define USART_SCLK_LOW (0x0<<1) //SCLK idle low -#define USART_SCLK_HIGH (0x1<<1) //SCLK idle high -#define USART_POLAR_RISING (0x0<<2) //sample on Rising edge -#define USART_POLAR_FALLING (0x1<<2) //sample on Falling edge - -/*** Line status register************/ -#define USART_LS_RDR (0x01) //receiver data ready flag -#define USART_LS_OE (0x01<<1) //overrun error flag -#define USART_LS_PE (0x01<<2) //parity error flag -#define USART_LS_FE (0x01<<3) //framing error flag -#define USART_LS_BI (0x01<<4) //break interrupt flag -#define USART_LS_THRE (0x01<<5) //transmitter holding register empty flag -#define USART_LS_TEMT (0x01<<6) //transmitter empty flag -#define USART_LS_RXFE (0x01<<7) //error in RX FIFO flag -#define USART_LS_THERR (0x01<<8) //TX error flag -#define mskUSART_LS_RDR (0x01) -#define mskUSART_LS_OE (0x01<<1) -#define mskUSART_LS_PE (0x01<<2) -#define mskUSART_LS_FE (0x01<<3) -#define mskUSART_LS_BI (0x01<<4) -#define mskUSART_LS_THRE (0x01<<5) -#define mskUSART_LS_TEMT (0x01<<6) -#define mskUSART_LS_RXFE (0x01<<7) -#define mskUSART_LS_TXERR (0x01<<8) - -/*** Line status register************/ -#define USART_MS_DCTS (0x01) -#define USART_MS_CTS (0x01<<4) -#define mskUSART_MS_DCTS (0x01) -#define mskUSART_MS_CTS (0x01<<4) - -/*** Interrupt Identification register************/ -#define USART_RLS 3 -#define USART_RDA 2 -#define USART_CTI 6 -#define USART_THRE 1 -#define USART_MODEM 0 -#define USART_TEMT 7 -#define USART_II_STATUS 0 //the INTstatus can be determined by USARTn_II[3:1] -#define USART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag -#define USART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag -#define USART_II_TXERRIF (0x01<<10) //TXERR interrupt flag -#define mskUSART_INTID_STATUS 7 //interrupt corresponding to the USARTn RX FIFO -#define mskUSART_II_STATUS (0x01) -#define mskUSART_II_ABEOIF (0x01<<8) -#define mskUSART_II_ABTOIF (0x01<<9) -#define mskUSART_II_TXERRIF (0x01<<10) - - -/*_____ M A C R O S ________________________________________________________*/ -#define __USART0_RXFIFO_RESET (SN_USART0->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET) -#define __USART0_TXFIFO_RESET (SN_USART0->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET) -#define __USART1_RXFIFO_RESET (SN_USART1->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET) -#define __USART1_TXFIFO_RESET (SN_USART1->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET) - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern uint32_t GulNum; -extern uint8_t bUSART0_RecvFIFO[16]; -extern uint32_t GulNum1; -extern uint8_t bUSART1_RecvFIFO[16]; -extern volatile uint8_t bUSART0_RecvNew; -extern volatile uint8_t bUSART1_RecvNew; - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern void USART0_Init(void); -extern void USART0_SendByte(void); -extern void USART0_Enable(void); -extern void USART0_Disable(void); -extern void USART0_InterruptEnable(void); -extern void USART0_AutoBaudrateInit(void); - -extern void USART1_Init(void); -extern void USART1_SendByte(void); -extern void USART1_Enable(void); -extern void USART1_Disable(void); -extern void USART1_InterruptEnable(void); -extern void USART1_AutoBaudrateInit(void); - -extern void USART0_Modem_Init(void); -extern void USART0_RS485_Init(void); -extern void USART0_SyncMode_Init(void); - - -#endif /*__SN32F240_USART_H*/ - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c deleted file mode 100644 index 27399c4cb6..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c +++ /dev/null @@ -1,374 +0,0 @@ -/******************** (C) COPYRIGHT 2015 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2015/05 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: USART0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function -* 1.2 2014/02/27 SA1 1. Fix typing errors. -* 1.22 2014/05/23 SA1 1. Fix USART0_Init for BR=115200 -* 2.0 2015/05/29 SA1 1. Fix USART0_Init for BR=115200 & 57600 @ PCLK=12MHz -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "USART.h" -#include "..\..\Utility\Utility.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint8_t bUSART0_RecvNew; -uint32_t GulNum; -uint8_t bUSART0_RecvFIFO[16]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : UART0_IRQHandler -* Description : USART0 interrupt service routine -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void USART0_IRQHandler (void) -{ - uint32_t II_Buf, LS_Buf, MS_Buf; - volatile uint32_t Null_Buf; - - II_Buf = SN_USART0->II; - while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] - { - switch ((II_Buf>>1) & mskUSART_INTID_STATUS) - { - case USART_RLS: //Receive Line Status - LS_Buf = SN_USART0->LS; - if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error - { } - if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error - { - if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error - Null_Buf = SN_USART0->RB; //Clear interrupt - if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error - Null_Buf = SN_USART0->RB; //Clear interrupt - if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt - Null_Buf = SN_USART0->RB; //Clear interrupt - } - break; - - case USART_RDA: //Receive Data Available - case USART_CTI: //Character Time-out Indicator - LS_Buf = SN_USART0->LS; - bUSART0_RecvNew = 1; - if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready - { - bUSART0_RecvFIFO[GulNum] = SN_USART0->RB; - GulNum++; - } - if(GulNum == 16) - GulNum = 0; - break; - - case USART_THRE: //THRE interrupt - LS_Buf = SN_USART0->LS; - if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty - { //SN_USART0->TH = Null_Buf; //Clear interrupt - } - break; - - case USART_TEMT: //TEMT interrupt - LS_Buf = SN_USART0->LS; - if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT) - { //SN_USART0->TH = Null_Buf; //Clear interrupt - } - break; - - case USART_MODEM: //Modem status - MS_Buf = SN_USART0->MS; - if((MS_Buf & mskUSART_MS_DCTS) == USART_MS_DCTS)//Delta CTS - { - if((MS_Buf & mskUSART_MS_CTS) == USART_MS_CTS) - { //Low to High transition - } - else - { //High to Low transition - } - } - break; - default: - break; - } //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS) - - II_Buf = SN_USART0->II; - //LS_Buf = SN_USART0->LS; - } //end while ((II_Buf&0x01) == mskUSART_II_STATUS) - - if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt - SN_USART0->ABCTRL |= USART_ABEO_EN; - else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt - SN_USART0->ABCTRL |= USART_ABTO_EN; - - if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt - { - LS_Buf = SN_USART0->LS; - if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error - SN_USART0->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset - } -} - - -/***************************************************************************** -* Function : USART0_Init -* Description : Initialization of USART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_Init (void) -{ - SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0 - - SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz - //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz - //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz - //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz - //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz - - //===Line Control=== - //setting character Word length(5/6/7/8 bit) - SN_USART0->LC = (USART_CHARACTER_LEN8BIT //8bit character length. - | USART_STOPBIT_1BIT //stop bit of 1 bit - | USART_PARITY_BIT_DISEN //parity bit is disable - | USART_PARITY_SELECTODD //parity bit is odd - | USART_BREAK_DISEN //Break Transmission control disable - | USART_DIVISOR_EN); //Divisor Latch Access enable - - //===Baud Rate Calculation=== - //USART PCLK = 12MHz, Baud rate = 115200 - SN_USART0->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); - SN_USART0->DLM = 0; - SN_USART0->DLL = 4; - /* - //USART PCLK = 12MHz, Baud rate = 57600 - SN_USART0->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); - SN_USART0->DLM = 0; - SN_USART0->DLL = 8; - */ - SN_USART0->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch - - //===Auto Baud Rate=== - //USART0_Autobaudrate_Init(); //Auto buad rate initial - - //===FIFO Control=== - SN_USART0->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs - | USART_RXFIFO_RESET //RX FIFO Reset - | USART_TXFIFO_RESET //TX FIFO Reset - | USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) - - //===Modem Control=== - //USART0_Modem_Init(); //Initialization of USART0 Modem. - - //===Smart Card Control=== - //SN_USART0->SCICTRL_b.NACKDIS = 1; //NACK response disable, T=0 only (0:NACK response is enabled, 1:NACK response is inhibited) - //SN_USART0->SCICTRL_b.PROTSEL = 1; //Protocol selection (0:T=0, 1:T=1) - //SN_USART0->SCICTRL_b.SCLKEN = 1; //SCLK out enable (0:Disable, 1:Enable) - //SN_USART0->SCICTRL_b.TXRETRY = 0; //T=0 only, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signal NACK. - //SN_USART0->SCICTRL_b.XTRAGUARD = 0; //T=0 only, this field indicates the Guard time value in terms of number of bit times - //SN_USART0->SCICTRL_b.TC = 0; //TC[7:0] (Count for SCLK clock cycle when SCLKEN=1. SCLK will toggle every (TC[7:0]+1)*USARTn_PCLK cycle) - - //===Synchronous Mode Control=== - //USART0_SyncMode_Init(); //USART0_SyncMode_Init - - //===RS485 Control=== - //USART0_RS485_Init(); //USART0_RS485_Init - - //===Scratch Pad=== - //SN_USART0->SP = 0; //A readable, writable byte - - //===Oversampling=== - //SN_USART0->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 - - //===Half-duplex=== - //SN_USART0->HDEN = 1; //Half-duplex mode enable - - //===Interrupt Enable=== - USART0_InterruptEnable(); - - //===USART Control=== - SN_USART0->CTRL =(USART_EN //Enable USART0 - | USART_MODE_UART //USART Mode = USAT - | USART_RX_EN //Enable RX - | USART_TX_EN); //Enable TX - //===NVIC=== - NVIC_EnableIRQ(USART0_IRQn); //Enable USART0 INT - -} - -/***************************************************************************** -* Function : USART0_SendByte -* Description : USART0 Send data -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_SendByte(void) -{ - uint32_t i; - for (i=0; i<8; i++) - { - SN_USART0->TH= ('a'+i); - while ((SN_USART0->LS & 0x40) == 0); - } -} - -/***************************************************************************** -* Function : USART0_AutoBaudrateInit -* Description : Initialization of USART0 Auto baud rate. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_AutoBaudrateInit(void) -{ - SN_USART0->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt - | USART_ABEO_EN //Clear Auto Baud interrupt - | USART_ABCCTRL_RESTART //Restart in case of time-out - | USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 - | USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) -} - -/***************************************************************************** -* Function : USART0_Modem_Init -* Description : Initialization of USART0 Modem. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_Modem_Init(void) -{ - SN_USART0->MC =(USART_MC_RTSCTRL //Source for modem output pin RTS - | USART_MCCTS_EN //CTS enable - | USART_MCRTS_EN); //RTS enable -} - -/***************************************************************************** -* Function : USART0_RS485_Init -* Description : Initialization of USART0 RS-485. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_RS485_Init(void) -{ - SN_USART0->RS485CTRL=(USART_NMM_EN //RS-485 Normal Multidrop Mode enable - | USART_485RX_EN //RS-485 Receiver enable, NMMEN=1 only - | USART_AAD_EN //Auto Address Detect enable - | USART_ADC_EN //Direction control enable - | USART_OINV_SEL1); //Polarity control - SN_USART0->RS485ADRMATCH = RS485_ADDRESS; //the address match value for RS-485mode - SN_USART0->RS485DLYV = RS485_DELAY_TIME; //The direction control (RTS or DTR) delay value,this time is in periods of the baud clock -} - -/***************************************************************************** -* Function : USART0_SyncMode_Init -* Description : Initialization of USART0 Synchronous Mode. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_SyncMode_Init(void) -{ - SN_USART0->SYNCCTRL=(USART_SCLK_HIGH //SCLK idle high - |USART_POLAR_FALLING); //sample on Falling edge -} - -/***************************************************************************** -* Function : USART0_Smartcard_Init -* Description : Initialization of USART0 Smart Card. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_Smartcard_Init(void) -{ -} - -/***************************************************************************** -* Function : USART0_Enable -* Description : Enable USART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_Enable(void) -{ - //Enable HCLK for USART0 - SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0 - SN_USART0->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit - __USART0_RXFIFO_RESET; - __USART0_TXFIFO_RESET; -} - -/***************************************************************************** -* Function : USART0_Disable -* Description : Disable USART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_Disable(void) -{ - SN_USART0->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable - //Disable HCLK for USART0 - SN_SYS1->AHBCLKEN &= ~(USART0_CLK_EN); //Disable clock for USART0 -} - -/***************************************************************************** -* Function : USART0_InterruptEnable -* Description : Interrupt Enable -* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable. - wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable. - wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable. - wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART0_InterruptEnable(void) -{ - SN_USART0->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt - | USART_THREIE_EN //Enable THRE interrupt - | USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt - | USART_TEMTIE_EN //Enable TEMT interrupt - | USART_ABEOIE_EN //Enable Auto Baud interrupt - | USART_ABTOIE_EN //Enable Auto Baud time-out interrupt - | USART_TXERRIE_EN);//Enable TXERR interrupt -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c deleted file mode 100644 index 428d37fd84..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c +++ /dev/null @@ -1,284 +0,0 @@ -/******************** (C) COPYRIGHT 2015 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2015/05 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: USART1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function -* 1.2 2014/02/27 SA1 1. Fix typing errors. -* 1.22 2014/05/23 SA1 1. Fix USART1_Init for BR=115200 -* 2.0 2015/05/29 SA1 1. Fix USART1_Init for BR=115200 & 57600 @ PCLK=12MHz -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "USART.h" -#include "..\..\Utility\Utility.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint8_t bUSART1_RecvNew; -uint32_t GulNum1; -uint8_t bUSART1_RecvFIFO[16]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : UART1_IRQHandler -* Description : USART1 interrupt service routine -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void USART1_IRQHandler (void) -{ - uint32_t II_Buf, LS_Buf; - volatile uint32_t Null_Buf; - - II_Buf = SN_USART1->II; - while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] - { - switch ((II_Buf>>1) & mskUSART_INTID_STATUS) - { - case USART_RLS: //Receive Line Status - LS_Buf = SN_USART1->LS; - if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error - { } - if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error - { - if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error - Null_Buf = SN_USART1->RB; //Clear interrupt - if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error - Null_Buf = SN_USART1->RB; //Clear interrupt - if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt - Null_Buf = SN_USART1->RB; //Clear interrupt - } - break; - - case USART_RDA: //Receive Data Available - case USART_CTI: //Character Time-out Indicator - LS_Buf = SN_USART1->LS; - bUSART1_RecvNew = 1; - if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready - { - bUSART1_RecvFIFO[GulNum1] = SN_USART1->RB; - GulNum1++; - } - if(GulNum1 == 16) - GulNum1 = 0; - break; - - case USART_THRE: //THRE interrupt - LS_Buf = SN_USART1->LS; - if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty - { //SN_USART1->TH = Null_Buf; //Clear interrupt - } - break; - - case USART_TEMT: //TEMT interrupt - LS_Buf = SN_USART1->LS; - if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT) - { //SN_USART1->TH = Null_Buf; //Clear interrupt - } - break; - - default: - break; - } //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS) - - II_Buf = SN_USART1->II; - } //end while ((II_Buf&0x01) == mskUSART_II_STATUS) - - if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt - SN_USART1->ABCTRL |= USART_ABEO_EN; - else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt - SN_USART1->ABCTRL |= USART_ABTO_EN; - - if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt - { - LS_Buf = SN_USART1->LS; - if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error - SN_USART1->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset - } -} - - -/***************************************************************************** -* Function : USART1_Init -* Description : Initialization of USART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_Init (void) -{ - SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0 - - SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz - //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz - //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz - //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz - //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz - - //===Line Control=== - //setting character Word length(5/6/7/8 bit) - SN_USART1->LC = (USART_CHARACTER_LEN8BIT //8bit character length. - | USART_STOPBIT_1BIT //stop bit of 1 bit - | USART_PARITY_BIT_DISEN //parity bit is disable - | USART_PARITY_SELECTODD //parity bit is odd - | USART_BREAK_DISEN //Break Transmission control disable - | USART_DIVISOR_EN); //Divisor Latch Access enable - - //===Baud Rate Calculation=== - //USART PCLK = 12MHz, Baud rate = 115200 - SN_USART1->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); - SN_USART1->DLM = 0; - SN_USART1->DLL = 4; - /* - //USART PCLK = 12MHz, Baud rate = 57600 - SN_USART1->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); - SN_USART1->DLM = 0; - SN_USART1->DLL = 8; - */ - SN_USART1->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch - - //===Auto Baud Rate=== - //USART0_Autobaudrate_Init(); //Auto buad rate initial - - //===FIFO Control=== - SN_USART1->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs - | USART_RXFIFO_RESET //RX FIFO Reset - | USART_TXFIFO_RESET //TX FIFO Reset - | USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) - - //===Scratch Pad=== - //SN_USART1->SP = 0; //A readable, writable byte - - //===Oversampling=== - //SN_USART1->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 - - //===Half-duplex=== - //SN_USART1->HDEN = 1; //Half-duplex mode enable - - //===Interrupt Enable=== - USART1_InterruptEnable(); - - //===USART Control=== - SN_USART1->CTRL =(USART_EN //Enable USART0 - | USART_MODE_UART //USART Mode = USAT - | USART_RX_EN //Enable RX - | USART_TX_EN); //Enable TX - //===NVIC=== - NVIC_EnableIRQ(USART1_IRQn); //Enable USART1 INT - -} - -/***************************************************************************** -* Function : USART1_SendByte -* Description : USART1 Send data -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_SendByte(void) -{ - uint32_t i; - for (i=0; i<8; i++) - { - SN_USART1->TH= ('a'+i); - while ((SN_USART1->LS & 0x40) == 0); - } -} - -/***************************************************************************** -* Function : USART1_AutoBaudrateInit -* Description : Initialization of USART1 Auto baud rate. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_AutoBaudrateInit(void) -{ - SN_USART1->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt - | USART_ABEO_EN //Clear Auto Baud interrupt - | USART_ABCCTRL_RESTART //Restart in case of time-out - | USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 - | USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) -} - -/***************************************************************************** -* Function : USART1_Enable -* Description : Enable USART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_Enable(void) -{ - //Enable HCLK for USART1 - SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0 - SN_USART1->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit - __USART1_RXFIFO_RESET; - __USART1_TXFIFO_RESET; -} - -/***************************************************************************** -* Function : USART1_Disable -* Description : Disable USART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_Disable(void) -{ - SN_USART1->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable - //Disable HCLK for USART1 - SN_SYS1->AHBCLKEN &= ~(USART1_CLK_EN); //Disable clock for USART0 -} - -/***************************************************************************** -* Function : USART1_InterruptEnable -* Description : Interrupt Enable -* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable. - wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable. - wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable. - wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USART1_InterruptEnable(void) -{ - SN_USART1->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt - | USART_THREIE_EN //Enable THRE interrupt - | USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt - | USART_TEMTIE_EN //Enable TEMT interrupt - | USART_ABEOIE_EN //Enable Auto Baud interrupt - | USART_ABTOIE_EN //Enable Auto Baud time-out interrupt - | USART_TXERRIE_EN);//Enable TXERR interrupt -} - diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk deleted file mode 100644 index 8326191ba0..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk +++ /dev/null @@ -1,5 +0,0 @@ -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c - -PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c deleted file mode 100644 index 4587191151..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_lld.c - * @brief PLATFORM USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include -#include -#include "hal.h" -#include "usbhw.h" - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define SN32_USB_IRQ_VECTOR Vector44 -#define SN32_USB_PMA_SIZE 256 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief USB1 driver identifier. - */ -#if (PLATFORM_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static int address; -static uint8_t nakcnt[USB_MAX_ENDPOINTS + 1] = {0, 0, 0, 0, 0, 0, 0}; - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_ENDPOINT_TYPE_CONTROL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out -}; -void rgb_matrix_toggle(void); -void handleACK(USBDriver* usbp, usbep_t ep); -void handleNAK(USBDriver* usbp, usbep_t ep); -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) -#define _usb_isr_invoke_tx_complete_cb(usbp, ep) { \ - (usbp)->transmitting &= ~(1 << (ep)); \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(usbp)->epc[ep]->in_state->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} -#else -#define _usb_isr_invoke_tx_complete_cb(usbp, ep) { \ - (usbp)->transmitting &= ~(1 << (ep)); \ -} -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) { - uint32_t *pRAM = &USB_SRAM_EP0_W0; - - if (ep == 0) { - memcpy(buf, pRAM, sz); - } else { - memcpy(buf, (void *)wUSB_EPnOffset[ep - 1], sz); - } -} - -static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool intr) { - uint32_t *pRAM = &USB_SRAM_EP0_W0; - - if (ep == 0) { - memcpy(pRAM, buf, sz); - } else { - memcpy((void *)wUSB_EPnOffset[ep - 1], buf, sz); - } -} - -void rgb_matrix_disable_noeeprom(void); -/** - * @brief USB shared ISR. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void usb_lld_serve_interrupt(USBDriver *usbp) -{ - uint32_t iwIntFlag; - size_t n; - - //** Get Interrupt Status and clear immediately. - iwIntFlag = SN_USB->INSTS; - //Clear flags right away for interrupts that we dont handle, keep other untill fully handled - SN_USB->INSTSC = 0x0007C0C0; - - if(iwIntFlag == 0) - { - //@20160902 add for EMC protection - return; - } - - if (iwIntFlag & mskBUS_WAKEUP) - { /* Wakeup */ - USB_WakeupEvent(); - _usb_wakeup(usbp); - return; - } - - ///////////////////////////////////////////////// - /* Device Status Interrupt (BusReset, Suspend) */ - ///////////////////////////////////////////////// - if (iwIntFlag & (mskBUS_RESET | mskBUS_SUSPEND | mskBUS_RESUME)) - { - if (iwIntFlag & mskBUS_RESET) - { - /* BusReset */ - USB_ResetEvent(); - _usb_reset(usbp); - } - else if (iwIntFlag & mskBUS_SUSPEND) - { - /* Suspend */ - __USB_CLRINSTS(mskBUS_SUSPEND); - _usb_suspend(usbp); - } - else if(iwIntFlag & mskBUS_RESUME) - { - /* Resume */ - __USB_CLRINSTS(mskBUS_RESUME); - _usb_wakeup(usbp); - } - } - ///////////////////////////////////////////////// - /* Device Status Interrupt (SETUP, IN, OUT) */ - ///////////////////////////////////////////////// - else if (iwIntFlag & (mskEP0_SETUP|mskEP0_IN|mskEP0_OUT|mskEP0_IN_STALL|mskEP0_OUT_STALL)) - { - const USBEndpointConfig *epcp = usbp->epc[0]; - - if (iwIntFlag & mskEP0_SETUP) - { - /* SETUP */ - //** keep EP0 NAK - //USB_EPnNak(USB_EP0); //useless - - //not sure we need it here... - //TODO: clean it up when packets are properly handled - epcp->in_state->txcnt = 0; - epcp->in_state->txsize = 0; - epcp->in_state->txlast = 0; - epcp->out_state->rxcnt = 0; - epcp->out_state->rxsize = 0; - epcp->out_state->rxpkts = 0; - - _usb_isr_invoke_setup_cb(usbp, 0); - __USB_CLRINSTS((mskEP0_SETUP|mskEP0_PRESETUP|mskEP0_OUT_STALL|mskEP0_IN_STALL)); - } - else if (iwIntFlag & mskEP0_IN) - { - USBInEndpointState *isp = epcp->in_state; - - /* IN */ - - // The address - if (address) { - SN_USB->ADDR = address; - address = 0; - USB_EPnStall(USB_EP0); - } - -// USB_EPnAck(USB_EP0,0); - - isp->txcnt += isp->txlast; - n = isp->txsize - isp->txcnt; - if (n > 0) { - /* Transfer not completed, there are more packets to send.*/ - if (n > epcp->in_maxsize) - n = epcp->in_maxsize; - - /* Writes the packet from the defined buffer.*/ - isp->txbuf += isp->txlast; - isp->txlast = n; - - sn32_usb_write_fifo(0, isp->txbuf, n, true); - - USB_EPnAck(USB_EP0, n); - } - else - { - //USB_EPnNak(USB_EP0); //not needed - - _usb_isr_invoke_in_cb(usbp, 0); - } - __USB_CLRINSTS(mskEP0_IN); - - } - else if (iwIntFlag & mskEP0_OUT) - { - USBOutEndpointState *osp = epcp->out_state; - /* OUT */ - - n = SN_USB->EP0CTL & mskEPn_CNT; - if (n > epcp->out_maxsize) - n = epcp->out_maxsize; - - //Just being paranoid here. keep here while debugging EP handling issue - //TODO: clean it up when packets are properly handled - if (epcp->out_state->rxsize >= n) { - //we are ok to copy n bytes to buf - sn32_usb_read_fifo(USB_EP0, osp->rxbuf, n, true); - epcp->out_state->rxsize -= n; - } - else if (epcp->out_state->rxsize > 0) { - //we dont have enough buffer to receive n bytes - //copy only size availabe on buffer - n = epcp->out_state->rxsize; - sn32_usb_read_fifo(USB_EP0, osp->rxbuf, n, true); - epcp->out_state->rxsize -= n; - } - else { - //well buffer is 0 size. strange. do nothing. - n = 0; - } - - epcp->out_state->rxbuf += n; - epcp->out_state->rxcnt += n; - if (epcp->out_state->rxpkts > 0) { - epcp->out_state->rxpkts -= 1; - } - - if (n < epcp->out_maxsize || epcp->out_state->rxpkts == 0) - { - //done with transfer - //USB_EPnNak(USB_EP0); //useless mcu resets it anyways - _usb_isr_invoke_out_cb(usbp, 0); - } - else { - //more to receive - USB_EPnAck(USB_EP0, 0); - } - __USB_CLRINSTS(mskEP0_OUT); - - } - else if (iwIntFlag & (mskEP0_IN_STALL|mskEP0_OUT_STALL)) - { - /* EP0_IN_OUT_STALL */ - USB_EPnStall(USB_EP0); - SN_USB->INSTSC = (mskEP0_IN_STALL|mskEP0_OUT_STALL); - } - } - ///////////////////////////////////////////////// - /* Device Status Interrupt (EPnACK) */ - ///////////////////////////////////////////////// - else if (iwIntFlag & (mskEP6_ACK|mskEP5_ACK|mskEP4_ACK|mskEP3_ACK|mskEP2_ACK|mskEP1_ACK)) - { - // Determine the interrupting endpoint, direction, and clear the interrupt flag - if(iwIntFlag & mskEP1_ACK) - { - handleACK(usbp, USB_EP1); - __USB_CLRINSTS(mskEP1_ACK); - } - if(iwIntFlag & mskEP2_ACK) - { - handleACK(usbp, USB_EP2); - __USB_CLRINSTS(mskEP2_ACK); - } - if(iwIntFlag & mskEP3_ACK) - { - handleACK(usbp, USB_EP3); - __USB_CLRINSTS(mskEP3_ACK); - } - if(iwIntFlag & mskEP4_ACK) - { - handleACK(usbp, USB_EP4); - __USB_CLRINSTS(mskEP4_ACK); - } - if(iwIntFlag & mskEP5_ACK) - { - handleACK(usbp, USB_EP5); - __USB_CLRINSTS(mskEP5_ACK); - } - if(iwIntFlag & mskEP6_ACK) - { - handleACK(usbp, USB_EP6); - __USB_CLRINSTS(mskEP6_ACK); - } - } - else if (iwIntFlag & (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK)) - { - // Determine the interrupting endpoint, direction, and clear the interrupt flag - if (iwIntFlag & mskEP1_NAK) - { - handleNAK(usbp, USB_EP1); - __USB_CLRINSTS(mskEP1_NAK); - } - if (iwIntFlag & mskEP2_NAK) - { - handleNAK(usbp, USB_EP2); - __USB_CLRINSTS(mskEP2_NAK); - } - if (iwIntFlag & mskEP3_NAK) - { - handleNAK(usbp, USB_EP3); - __USB_CLRINSTS(mskEP3_NAK); - } - if (iwIntFlag & mskEP4_NAK) - { - handleNAK(usbp, USB_EP4); - __USB_CLRINSTS(mskEP4_NAK); - } - if (iwIntFlag & mskEP5_NAK) - { - handleNAK(usbp, USB_EP5); - __USB_CLRINSTS(mskEP5_NAK); - } - if (iwIntFlag & mskEP6_NAK) - { - handleNAK(usbp, USB_EP6); - __USB_CLRINSTS(mskEP6_NAK); - } - } - - ///////////////////////////////////////////////// - /* Device Status Interrupt (SOF) */ - ///////////////////////////////////////////////// - if ((iwIntFlag & mskUSB_SOF) && (SN_USB->INTEN & mskUSB_SOF_IE)) - { - /* SOF */ - _usb_isr_invoke_sof_cb(usbp); - __USB_CLRINSTS(mskUSB_SOF); - } -} - -void handleACK(USBDriver* usbp, usbep_t ep) { - uint8_t out = 0; - uint8_t cnt = 0; - size_t n; - - if(ep == USB_EP1) - { - out = ( SN_USB->CFG & mskEP1_DIR ) == mskEP1_DIR; - cnt = SN_USB->EP1CTL & mskEPn_CNT; - } - else if(ep == USB_EP2) - { - out = ( SN_USB->CFG & mskEP2_DIR ) == mskEP2_DIR; - cnt = SN_USB->EP2CTL & mskEPn_CNT; - } - else if(ep == USB_EP3) - { - out = ( SN_USB->CFG & mskEP3_DIR ) == mskEP3_DIR; - cnt = SN_USB->EP3CTL & mskEPn_CNT; - } - else if(ep == USB_EP4) - { - out = ( SN_USB->CFG & mskEP4_DIR ) == mskEP4_DIR; - cnt = SN_USB->EP4CTL & mskEPn_CNT; - } - else if(ep == USB_EP5) - { - out = ( SN_USB->CFG & mskEP5_DIR ) == mskEP5_DIR; - cnt = SN_USB->EP5CTL & mskEPn_CNT; - } - else if(ep == USB_EP6) - { - out = ( SN_USB->CFG & mskEP6_DIR ) == mskEP6_DIR; - cnt = SN_USB->EP6CTL & mskEPn_CNT; - } - else { - return; - } - nakcnt[ep] = 0; - - // Get the endpoint config and state - const USBEndpointConfig *epcp = usbp->epc[ep]; - USBInEndpointState *isp = epcp->in_state; - USBOutEndpointState *osp = epcp->out_state; - - // Process based on endpoint direction - if(out) - { - // Read size of received data - n = cnt; - - if (n > epcp->out_maxsize) - n = epcp->out_maxsize; - - //state is NAK already - //Just being paranoid here. keep here while debugging EP handling issue - //TODO: clean it up when packets are properly handled - if (epcp->out_state->rxsize >= n) { - //we are ok to copy n bytes to buf - sn32_usb_read_fifo(ep, osp->rxbuf, n, true); - epcp->out_state->rxsize -= n; - } - else if (epcp->out_state->rxsize > 0) { - //we dont have enough buffer to receive n bytes - //copy only size availabe on buffer - n = epcp->out_state->rxsize; - sn32_usb_read_fifo(ep, osp->rxbuf, n, true); - epcp->out_state->rxsize -= n; - } - else { - //well buffer is 0 size. strange. do nothing. - n = 0; - } - osp->rxbuf += n; - - epcp->out_state->rxcnt += n; - if (epcp->out_state->rxpkts > 0) { - epcp->out_state->rxpkts -= 1; - } - - if (n < epcp->out_maxsize || epcp->out_state->rxpkts == 0) - { - _usb_isr_invoke_out_cb(usbp, ep); - } - else - { - //not done. keep on receiving - USB_EPnAck(ep, 0); - } - } - else - { - // Process transmit queue - isp->txcnt += isp->txlast; - n = isp->txsize - isp->txcnt; - - if (n > 0) - { - /* Transfer not completed, there are more packets to send.*/ - if (n > epcp->in_maxsize) - { - n = epcp->in_maxsize; - } - - /* Writes the packet from the defined buffer.*/ - isp->txbuf += isp->txlast; - isp->txlast = n; - - sn32_usb_write_fifo(ep, isp->txbuf, n, true); - - USB_EPnAck(ep, n); - } - else - { - //USB_EPnNak(ep); //not needed here it is autoreset to NAK already - - _usb_isr_invoke_in_cb(usbp, ep); - } - } -} - -void handleNAK(USBDriver *usbp, usbep_t ep) { - uint8_t out = 0; - //handle it properly - if (ep == USB_EP1) { - out = ( SN_USB->CFG & mskEP1_DIR ) == mskEP1_DIR; - } - else if (ep == USB_EP2) { - out = ( SN_USB->CFG & mskEP2_DIR ) == mskEP2_DIR; - } - else if (ep == USB_EP3) { - out = ( SN_USB->CFG & mskEP3_DIR ) == mskEP3_DIR; - } - else if (ep == USB_EP4) { - out = ( SN_USB->CFG & mskEP4_DIR ) == mskEP4_DIR; - } - else if (ep == USB_EP5) { - out = ( SN_USB->CFG & mskEP5_DIR ) == mskEP5_DIR; - } - else if (ep == USB_EP6) { - out = ( SN_USB->CFG & mskEP6_DIR ) == mskEP6_DIR; - } - else { - return; - } - - - if(out) - { - // By acking next OUT token from host we are allowing reception - // of the data from host - USB_EPnAck(ep, 0); - } - else - { - // This is not a retransmission, retransmission is transparent and happens on phy layer - // NAK happens when host polls IN EP and device has nothing to send - // It has been observed that sometimes USB phy doesn't generate ACK (unknown why) - // (count ACK interrupts didn't match count of usb_lld_start_in calls per EP) - // However while USB transmitting and qmk thread wants to send another packet qmk goes to - // infinite sleep, expecting that successfull USB transmission will wake it up - // If USB transmission never completes (no ACK) then qmk never wakes up and keyboard locks up - // To prevent this every NAK (1ms or 8ms depending on host poll interval) was calling - // callbacks and wake up function to wake up qmk thread, however packet was not delivered to host - // (for unknown reason) and thus we have seen: - // 1) stuck keypresses when usb packets to press key delivered but key release packet lost - // 2) untyped key when usb packet to press key was lost but key release packet delivered - // Because callback was called every NAK some qmk features didnt work such as CONSOLE - // since callback might release buffers and endup in deadlock via disabled interrupts - // callback for keyboard is empty thus its repated calling is harmless - #if defined(SN32_USB_ORIGINAL_NAK_HANDLING) - _usb_isr_invoke_in_cb(usbp, ep); - #else - //To fake missing ACK we can send 0 sized packet - //however (again for unknown reason) packets now being delivered to host as well! - //- value 2 has been selected to allow at least 2 NAK delivery (2ms or 16ms depending on - //host polling interval) between moment qmk called start_in and moment USB phy actually - //started transmission - //- value 10 was selected arbitrary. - //- values 3-10 we are delivering 0 sized packet trying to get at least one ack - if (nakcnt[ep] > 0) { - //qmk called start_in - if (nakcnt[ep] > 10) { - //11-.... - //consider packet undeliverable but ack it to the qmk - nakcnt[ep] = 0; - _usb_isr_invoke_in_cb(usbp, ep); - } - else if (nakcnt[ep] > 2) { - //3-10 - nakcnt[ep]++; - USB_EPnAck(ep, 0); - } - else { - //1-2 - //give it sometime to deliver the packet - nakcnt[ep]++; - } - } - #endif - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers and threads. */ -/*===========================================================================*/ - -/** - * @brief SN32 USB Interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(SN32_USB_IRQ_VECTOR) { - - OSAL_IRQ_PROLOGUE(); - usb_lld_serve_interrupt(&USBD1); - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - - #if PLATFORM_USB_USE_USB1 == TRUE - /* Driver initialization.*/ - usbObjectInit(&USBD1); - #endif -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - - if (usbp->state == USB_STOP) { - /* Enables the peripheral.*/ - #if PLATFORM_USB_USE_USB1 == TRUE - if (&USBD1 == usbp) { - USB_Init(); - nvicEnableVector(USB_IRQn, 14); - } - #endif - } - /* Configures the peripheral.*/ -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - if (usbp->state == USB_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ - #if PLATFORM_USB_USE_USB1 == TRUE - if (&USBD1 == usbp) { - } - #endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - /* Post reset initialization.*/ - - /* EP0 initialization.*/ - usbp->epc[0] = &ep0config; - usb_lld_init_endpoint(usbp, 0); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - // It seems the address must be set after an endpoint interrupt, so store it for now. - // It will be written to SN_USB->ADDR in the EP0 IN interrupt - address = usbp->address; -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - const USBEndpointConfig *epcp = usbp->epc[ep]; - - /* Set the endpoint type. */ - switch (epcp->ep_mode & USB_EP_MODE_TYPE) { - case USB_EP_MODE_TYPE_ISOC: - break; - case USB_EP_MODE_TYPE_BULK: - break; - case USB_EP_MODE_TYPE_INTR: - break; - default: - break; - } - - /* IN endpoint? */ - if (epcp->in_state != NULL) { - // Set endpoint direction flag in USB configuration register - switch (ep) - { - case 1: - SN_USB->CFG &= ~mskEP1_DIR; - break; - case 2: - SN_USB->CFG &= ~mskEP2_DIR; - break; - case 3: - SN_USB->CFG &= ~mskEP3_DIR; - break; - case 4: - SN_USB->CFG &= ~mskEP4_DIR; - break; - case 5: - SN_USB->CFG &= ~mskEP5_DIR; - break; - case 6: - SN_USB->CFG &= ~mskEP6_DIR; - break; - } - } - - /* OUT endpoint? */ - if (epcp->out_state != NULL) { - // Set endpoint direction flag in USB configuration register - // Also enable ACK state - switch (ep) - { - case 1: - SN_USB->CFG |= mskEP1_DIR; - break; - case 2: - SN_USB->CFG |= mskEP2_DIR; - break; - case 3: - SN_USB->CFG |= mskEP3_DIR; - break; - case 4: - SN_USB->CFG |= mskEP4_DIR; - break; - case 5: - SN_USB->CFG |= mskEP5_DIR; - break; - case 6: - SN_USB->CFG |= mskEP6_DIR; - break; - } - } - - /* Enable endpoint. */ - switch(ep) - { - case 1: - SN_USB->EP1CTL |= mskEPn_ENDP_EN; - break; - case 2: - SN_USB->EP2CTL |= mskEPn_ENDP_EN; - break; - case 3: - SN_USB->EP3CTL |= mskEPn_ENDP_EN; - break; - case 4: - SN_USB->EP4CTL |= mskEPn_ENDP_EN; - break; - case 5: - SN_USB->EP5CTL |= mskEPn_ENDP_EN; - break; - case 6: - SN_USB->EP6CTL |= mskEPn_ENDP_EN; - break; - } -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - unsigned i; - - /* Disabling all endpoints.*/ - for (i = 1; i <= USB_MAX_ENDPOINTS; i++) { - USB_EPnDisable(i); - } -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - if (ep > USB_MAX_ENDPOINTS) - return EP_STATUS_DISABLED; - if (!USB_EPnEnabled(ep)) - return EP_STATUS_DISABLED; - if (USB_EPnStalled(ep)) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -/* - if (SN_USB->INSTS & mskEP0_OUT) { - return EP_STATUS_DISABLED; - } else if (SN_USB->INSTS & mskEP0_OUT_STALL) { - return EP_STATUS_STALLED; - } else { - return EP_STATUS_ACTIVE; - } -*/ -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - if (ep > USB_MAX_ENDPOINTS) - return EP_STATUS_DISABLED; - if (!USB_EPnEnabled(ep)) - return EP_STATUS_DISABLED; - if (USB_EPnStalled(ep)) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -/* - if (SN_USB->INSTS & mskEP0_IN) { - return EP_STATUS_DISABLED; - } else if (SN_USB->INSTS & mskEP0_IN_STALL) { - return EP_STATUS_STALLED; - } else { - return EP_STATUS_ACTIVE; - } -*/ -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ - -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - - sn32_usb_read_fifo(ep, buf, 8, false); -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - /* Transfer initialization.*/ - if (osp->rxsize == 0) /* Special case for zero sized packets.*/ - osp->rxpkts = 1; - else - osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / - usbp->epc[ep]->out_maxsize); - osp->rxcnt = 0;//haven't received anything yet - USB_EPnAck(ep, 0); -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) -{ - size_t n; - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - /* Transfer initialization.*/ - //who handles 0 packet ack on setup? - n = isp->txsize; - - if((n >= 0) || (ep == 0)) - { - if (n > (size_t)usbp->epc[ep]->in_maxsize) - n = (size_t)usbp->epc[ep]->in_maxsize; - - isp->txlast = n; - - sn32_usb_write_fifo(ep, isp->txbuf, n, false); - - nakcnt[ep] = 1; - USB_EPnAck(ep, n); - } - else - { - _usb_isr_invoke_in_cb(usbp, ep); - } - -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - USB_EPnStall(ep); - -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - USB_EPnStall(ep); - -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - if (ep > USB_MAX_ENDPOINTS) - return; - USB_EPnNak(ep); - //__USB_CLRINSTS(mskEP0_OUT); -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - if (ep > USB_MAX_ENDPOINTS) - return; - USB_EPnNak(ep); - //__USB_CLRINSTS(mskEP0_IN); -} - -#endif /* HAL_USE_USB == TRUE */ - -/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h deleted file mode 100644 index 72ea3ee44f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_lld.h - * @brief PLATFORM USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef HAL_USB_LLD_H -#define HAL_USB_LLD_H - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -#include "sn32_usb.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief The address can be changed immediately upon packet reception. - */ -#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS // FixMe: USB_LATE_SET_ADDRESS ? - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief USB driver enable switch. - * @details If set to @p TRUE the support for USB1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__) -#define PLATFORM_USB_USE_USB1 TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Size of the last transmitted packet. - */ - size_t txlast; -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Number of packets to receive. - */ - uint16_t rxpkts; -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not - * used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not - * used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This structure maintains the state of the IN endpoint. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This structure maintains the state of the OUT endpoint. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ - /* End of the mandatory fields.*/ - /** - * @brief Reserved field, not currently used. - * @note Initialize this field to 1 in order to be forward compatible. - */ - uint16_t ep_buffers; - /** - * @brief Pointer to a buffer for setup packets. - * @details Setup packets require a dedicated 8-bytes buffer, set this - * field to @p NULL for non-control endpoints. - */ - uint8_t *setup_buf; -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; - /** - * @brief State of the driver when a suspend happened. - */ - usbstate_t saved_state; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the next address in the packet memory. - */ - uint32_t pmnext; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @notapi - */ -#define usb_lld_get_frame_number(usbp) 0 - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -/** - * @brief Connects the USB device. - * - * @api - */ -#define usb_lld_connect_bus(usbp) - -/** - * @brief Disconnect the USB device. - * - * @api - */ -#define usb_lld_disconnect_bus(usbp) - -/** - * @brief Start of host wake-up procedure. - * - * @notapi - */ -#define usb_lld_wakeup_host(usbp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* Descriptor related */ -/* bmAttributes in Endpoint Descriptor */ -#define USB_ENDPOINT_TYPE_MASK 0x03 -#define USB_ENDPOINT_TYPE_CONTROL 0x00 -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 -#define USB_ENDPOINT_TYPE_BULK 0x02 -#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 -#define USB_ENDPOINT_SYNC_MASK 0x0C -#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 -#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 -#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 -#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C -#define USB_ENDPOINT_USAGE_MASK 0x30 -#define USB_ENDPOINT_USAGE_DATA 0x00 -#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 -#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 -#define USB_ENDPOINT_USAGE_RESERVED 0x30 - -/* bEndpointAddress in Endpoint Descriptor */ -#define USB_ENDPOINT_DIRECTION_MASK 0x80 - -#if (PLATFORM_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); - void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB == TRUE */ - -#endif /* HAL_USB_LLD_H */ - -/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h deleted file mode 100644 index beee10efa9..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file USBv1/sn32_usb.h - * @brief SN32 USB registers layout header. - * @note This file requires definitions from the ST STM32 header files - * sn32f124x.h - * - * @addtogroup USB - * @{ - */ - -#ifndef SN32_USB_H -#define SN32_USB_H - -// TODO: ENDPOINTS nubmer is chip dependent and needs to be organized better -/** - * @brief Number of the available endpoints. - * @details This value does not include the endpoint 0 which is always present. - */ -#define USB_MAX_ENDPOINTS 6 - -/** - * @brief USB registers block numeric address. - */ -#define SN32_USB_BASE SN_USB_BASE - -/** - * @brief USB RAM numeric address. - */ -#define SN32_USBRAM_BASE SN_USB_BASE + 0x100 - -/** - * @brief Pointer to the USB registers block. - */ -// #define SN32_USB ((sn32_usb_t *)SN32_USB_BASE) - -/** - * @brief Pointer to the USB RAM. - */ -#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE) - -#endif /* SN32_USB_H */ - -/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c deleted file mode 100644 index 3eb8f9679d..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c +++ /dev/null @@ -1,323 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbhw.c - * Purpose: USB Custom User Module - * Version: V1.01 - * Date: 2017/07 - *------------------------------------------------------------------------------*/ -#include -#include "SN32F200_Def.h" - -#include "usbhw.h" -#include "usbsystem.h" - -volatile uint32_t wUSB_EPnOffset[7]; -volatile uint32_t wUSB_EPnMaxPacketsize[7]; - -/***************************************************************************** -* Function : USB_Init -* Description : 1. setting IDLE_TIME, REPORT_PROTOCOL, S_USB_EP0setupdata.wUSB_Status -* 2. set EP1~EP6 FIFO RAM address. -* 3. save EP1~EP6 FIFO RAM point address. -* 4. save EP1~EP6 Package Size. -* 5. Enable USB function and setting EP1~EP6 Direction. -* 6. NEVER REMOVE !! USB D+/D- Dischage -* 7. Enable USB PHY and USB interrupt. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_Init (void) -{ - volatile uint32_t *pRam; - uint32_t wTmp, i; - - /* Initialize clock and Enable USB PHY. */ - USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting - SN_SYS1->AHBCLKEN |= 0x02; // Enable USBCLKEN - __USB_PHY_ENABLE; // enable ESD_EN & PHY_EN - - /* Initialize USB EP1~EP6 RAM address base on 64-bytes. */ - USB_EPnBufferOffset(1,EP1_BUFFER_OFFSET_VALUE); - USB_EPnBufferOffset(2,EP2_BUFFER_OFFSET_VALUE); - USB_EPnBufferOffset(3,EP3_BUFFER_OFFSET_VALUE); - USB_EPnBufferOffset(4,EP4_BUFFER_OFFSET_VALUE); - USB_EPnBufferOffset(5,EP5_BUFFER_OFFSET_VALUE); - USB_EPnBufferOffset(6,EP6_BUFFER_OFFSET_VALUE); - - /* Initialize EP1~EP6 RAM point address to array(wUSB_EPnOffset).*/ - pRam = &wUSB_EPnOffset[0]; - *(pRam+0) = (uint32_t)(&USB_SRAM_EP0_W0) + EP1_BUFFER_OFFSET_VALUE; - *(pRam+1) = (uint32_t)(&USB_SRAM_EP0_W0) + EP2_BUFFER_OFFSET_VALUE; - *(pRam+2) = (uint32_t)(&USB_SRAM_EP0_W0) + EP3_BUFFER_OFFSET_VALUE; - *(pRam+3) = (uint32_t)(&USB_SRAM_EP0_W0) + EP4_BUFFER_OFFSET_VALUE; - *(pRam+4) = (uint32_t)(&USB_SRAM_EP0_W0) + EP5_BUFFER_OFFSET_VALUE; - *(pRam+5) = (uint32_t)(&USB_SRAM_EP0_W0) + EP6_BUFFER_OFFSET_VALUE; - - /* Initialize EP0~EP6 package size to array(wUSB_EPnPacketsize).*/ - pRam = &wUSB_EPnMaxPacketsize[0]; - *(pRam+0) = USB_EP0_PACKET_SIZE; - *(pRam+1) = USB_EP1_PACKET_SIZE; - *(pRam+2) = USB_EP2_PACKET_SIZE; - *(pRam+3) = USB_EP3_PACKET_SIZE; - *(pRam+4) = USB_EP4_PACKET_SIZE; - *(pRam+5) = USB_EP5_PACKET_SIZE; - *(pRam+6) = USB_EP6_PACKET_SIZE; - - /* Enable the USB Interrupt */ - SN_USB->INTEN = (mskBUS_IE|mskUSB_IE|mskUSB_BUSWK_IE); - SN_USB->INTEN |= mskEP1_NAK_EN; - SN_USB->INTEN |= mskEP2_NAK_EN; - SN_USB->INTEN |= mskEP3_NAK_EN; - SN_USB->INTEN |= mskEP4_NAK_EN; - SN_USB->INTEN |= mskEP5_NAK_EN; - SN_USB->INTEN |= mskEP6_NAK_EN; - SN_USB->INTEN |= mskUSB_SOF_IE; - - NVIC_ClearPendingIRQ(USB_IRQn); - NVIC_EnableIRQ(USB_IRQn); - - /* BUS_DRVEN = 0, BUS_DP = 1, BUS_DN = 0 */ - SN_USB->SGCTL = mskBUS_J_STATE; - /* VREG33_EN = 1, PHY_EN = 1, DPPU_EN = 1, SIE_EN = 1, USBRAM_EN = 1, FLTDET_PUEN = 1 */ - wTmp = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN|mskUSBRAM_EN|mskVREG33DIS_EN|mskFLTDET_PUEN_DISABLE); - - //!!NEVER REMOVE!!! - SN_USB->CFG = wTmp; - for (i = 0; i < DISCHARE_DELAY; i++); - SN_USB->CFG = (wTmp&(~mskVREG33DIS_EN))|mskDPPU_EN; - //!!NEVER REMOVE!!! - - SN_USB->PHYPRM = (0x01U<<31); - return; -} - -/***************************************************************************** -* Function : USB_ClrEPnToggle -* Description : USB Clear EP1~EP6 toggle bit to DATA0 -* write 1: toggle bit Auto. -* write 0: clear EPn toggle bit to DATA0 -* Input : hwEPNum ->EP1~EP6 -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_ClrEPnToggle (uint32_t hwEPNum) -{ - SN_USB->EPTOGGLE &= ~(0x1< USB_EP6) - return; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - *pEPn_ptr = 0; //** SET DISABLE. No handshake IN/OUT token. -} - -/***************************************************************************** -* Function : USB_EPnNak -* Description : SET EP1~EP6 is NAK. -* For IN will handshake NAK to IN token. -* For OUT will handshake NAK to OUT token. -* Input : wEPNum -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_EPnNak (uint32_t wEPNum) -{ - volatile uint32_t *pEPn_ptr; - if(wEPNum > USB_EP6) - return; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - *pEPn_ptr = mskEPn_ENDP_EN; //** SET NAK -} - -/***************************************************************************** -* Function : USB_EPnAck -* Description : SET EP1~EP6 is ACK. -* For IN will handshake bBytent to IN token. -* For OUT will handshake ACK to OUT token. -* Input : wEPNum:EP1~EP6. -* bBytecnt: Byte Number of Handshake. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_EPnAck (uint32_t wEPNum, uint8_t bBytecnt) -{ - volatile uint32_t *pEPn_ptr; - if (wEPNum > USB_EP6) - return; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - *pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt); -} - -/***************************************************************************** -* Function : USB_EPnAck -* Description : SET EP1~EP6 is STALL. For IN will handshake STALL to IN token. -* For OUT will handshake STALL to OUT token. -* Input : wEPNum:EP1~EP6. -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_EPnStall (uint32_t wEPNum) -{ - volatile uint32_t *pEPn_ptr; - if(wEPNum > USB_EP6) //wEPNum != EP0~EP6 - return; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - if (wEPNum == USB_EP0) - { - if(SN_USB->INSTS & mskEP0_PRESETUP) - return; - } - *pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_STALL); -} - -/***************************************************************************** -* Function : USB_EPnEnabled -* Description : check if EP0~EP4 enabled or not -* Input : wEPNum:EP0~EP4. -* Output : None -* Return : true - enabled/false - disabled -* Note : None -*****************************************************************************/ -_Bool USB_EPnEnabled(uint32_t wEPNum) -{ - volatile uint32_t *pEPn_ptr; - if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6 - return 0; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - return (((*pEPn_ptr) & mskEPn_ENDP_EN) == mskEPn_ENDP_EN); -} - -/***************************************************************************** -* Function : USB_EPnStalled -* Description : GET EP0~EP4 state. -* Input : wEPNum:EP0~EP4. -* Output : None -* Return : mskEPn_ENDP_STATE -* Note : None -*****************************************************************************/ -_Bool USB_EPnStalled(uint32_t wEPNum) -{ - volatile uint32_t *pEPn_ptr; - if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6 - return 0; - pEPn_ptr = &SN_USB->EP0CTL + wEPNum; - return (((*pEPn_ptr) & mskEPn_ENDP_STATE) == mskEPn_ENDP_STATE_STALL); -} - -/***************************************************************************** -* Function : USB_RemoteWakeUp -* Description : USB Remote wakeup: USB D+/D- siganl is J-K state. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_RemoteWakeUp() -{ - __USB_JSTATE_DRIVER; //** J state ;Full speed D+ = 1, D- = 0 - USB_DelayJstate(); - __USB_KSTATE_DRIVER; //** K state ;Full speed D+ = 0, D- = 1 - USB_DelayKstate(); - SN_USB->SGCTL &= ~mskBUS_DRVEN; -} - -/***************************************************************************** - * Function : USB_DelayJstate - * Description : For J state delay. about 180us - * Input : None - * Output : None - * Return : None - * Note : None - *****************************************************************************/ -void USB_DelayJstate() -{ - uint32_t i; - for (i = 0; i < 300; i++) - ; // delay 180us -} - -/***************************************************************************** - * Function : USB_DelayKstate - * Description : For K state delay. about 14 ~ 14.5ms - * Input : None - * Output : None - * Return : None - * Note : None - *****************************************************************************/ -void USB_DelayKstate() -{ - uint32_t i; - for (i = 0; i < K_STATE_DELAY; i++) - ; // require delay 1ms ~ 15ms -} - -/***************************************************************************** -* Function : USB_EPnBufferOffset -* Description : SET EP1~EP6 RAM point address -* Input : wEPNum: EP1~EP6 -* wAddr of device address -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr) -{ - volatile uint32_t *pEPn_ptr; - if ((wEPNum > USB_EP0) && (wEPNum <= USB_EP6)) //wEPNum = EP1 ~ EP6 - { - pEPn_ptr = &SN_USB->EP1BUFOS; // Assign point to EP1 RAM address - *(pEPn_ptr+wEPNum-1) = wAddr; // SET point to EPn RAM address - } -} - -/***************************************************************************** -* Function : USB_ResetEvent -* Description : recevice USB bus reset to Initial parameter -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_ResetEvent (void) -{ - uint32_t wLoop; - __USB_CLRINSTS(0xFFFFFFFF); // Clear all USB Event status - __USB_SETADDRESS(0); // Set USB address = 0 - USB_EPnStall(USB_EP0); // Set EP0 enable & INOUTSTALL - - for (wLoop=USB_EP1; wLoop<=USB_EP6; wLoop++) - USB_EPnDisable(wLoop); // Set EP1~EP6 disable & NAK -} - -/***************************************************************************** -* Function : USB_WakeupEvent -* Description : Enable USB CLK and PHY -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void USB_WakeupEvent (void) -{ - USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting - __USB_PHY_ENABLE; //** enable ESD_EN & PHY_EN - __USB_CLRINSTS(mskBUS_WAKEUP); //** Clear BUS_WAKEUP -} \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h deleted file mode 100644 index 4c36a252d1..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** - **************************************************************************** -****************************************************************************/ -#ifndef __USBHW_H__ -#define __USBHW_H__ - -//** USB Remote Wakeup I/O Define -//** USB Remote Wakeup I/O Port Define, Default P1.5 -#define REMOTE_WAKEUP_IO_P0 DISABLE -#define REMOTE_WAKEUP_IO_P1 ENABLE -#define REMOTE_WAKEUP_IO_P2 DISABLE -#define REMOTE_WAKEUP_IO_P3 DISABLE - -//** USB Remote Wakeup I/O Bit Define -#define REMOTE_WAKEUP_IO_P0_BIT 0x0000 -#define REMOTE_WAKEUP_IO_P1_BIT 0x0020 -#define REMOTE_WAKEUP_IO_P2_BIT 0x0000 -#define REMOTE_WAKEUP_IO_P3_BIT 0x0000 - -//** USB EPn NAK interrupt -#define EP1_NAK_IE DISABLE -#define EP2_NAK_IE DISABLE -#define EP3_NAK_IE DISABLE -#define EP4_NAK_IE DISABLE - -//** USB SOF interrupt -#define SOF_IE DISABLE - -/* AHB Clock Enable register */ -#define mskP0CLK_EN (0x1<<0) -#define mskP1CLK_EN (0x1<<1) -#define mskP2CLK_EN (0x1<<2) -#define mskP3CLK_EN (0x1<<3) -#define mskUSBCLK_EN (0x1<<4) -#define mskCT16B0CLK_EN (0x1<<6) -#define mskCT16B1CLK_EN (0x1<<7) -#define mskADCCLK_EN (0x1<<11) -#define mskSPI0CLK_EN (0x1<<12) -#define mskUART0CLK_EN (0x1<<16) -#define mskUART1CLK_EN (0x1<<17) -#define mskUART2CLK_EN (0x1<<18) -#define mskI2C0CLK_EN (0x1<<21) -#define mskWDTCLK_EN (0x1<<24) - -/* USB Interrupt Enable Bit Definitions */ -#define mskEP1_NAK_EN (0x1<<0) -#define mskEP2_NAK_EN (0x1<<1) -#define mskEP3_NAK_EN (0x1<<2) -#define mskEP4_NAK_EN (0x1<<3) -#define mskEP5_NAK_EN (0x1<<4) -#define mskEP6_NAK_EN (0x1<<5) -#define mskUSB_BUSWK_IE (0x1<<28) -#define mskUSB_IE (0x1<<29) -#define mskUSB_SOF_IE (0x1<<30) -#define mskBUS_IE (0x1U<<31) - -/* USB Interrupt Event Status Bit Definitions */ -#define mskEP1_NAK (0x1<<0) -#define mskEP2_NAK (0x1<<1) -#define mskEP3_NAK (0x1<<2) -#define mskEP4_NAK (0x1<<3) -#define mskEP5_NAK (0x1<<4) -#define mskEP6_NAK (0x1<<5) -#define mskEP1_ACK (0x1<<8) -#define mskEP2_ACK (0x1<<9) -#define mskEP3_ACK (0x1<<10) -#define mskEP4_ACK (0x1<<11) -#define mskEP5_ACK (0x1<<12) -#define mskEP6_ACK (0x1<<13) -#define mskERR_TIMEOUT (0x1<<17) -#define mskERR_SETUP (0x1<<18) -#define mskEP0_OUT_STALL (0x1<<19) -#define mskEP0_IN_STALL (0x1<<20) -#define mskEP0_OUT (0x1<<21) -#define mskEP0_IN (0x1<<22) -#define mskEP0_SETUP (0x1<<23) -#define mskEP0_PRESETUP (0x1<<24) -#define mskBUS_WAKEUP (0x1<<25) -#define mskUSB_SOF (0x1<<26) -#define mskBUS_RESUME (0x1<<29) -#define mskBUS_SUSPEND (0x1<<30) -#define mskBUS_RESET (0x1U<<31) - -/* USB Device Address Bit Definitions */ -#define mskUADDR (0x7F<<0) - -/* USB Configuration Bit Definitions */ -#define mskEP1_DIR (0x1<<0) -#define mskEP2_DIR (0x1<<1) -#define mskEP3_DIR (0x1<<2) -#define mskEP4_DIR (0x1<<3) -#define mskEP5_DIR (0x1<<4) -#define mskEP6_DIR (0x1<<5) -#define mskEP2_ISO (0x1<<9) -#define mskEP3_ISO (0x1<<10) -#define mskEP4_ISO (0x1<<11) -#define mskEP5_ISO (0x1<<12) -#define mskEP6_ISO (0x1<<13) -#define mskVREG33DIS_EN (0x1<<31) -#define mskUSBRAM_EN (0x1<<25) -#define mskFLTDET_PUEN_DISABLE (0x1<<26) // FixMe ? // #define mskDIS_PDEN (0x1<<26) -#define mskESD_EN (0x1<<27) -#define mskSIE_EN (0x1<<28) -#define mskDPPU_EN (0x1<<29) -#define mskPHY_EN (0x1<<30) -#define mskVREG33_EN (0x1U<<31) - -/* USB Signal Control Bit Definitions */ -#define mskBUS_DRVEN (0x1<<2) -#define mskBUS_DPDN_STATE (0x3<<0) -#define mskBUS_J_STATE (0x2<<0) // D+ = 1, D- = 0 -#define mskBUS_K_STATE (0x1<<0) // D+ = 0, D- = 1 -#define mskBUS_SE0_STATE (0x0<<0) // D+ = 0, D- = 0 -#define mskBUS_SE1_STATE (0x3<<0) // D+ = 1, D- = 1 -#define mskBUS_IDLE_STATE mskBUS_J_STATE - -/* USB Configuration Bit Definitions */ -#define mskEPn_CNT (0x1FF<<0) -#define mskEP0_OUT_STALL_EN (0x1<<27) -#define mskEP0_IN_STALL_EN (0x1<<28) -#define mskEPn_ENDP_STATE (0x3<<29) -#define mskEPn_ENDP_STATE_ACK (0x1<<29) -#define mskEPn_ENDP_STATE_NAK (0x0<<29) -#define mskEPn_ENDP_STATE_STALL (0x3<<29) -#define mskEPn_ENDP_EN (0x1U<<31) - -/* USB Endpoint Data Toggle Bit Definitions */ -#define mskEP1_CLEAR_DATA0 (0x1<<0) -#define mskEP2_CLEAR_DATA0 (0x1<<1) -#define mskEP3_CLEAR_DATA0 (0x1<<2) -#define mskEP4_CLEAR_DATA0 (0x1<<3) -#define mskEP5_CLEAR_DATA0 (0x1<<4) -#define mskEP6_CLEAR_DATA0 (0x1<<5) - -/* USB Endpoint n Buffer Offset Bit Definitions */ -#define mskEPn_OFFSET (0x1FF<<0) - -/* USB Frame Number Bit Definitions */ -#define mskFRAME_NO (0x7FF<<0) - -/* Rx & Tx Packet Length Definitions */ -#define PKT_LNGTH_MASK 0x000003FF - -/* nUsb_Status Register Definitions */ -#define mskBUSRESET (0x1<<0) -#define mskBUSSUSPEND (0x1<<1) -#define mskBUSRESUME (0x1<<2) -#define mskREMOTEWAKEUP (0x1<<3) -#define mskSETCONFIGURATION0CMD (0x1<<4) -#define mskSETADDRESS (0x1<<5) -#define mskSETADDRESSCMD (0x1<<6) -#define mskREMOTE_WAKEUP (0x1<<7) -#define mskDEV_FEATURE_CMD (0x1<<8) -#define mskSET_REPORT_FLAG (0x1<<9) -#define mskPROTOCOL_GET_REPORT (0x1<<10) -#define mskPROTOCOL_SET_IDLE (0x1<<11) -#define mskPROTOCOL_ARRIVAL (0x1<<12) -#define mskSET_REPORT_DONE (0x1<<13) -#define mskNOT_8BYTE_ENDDING (0x1<<14) -#define mskSETUP_OUT (0x1<<15) -#define mskSETUP_IN (0x1<<16) -#define mskINITREPEAT (0x1<<17) -#define mskREMOTE_WAKEUP_ACT (0x1<<18) - -//ISP KERNEL MODE -#define RETURN_KERNEL_0 0x5AA555AA -#define RETURN_KERNEL_1 0xCC3300FF -/*********Marco function***************/ - -//USB device address set -#define __USB_SETADDRESS(addr) (SN_USB->ADDR = addr) -//USB INT status register clear -#define __USB_CLRINSTS(Clrflag) (SN_USB->INSTSC = Clrflag) -//USB EP0_IN token set STALL -#define __USB_EP0INSTALL_EN (SN_USB->EP0CTL |= mskEP0_IN_STALL_EN) -//USB EP0_OUT token set STALL -#define __USB_EP0OUTSTALL_EN (SN_USB->EP0CTL |= mskEP0_OUT_STALL_EN) -//USB bus driver J state -#define __USB_JSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE)) -//USB bus driver K state -#define __USB_KSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_K_STATE)) -//USB PHY set enable -#define __USB_PHY_ENABLE (SN_USB->CFG |= (mskESD_EN|mskPHY_EN)) -//USB PHY set Disable -#define __USB_PHY_DISABLE (SN_USB->CFG &= ~(mskESD_EN|mskPHY_EN)) - -/***************************************/ - -/* USB SRAM */ -#define USB_SRAM_EP0_W0 *((uint32_t *)&SN_USB->SRAM+0) // EP0 SRAM Byte 0~3 -#define USB_SRAM_EP0_W1 *((uint32_t *)&SN_USB->SRAM+1) // EP0 SRAM Byte 4~7 -#define USB_SRAM_EP0_W2 *((uint32_t *)&SN_USB->SRAM+2) // EP0 SRAM Byte 8~11 -#define USB_SRAM_EP0_W3 *((uint32_t *)&SN_USB->SRAM+3) // EP0 SRAM Byte 12~15 -#define USB_SRAM_EP0_W4 *((uint32_t *)&SN_USB->SRAM+4) // EP0 SRAM Byte 16~19 -#define USB_SRAM_EP0_W5 *((uint32_t *)&SN_USB->SRAM+5) // EP0 SRAM Byte 20~23 -#define USB_SRAM_EP0_W6 *((uint32_t *)&SN_USB->SRAM+6) // EP0 SRAM Byte 24~27 -#define USB_SRAM_EP0_W7 *((uint32_t *)&SN_USB->SRAM+7) // EP0 SRAM Byte 28~31 -#define USB_SRAM_EP0_W8 *((uint32_t *)&SN_USB->SRAM+8) // EP0 SRAM Byte 32~35 -#define USB_SRAM_EP0_W9 *((uint32_t *)&SN_USB->SRAM+9) // EP0 SRAM Byte 36~39 -#define USB_SRAM_EP0_W10 *((uint32_t *)&SN_USB->SRAM+10) // EP0 SRAM Byte 40~43 -#define USB_SRAM_EP0_W11 *((uint32_t *)&SN_USB->SRAM+11) // EP0 SRAM Byte 44~47 -#define USB_SRAM_EP0_W12 *((uint32_t *)&SN_USB->SRAM+12) // EP0 SRAM Byte 48~51 -#define USB_SRAM_EP0_W13 *((uint32_t *)&SN_USB->SRAM+13) // EP0 SRAM Byte 52~55 -#define USB_SRAM_EP0_W14 *((uint32_t *)&SN_USB->SRAM+14) // EP0 SRAM Byte 56~59 -#define USB_SRAM_EP0_W15 *((uint32_t *)&SN_USB->SRAM+15) // EP0 SRAM Byte 60~63 - -/* TODO: orgaize better since this is MCU dependent: - * 240b has 1+4 EPs/256 Bytes USB SRAM - * 240 has 1+6 EPs/512 Bytes USB SRAM - * 260 has 1+4 EPs/256 Bytes USB SRAM - * */ -// USB EPn Buffer Offset Register -#define EP1_BUFFER_OFFSET_VALUE 0x40 -#define EP2_BUFFER_OFFSET_VALUE 0x80 -#define EP3_BUFFER_OFFSET_VALUE 0xC0 -#define EP4_BUFFER_OFFSET_VALUE 0x100 -#define EP5_BUFFER_OFFSET_VALUE 0x140 -#define EP6_BUFFER_OFFSET_VALUE 0x180 - -/* USB Endpoint Max Packet Size */ -#define USB_EP0_PACKET_SIZE 64 // only 8, 64 -#define USB_EP1_PACKET_SIZE 0x40 -#define USB_EP2_PACKET_SIZE 0x40 -#define USB_EP3_PACKET_SIZE 0x20 -#define USB_EP4_PACKET_SIZE 0x20 -#define USB_EP5_PACKET_SIZE 0x20 -#define USB_EP6_PACKET_SIZE 0x20 - -/* USB Endpoint Direction */ -#define USB_DIRECTION_OUT 0 -#define USB_DIRECTION_IN 1 - -/* USB Endpoint Address */ -#define USB_EP0 0x0 -#define USB_EP1 0x1 -#define USB_EP2 0x2 -#define USB_EP3 0x3 -#define USB_EP4 0x4 -#define USB_EP5 0x5 -#define USB_EP6 0x6 - -extern volatile uint32_t wUSB_EPnOffset[]; -extern volatile uint32_t wUSB_EPnMaxPacketSize[]; - -/* USB Hardware Functions */ -extern void USB_Init(void); -extern void USB_ClrEPnToggle(uint32_t wEPNum); -extern void USB_EPnDisable(uint32_t wEPNum); -extern void USB_EPnNak(uint32_t wEPNum); -extern void USB_EPnAck(uint32_t wEPNum, uint8_t bBytecnt); -extern void USB_EPnStall(uint32_t wEPNum); -extern _Bool USB_EPnEnabled(uint32_t wEPNum); -extern _Bool USB_EPnStalled(uint32_t wEPNum); - -extern void USB_RemoteWakeUp(void); -extern void USB_DelayJstate(void); -extern void USB_DelayKstate(void); -extern void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr); - -/* USB IRQ Functions*/ -extern void USB_ResetEvent(void); -extern void USB_WakeupEvent(void); - -#endif /* __USBHW_H__ */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c deleted file mode 100644 index d837576c96..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c +++ /dev/null @@ -1,106 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbsystem.c - * Purpose: USB Custom User Module - * Version: V1.01 - * Date: 2013/12 - *------------------------------------------------------------------------------*/ -#include -//#include "type.h" -//#include "..\Utility\Utility.h" - -#include "usbsystem.h" - - -void USB_SystemInit (void) -{ - - SN_FLASH->LPCTRL = 0x5AFA0000; //Disable Slow mode power saving - -//*********************************** -#if (USB_SYS_CLOCK_SETUP) - - #if (USB_SYS0_CLKCFG_VAL == USB_IHRC) //IHRC - SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC - while ((SN_SYS0->CSST & 0x01) != 0x01); //check IHRC ready - SN_SYS0->CLKCFG = 0x00; //switch IHRC - while ((SN_SYS0->CLKCFG & 0x70) != 0x00); - #endif - - #if (USB_SYS0_CLKCFG_VAL == USB_ILRC) //ILRC - SN_SYS0->CLKCFG = 0x1; - while ((SN_SYS0->CLKCFG & 0x70) != 0x10); //switch ILRC - #endif - - #if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL) //EHS XTAL - #if (USB_EHS_FREQ > 12) - SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz - #else - SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz - #endif - - SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL - while ((SN_SYS0->CSST & 0x10) != 0x10); - SN_SYS0->CLKCFG = 0x02; //switch XTAL - while ((SN_SYS0->CLKCFG & 0x70) != 0X20); - #endif -#endif - - #if (USB_PLL_ENABLE == 0x01) //SET PLL - SN_SYS0->PLLCTRL = USB_SYS0_PLLCTRL_EN; //ENABLE PLL - if(USB_PLL_CLKIN == 0x0) //PLL clk source is IHRC - { - SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC - SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_IHRC; - } - else //PLL clk source is XTAL - { - - #if (USB_EHS_FREQ > 12) - SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz - #else - SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz - #endif - - SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL - while ((SN_SYS0->CSST & 0x10) != 0x10); - - - - #if (USB_EHS_FREQ == 12) //XTAL = 12MHz - //SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL < 12MHz - SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_12MHz; - #endif - - #if (USB_EHS_FREQ == 16) //XTAL = 16MHz - SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz - SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_16MHz; - #endif - - #if (USB_EHS_FREQ == 24) //XTAL = 24MHz - SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz - SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_24MHz; - #endif - SN_SYS0->ANBCTRL |= (1<<4); //Enable EHS XTAL - while ((SN_SYS0->CSST & 0x10) != 0x10); - - #if (USB_PLL_CLKIN == 0x01 ) - SN_SYS0->PLLCTRL |= (0x01<<12); - SN_SYS0->PLLCTRL |= (0x01<<15); //ENABLE PLL - #endif - } - #endif - - #if (USB_SYS0_CLKCFG_VAL == USB_PLL) - { - while ((SN_SYS0->CSST & 0x40) != 0x40); - SN_SYS0->CLKCFG = 0x4; //CLK switch PLL - while ((SN_SYS0->CLKCFG & 0x70) != 0x40); - } - #endif - SN_SYS0->AHBCP = USB_AHB_PRESCALAR; - #if (USB_CLKOUT_SEL_VAL > 0) //CLKOUT - SN_SYS1->AHBCLKEN |= (USB_CLKOUT_SEL_VAL<<28); - #endif -} \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h deleted file mode 100644 index c9aa2a8bc5..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h +++ /dev/null @@ -1,145 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbsystem.h - * Purpose: USB Custom User Definitions - * Version: V1.20 - *----------------------------------------------------------------------------*/ - -#ifndef __USBSYSTEM_H__ -#define __USBSYSTEM_H__ -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// System Clock Configuration -// SYSCLKSEL (SYS0_CLKCFG) -// <0=> ILRC -// <1=> IHRC -// <2=> EHS X'TAL -// <4=> PLL -// -// EHS Source Frequency (MHz) -// <10-25> -// -// PLL Control Register (SYS0_PLLCTRL) -// F_CLKOUT = F_VCO / P = (F_CLKIN / F * M) / P -// 10 MHz <= F_CLKIN <= 25 MHz -// 156 MHz <= (F_CLKIN / F * M) <= 320 MHz -// MSEL -// <24=> MSEL = 24 -// <18=> MSEL = 18 -// <12=> MSEL = 12 -// PSEL -// <3=> P = 6 -// <4=> P = 8 -// FSEL -// <0=> F = 1 -// <1=> F = 2 -// PLL CLKIN Source selection -// <0=> IHRC -// <1=> EHS X'TAL -// PLL Enable selection -// <1=> Enable -// -// -// AHB Clock Prescaler Register (SYS0_AHBCP) -// <0=> SYSCLK/1 -// <1=> SYSCLK/2 -// <2=> SYSCLK/4 -// <3=> SYSCLK/8 -// <4=> SYSCLK/16 -// <5=> SYSCLK/32 -// <6=> SYSCLK/64 -// <7=> SYSCLK/128 -// <8=> SYSCLK/256 -// <9=> SYSCLK/512 -// -// CLKOUT selection -// <0=> Disable -// <1=> ILRC -// <2=> ELS X'TAL -// <4=> HCLK -// <5=> IHRC -// <6=> EHS X'TAL -// <7=> PLL -// -*/ - -#define USB_SYS_CLOCK_SETUP 1 -#define USB_SYS0_CLKCFG_VAL USB_PLL -#define USB_EHS_FREQ 12 -#define USB_PLL_MSEL 18 -#define USB_PLL_PSEL 3 -#define USB_PLL_FSEL 0 -#define USB_PLL_CLKIN 0 -#define USB_PLL_ENABLE 1 -#define USB_AHB_PRESCALAR 0x0 -#define USB_CLKOUT_SEL_VAL 0x0 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -#define USB_IHRC 0 -#define USB_ILRC 1 -#define USB_EHSXTAL 2 -#define USB_ELSXTAL 3 -#define USB_PLL 4 - -#define USB_IHRC_EN 1 -#define USB_SYS0_PLLCTRL_EN 0x8000 -#define USB_PSEL_6 (0x03<<5) -#define USB_PSEL_8 (0x04<<5) -#define USB_MSEL_24 24 -#define USB_MSEL_18 18 -#define USB_MSEL_12 12 -#define USB_PLL_CLKSOURCE_IHRC (USB_PSEL_6|USB_MSEL_24) -#define USB_PLL_CLKSOURCE_12MHz (USB_PSEL_6|USB_MSEL_24) -#define USB_PLL_CLKSOURCE_16MHz (USB_PSEL_6|USB_MSEL_18) -#define USB_PLL_CLKSOURCE_24MHz (USB_PSEL_6|USB_MSEL_12) - -#define USB_PLL_DLEYA_TIME 100000 -#define USB_PLL_10US_TIME 76 - -#if (USB_SYS0_CLKCFG_VAL == USB_PLL) - #define K_STATE_DELAY USB_PLL_DLEYA_TIME*(USB_AHB_PRESCALAR+1) - #define DISCHARE_DELAY K_STATE_DELAY - #define UTILITY_10US_DELAY USB_PLL_10US_TIME*(USB_AHB_PRESCALAR+1) -#endif //end USB_SYS0_CLKCFG_VAL == PLL - -#if (USB_SYS0_CLKCFG_VAL == USB_IHRC) -#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1) -#define DISCHARE_DELAY K_STATE_DELAY - #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1) -#endif //end USB_SYS0_CLKCFG_VAL == USB_IHRC - -#if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL) -#if (USB_EHS_FREQ == 12) - #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1) - #define DISCHARE_DELAY K_STATE_DELAY - #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1) -#elif (USB_EHS_FREQ == 16) - #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/3)*(USB_AHB_PRESCALAR+1) - #define DISCHARE_DELAY K_STATE_DELAY - #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/3)*(USB_AHB_PRESCALAR+1) -#elif (USB_EHS_FREQ == 24) - #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/2)*(USB_AHB_PRESCALAR+1) - #define DISCHARE_DELAY K_STATE_DELAY - #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/2)*(USB_AHB_PRESCALAR+1) -#endif //end USB_EHS_FREQ -#endif //end USB_SYS0_CLKCFG_VAL == USB_EHSTAL - -extern void USB_SystemInit (void); -#endif /* __USBSYSTEM_H__ */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c deleted file mode 100644 index a774d183dc..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c +++ /dev/null @@ -1,155 +0,0 @@ -/******************** (C) COPYRIGHT 2014 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2014/01 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: WDT related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* 1.1 2014/01/20 SA1 1. Modify WDT_ReloadValue function -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include -#include "WDT.h" -#include "..\..\System\SYS_con_drive.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : WDT_IRQHandler -* Description : ISR of WDT interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void WDT_IRQHandler(void) -{ - SN_GPIO2->DATA_b.DATA0 = ~SN_GPIO2->DATA_b.DATA0; //P2.0 toggle - - __WDT_FEED_VALUE; - - __WDT_CLRINSTS; //Clear WDT interrupt flag -} - -/***************************************************************************** -* Function : WDT_Init -* Description : WDT initial -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void WDT_Init(void) -{ - uint32_t wRegBuf; - - WDT_SelectClockSource(WDT_CLKSEL_ILRC); //clock source select - - #if WDT_MODE == INTERRUPT - wRegBuf = mskWDT_WDTIE_ENABLE; //WDT as interrupt mode - #endif - - #if WDT_MODE == RESET - wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode - #endif - - wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag - - wRegBuf = wRegBuf | mskWDT_WDKEY; - - SN_WDT->CFG = wRegBuf; - - WDT_ReloadValue(61); //Set overflow time = 250ms - - WDT_NvicEnable(); //Enable WDT NVIC interrupt - - __WDT_ENABLE; //Enable WDT -} - -/***************************************************************************** -* Function : WDT_ReloadValue -* Description : set WDT reload value -* Input : time - - 0~255: overflow time set -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void WDT_ReloadValue(uint32_t time) -{ - uint32_t wRegBuf; - - wRegBuf = time | mskWDT_WDKEY; - - SN_WDT->TC = wRegBuf; - - __WDT_FEED_VALUE; -} - -/*********************************************************************************** -* Function : WDT_SelectClockSource -* Description : Select WDT clcok source -* Input : WDT clock source - - WDT_CLKSEL_IHRC or WDT_CLKSEL_HCLK or WDT_CLKSEL_ILRC or WDT_CLKSEL_ELS -* Output : None -* Return : None -* Note : None -***********************************************************************************/ -void WDT_SelectClockSource(uint32_t src) -{ - if (src == WDT_CLKSEL_IHRC) - SYS0_EnableIHRC(); - else if (src == WDT_CLKSEL_ELS) - SYS0_EnableELSXtal(); - - SN_WDT->CLKSOURCE = mskWDT_WDKEY | src; //clock source select -} - -/***************************************************************************** -* Function : WDT_NvicEnable -* Description : Enable WDT interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void WDT_NvicEnable(void) -{ - NVIC_ClearPendingIRQ(WDT_IRQn); - NVIC_EnableIRQ(WDT_IRQn); - NVIC_SetPriority(WDT_IRQn, 0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : WDT_NvicDisable -* Description : Disable WDT interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void WDT_NvicDisable(void) -{ - NVIC_DisableIRQ(WDT_IRQn); -} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h deleted file mode 100644 index 67e44a362c..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef __SN32F240_WDT_H -#define __SN32F240_WDT_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define RESET 0 //WDT as Reset mode -#define INTERRUPT 1 //WDT as Interrupt mode -#define WDT_MODE INTERRUPT - //RESET_MODE : WDT as Reset mode - -//Watchdog register key -#define mskWDT_WDKEY (0x5AFA<<16) - -//Watchdog interrupt flag -#define mskWDT_WDTINT (1<<2) - -//Watchdog interrupt enable -#define WDT_WDTIE_DISABLE 0 -#define WDT_WDTIE_ENABLE 1 -#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1) -#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1) - -//Watchdog enable -#define mskWDT_WDTEN_DISABLE 0 -#define mskWDT_WDTEN_ENABLE 1 - -//Watchdog Clock source -#define WDT_CLKSEL_IHRC 0 -#define WDT_CLKSEL_HCLK 1 -#define WDT_CLKSEL_ILRC 2 -#define WDT_CLKSEL_ELS 3 - -//Watchdog Feed value -#define mskWDT_FV 0x55AA - -/*_____ M A C R O S ________________________________________________________*/ -//Watchdog Feed Value -#define __WDT_FEED_VALUE (SN_WDT->FEED = (mskWDT_WDKEY | mskWDT_FV)) - -//WDT Enable/Disable -#define __WDT_ENABLE (SN_WDT->CFG |= (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE)) -#define __WDT_DISABLE (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTEN_ENABLE))) - -//WDT INT status register clear -#define __WDT_CLRINSTS (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTINT))) - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void WDT_Init(void); -void WDT_ReloadValue(uint32_t time); -void WDT_SelectClockSource(uint32_t src); -void WDT_NvicEnable(void); -void WDT_NvicDisable(void); -#endif /*__SN32F240_WDT_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c deleted file mode 100644 index 964a1f6c9a..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c +++ /dev/null @@ -1,128 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: ADC related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include -#include "ADC.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -uint8_t bADC_StartConv; - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : ADC_Init -* Description : Initialization of ADC -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_Init(void) -{ - SN_SYS1->AHBCLKEN_b.ADCCLKEN = 1; //Enables HCLK for ADC - - SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC - - UT_DelayNx10us(10); //Delay 100us - - SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal reference - - SN_ADC->ADM_b.VHS = ADC_VHS_VDD; //Set ADC high reference voltage source as VDD - - SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel - - SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit - - SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV1; //ADC_CLK = ADC_PCLK/1 - //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV2; //ADC_CLK = ADC_PCLK/2 - //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV4; //ADC_CLK = ADC_PCLK/4 - //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV8; //ADC_CLK = ADC_PCLK/8 - //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV16; //ADC_CLK = ADC_PCLK/16 - //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32 - - SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel - - SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt - - ADC_NvicEnable(); //Enable ADC NVIC interrupt -} - -/***************************************************************************** -* Function : ADC_Read -* Description : Read ADC converted data -* Input : None -* Output : None -* Return : Data in ADB register -* Note : None -*****************************************************************************/ -uint16_t ADC_Read(void) -{ - return SN_ADC->ADB; -} - -/***************************************************************************** -* Function : ADC_IRQHandler -* Description : ISR of ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void ADC_IRQHandler(void) -{ - bADC_StartConv = 0; - - SN_ADC->RIS = 0x0; //clear interrupt flag -} - -/***************************************************************************** -* Function : ADC_NvicEnable -* Description : Enable ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_NvicEnable(void) -{ - NVIC_ClearPendingIRQ(ADC_IRQn); - NVIC_EnableIRQ(ADC_IRQn); - NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : ADC_NvicDisable -* Description : Disable ADC interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void ADC_NvicDisable(void) -{ - NVIC_DisableIRQ(ADC_IRQn); -} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h deleted file mode 100644 index ef93536f2d..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef __SN32F2XX_ADC_H -#define __SN32F2XX_ADC_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -//ADC Internal Reference Voltage level -#define ADC_VHS_INTERNAL_2V 0 -#define ADC_VHS_INTERNAL_3V 1 -#define ADC_VHS_INTERNAL_4P5V 2 -#define ADC_VHS_VDD 7 - -//ADC high reference voltage source select bit -#define ADC_AVREFHSEL_INTERNAL 0x0 -#define ADC_AVREFHSEL_EXTERNAL 0x1 - -//ADC Enable bit -#define ADC_ADENB_DIS 0x0 -#define ADC_ADENB_EN 0x1 - -//ADC Clock source divider -#define ADC_ADCKS_DIV1 0x0 -#define ADC_ADCKS_DIV2 0x1 -#define ADC_ADCKS_DIV4 0x2 -#define ADC_ADCKS_DIV8 0x3 -#define ADC_ADCKS_DIV16 0x5 -#define ADC_ADCKS_DIV32 0x6 - -//ADC resolution control bit -#define ADC_ADLEN_8BIT 0x0 -#define ADC_ADLEN_12BIT 0x1 - -//ADC start control bit -#define ADC_ADS_STOP 0x0 -#define ADC_ADS_START 0x1 - -//ADC global channel select bit -#define ADC_GCHS_DIS 0x0 -#define ADC_GCHS_EN 0x1 - -//ADC input channels select bit -#define ADC_CHS_AIN0 0x0 //P2.0 -#define ADC_CHS_AIN1 0x1 //P2.1 -#define ADC_CHS_AIN2 0x2 //P2.2 -#define ADC_CHS_AIN3 0x3 //P2.3 -#define ADC_CHS_AIN4 0x4 //P2.4 -#define ADC_CHS_AIN5 0x5 //P2.5 -#define ADC_CHS_AIN6 0x6 //P2.6 -#define ADC_CHS_AIN7 0x7 //P2.7 -#define ADC_CHS_AIN8 0x8 //P2.8 -#define ADC_CHS_AIN9 0x9 //P2.9 -#define ADC_CHS_AIN10 0xA //P2.10 -#define ADC_CHS_AIN11 0xB //P2.11 -#define ADC_CHS_AIN12 0xC //P2.12 -#define ADC_CHS_AIN13 0xD //P2.13 -#define ADC_CHS_AIN14 0xE //P2.14 -#define ADC_CHS_AIN15 0xF //P2.15 -#define ADC_CHS_AIN16 0x10 //Internal Ref. Voltage -#define ADC_CHS_AIN17 0x11 //VDD -#define ADC_CHS_AIN18 0x12 //VSS - -//ADC Interrupt Enable register(ADC_IE) -#define ADC_IE_AIN0 0x00001 -#define ADC_IE_AIN1 0x00002 -#define ADC_IE_AIN2 0x00004 -#define ADC_IE_AIN3 0x00008 -#define ADC_IE_AIN4 0x00010 -#define ADC_IE_AIN5 0x00020 -#define ADC_IE_AIN6 0x00040 -#define ADC_IE_AIN7 0x00080 -#define ADC_IE_AIN8 0x00100 -#define ADC_IE_AIN9 0x00200 -#define ADC_IE_AIN10 0x00400 -#define ADC_IE_AIN11 0x00800 -#define ADC_IE_AIN12 0x01000 -#define ADC_IE_AIN13 0x02000 -#define ADC_IE_AIN14 0x04000 -#define ADC_IE_AIN15 0x08000 -#define ADC_IE_AIN16 0x10000 -#define ADC_IE_AIN17 0x20000 -#define ADC_IE_AIN18 0x40000 - -//ADC Raw Interrupt Status register(ADC_RIS) -#define mskADC_IF_AIN0 (0x1<<0) //P2.0 -#define mskADC_IF_AIN1 (0x1<<1) //P2.1 -#define mskADC_IF_AIN2 (0x1<<2) //P2.2 -#define mskADC_IF_AIN3 (0x1<<3) //P2.3 -#define mskADC_IF_AIN4 (0x1<<4) //P2.4 -#define mskADC_IF_AIN5 (0x1<<5) //P2.5 -#define mskADC_IF_AIN6 (0x1<<6) //P2.6 -#define mskADC_IF_AIN7 (0x1<<7) //P2.7 -#define mskADC_IF_AIN8 (0x1<<8) //P2.8 -#define mskADC_IF_AIN9 (0x1<<9) //P2.9 -#define mskADC_IF_AIN10 (0x1<<10) //P2.10 -#define mskADC_IF_AIN11 (0x1<<11) //P2.11 -#define mskADC_IF_AIN12 (0x1<<12) //P2.12 -#define mskADC_IF_AIN13 (0x1<<13) //P2.13 -#define mskADC_IF_AIN14 (0x1<<14) //P2.14 -#define mskADC_IF_AIN15 (0x1<<15) //P2.15 -#define mskADC_IF_AIN16 (0x1<<16) //Internal Ref. Voltage -#define mskADC_IF_AIN17 (0x1<<17) //VDD -#define mskADC_IF_AIN18 (0x1<<18) //VSS - -/*_____ M A C R O S ________________________________________________________*/ - - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern uint8_t bADC_StartConv; - -void ADC_Init(void); -uint16_t ADC_Read(void); -void ADC_NvicEnable(void); -void ADC_NvicDisable(void); - -#endif /*__SN32F2XX_ADC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk new file mode 100644 index 0000000000..624f671b81 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/ADC diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.c new file mode 100644 index 0000000000..593ff41b74 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.c @@ -0,0 +1,317 @@ +/* + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADC/hal_adc_lld.c + * @brief SN32 ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC driver identifier.*/ +#if SN32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ +#define ADC_CHANNEL_MASK 0x0F +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Stops an ongoing conversion, if any. + * + * @param[in] adc pointer to the ADC registers block + */ +static void adc_lld_stop_adc(SN_ADC_Type *adc) { + + if (adc->ADM_b.EOC == ADC_EOC_BUSY) { + adc->ADM_b.EOC = ADC_EOC_RESET; + adc->IE = 0; + } + adcSN32DisableGCHS(adc); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SN32_ADC_USE_ADC1 || defined(__DOXYGEN__) +#if !defined(SN32_ADC_HANDLER) +#error "SN32_ADC_HANDLER not defined" +#endif +/** + * @brief ADC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_ADC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + adc_lld_serve_interrupt(&ADCD1); + +#if defined(SN32_ADC_ADC1_IRQ_HOOK) + SN32_ADC_ADC1_IRQ_HOOK +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if SN32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = SN_ADC; + /* The vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(SN32_ADC_NUMBER, SN32_ADC_IRQ_PRIORITY); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC peripheral and clock.*/ + if (adcp->state == ADC_STOP) { +#if SN32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + sys1EnableADC(); + adcp->adc->ADM_b.ADENB = ADC_ADENB_EN; + osalThreadSleepMicroseconds(SN32_ADC_WAKEUP_DURATION); + /* Clock settings.*/ + adcp->adc->ADM_b.ADCKS = SN32_ADC_PRESC; + } +#endif /* SN32_ADC_USE_ADC1 */ + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC peripheral and clock.*/ + if (adcp->state == ADC_READY) { + + /* Disabling the ADC.*/ + adc_lld_stop_adc(adcp->adc); + adcp->adc->ADM_b.ADENB = ADC_ADENB_DIS; + while ((adcp->adc->ADM_b.ADENB & ADC_ADENB_EN) != 0U) { + /* Waiting for ADC to be disabled.*/ + } + +#if SN32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + sys1DisableADC(); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + const ADCConversionGroup *grpp = adcp->grpp; + + /* Apply ADC configuration.*/ + if(grpp->avrefhsel) adcSN32EnableAVREFHSEL(adcp); + adcp->adc->ADM_b.VHS = grpp->vhs; + adcSN32EnableGCHS(adcp->adc); + adcp->adc->ADM_b.ADLEN = grpp->adlen; + + adcp->number_of_samples = adcp->depth * grpp->num_channels; + adcp->current_index = 0; + + /* Skip to the next channel */ + adcp->current_channel = 0; + while (((1 << adcp->current_channel) & grpp->chs) == 0) { + adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK; + } + + /* Select ADC channel. */ + adcp->adc->ADM_b.CHS = adcp->current_channel; + + /* Enable ADC interrupt. */ + adcp->adc->RIS = 0U; + adcp->adc->IE = ADC_IE_AIN(adcp->current_channel); + + /* ADC conversion start.*/ + adcp->adc->ADM_b.ADS |= ADC_ADS_START; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + adc_lld_stop_adc(adcp->adc); +} + +/** + * @brief ISR code. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_serve_interrupt(ADCDriver *adcp) { + + /* Disable Interrupt, Disable Channel */ + adcp->adc->IE = 0U; + adcp->adc->ADM_b.CHS = 0U; + adcp->adc->RIS = 0U; + + /* Read the sample into the buffer */ + adcp->samples[adcp->current_index++] = adcp->adc->ADB; + + bool more = true; + /* At the end of the buffer then we may be finished */ + if (adcp->current_index == adcp->number_of_samples) { + /* We are never finished in circular mode */ + more = adcp->grpp->circular; + + _adc_isr_full_code(adcp); + + adcp->current_index = 0; + + } + + if (more) { + + /* Signal half completion in circular mode. */ + if (adcp->grpp->circular && + (adcp->current_index == (adcp->number_of_samples / 2))) { + + _adc_isr_half_code(adcp); + } + + /* Skip to the next channel */ + do { + adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK; + } while (((1 << adcp->current_channel) & adcp->grpp->chs) == 0); + + /* Enable Interrupt, Select the Channel */ + adcp->adc->ADM_b.CHS = adcp->current_channel; + adcp->adc->IE = ADC_IE_AIN(adcp->current_channel); + /* Sample the next channel */ + adcp->adc->ADM_b.ADS |= ADC_ADS_START; + } +} + +/** + * @brief Enables the AVREFHSEL bit. + * @details The AVREFHSEL bit is required in order to sample the VREF channel. + * @note This is an SN32-only functionality. + * @note This function is meant to be called after @p adcStart(). + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adcSN32EnableAVREFHSEL(ADCDriver *adcp) { + adcp->adc->ADM_b.AVREFHSEL |= ADC_AVREFHSEL_EXTERNAL; +} + +/** + * @brief Disables the AVREFHSEL bit. + * @details The AVREFHSEL bit is required in order to sample the VREF channel. + * @note This is an SN32-only functionality. + * @note This function is meant to be called after @p adcStart(). + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adcSN32DisableAVREFHSEL(ADCDriver *adcp) { + adcp->adc->ADM_b.AVREFHSEL &= ~ADC_AVREFHSEL_EXTERNAL; +} + +/** + * @brief Enables the GCHS bit. + * @details The GCHS bit is required in order to sample the AIN channels. + * @note This is an SN32-only functionality. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adcSN32EnableGCHS(SN_ADC_Type *adc) { + adc->ADM_b.GCHS |= ADC_GCHS_EN; +} + +/** + * @brief Disables the GCHS bit. + * @details The GCHS bit is required in order to sample the AIN channels. + * @note This is an SN32-only functionality. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adcSN32DisableGCHS(SN_ADC_Type *adc) { + adc->ADM_b.GCHS &= ~ADC_GCHS_EN; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.h new file mode 100644 index 0000000000..4786167b81 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/hal_adc_lld.h @@ -0,0 +1,250 @@ +/* + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADC/hal_adc_lld.h + * @brief SN32 ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H +#define HAL_ADC_LLD_H + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ADC ADM register configuration helpers + * @{ + */ +//ADC Enable bit +#define ADC_ADENB_DIS 0x0 +#define ADC_ADENB_EN 0x1 + +//ADC start control bit +#define ADC_ADS_STOP 0x0 +#define ADC_ADS_START 0x1 + +//ADC End Of Conversion bit +#define ADC_EOC_BUSY 0x0 +#define ADC_EOC_RESET 0x1 + +//ADC global channel select bit +#define ADC_GCHS_DIS 0x0 +#define ADC_GCHS_EN 0x1 + +//ADC high reference voltage source select bit +#define ADC_AVREFHSEL_INTERNAL 0x0 +#define ADC_AVREFHSEL_EXTERNAL 0x1 +/** @} */ + +/** + * @name ADC Internal reference voltage level selection helpers + * @{ + */ +#define ADC_ADM_VREF_2_0V 0U // Internal 2.0V as ADC internal reference high voltage +#define ADC_ADM_VREF_3_0V 1U // Internal 3.0V as ADC internal reference high voltage +#define ADC_ADM_VREF_4_5V 2U // Internal 4.5V as ADC internal reference high voltage +#define ADC_ADM_VREF_VDD_2_0V_AIN 4U // VDD as ADC internal reference high voltage, Internal 2.0V as AIN +#define ADC_ADM_VREF_VDD_3_0V_AIN 5U // VDD as ADC internal reference high voltage, Internal 3.0V as AIN +#define ADC_ADM_VREF_VDD_4_5V_AIN 6U // VDD as ADC internal reference high voltage, Internal 4.5V as AIN +#define ADC_ADM_VREF_VDD 7U // VDD as ADC internal reference high voltage + +/** @} */ + +/** + * @name ADC Interrupt register configuration helpers + * @{ + */ +// ADC Interrupt Enable register (ADC_IE) +#define ADC_IE_AIN(n) (1U << (n)) +//ADC Raw Interrupt Status register(ADC_RIS) +#define mskADC_IF_AIN(n) (1U << (n)) + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC driver enable switch. + * @details If set to @p TRUE the support for ADC is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define SN32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(SN32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_ADC_IRQ_PRIORITY 3 +#endif + +/* + * @brief ADC prescaler setting. + */ +#if !defined(SN32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__) +#define SN32_ADC_PRESCALER_VALUE 1 +#endif + +/** + * @brief ADC wake-up procedure duration. + */ +#if !defined(SN32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__) +#define SN32_ADC_WAKEUP_DURATION 100 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks.*/ +#if !defined(SN32_HAS_ADC) +#error "SN32_HAS_ADC not defined in registry" +#endif + +#if !defined(SN32_ADC_HANDLER) +#error "SN32_ADC_HANDLER not defined in registry" +#endif + +#if !defined(SN32_ADC_NUMBER) +#error "SN32_ADC_NUMBER not defined in registry" +#endif + +/* ADC IRQ priority tests.*/ +#if !OSAL_IRQ_IS_VALID_PRIORITY(SN32_ADC_ADC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC" +#endif + +/* ADC clock source checks.*/ +#if SN32_ADC_PRESCALER_VALUE == 1 +#define SN32_ADC_PRESC 0U +#elif SN32_ADC_PRESCALER_VALUE == 2 +#define SN32_ADC_PRESC 1U +#elif SN32_ADC_PRESCALER_VALUE == 4 +#define SN32_ADC_PRESC 2U +#elif SN32_ADC_PRESCALER_VALUE == 8 +#define SN32_ADC_PRESC 3U +#elif SN32_ADC_PRESCALER_VALUE == 16 +#define SN32_ADC_PRESC 5U +#elif SN32_ADC_PRESCALER_VALUE == 32 +#define SN32_ADC_PRESC 6U +#else +#error "Invalid value assigned to SN32_ADC_PRESCALER_VALUE" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of an ADC error mask. + */ +typedef uint32_t adcerror_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the ADC driver structure. + */ +#define adc_lld_driver_fields \ + /* Pointer to the ADCx registers block.*/ \ + SN_ADC_Type *adc; \ + /* @brief Number of samples expected. */ \ + size_t number_of_samples; \ + /* @brief Current position in the buffer. */ \ + size_t current_index; \ + /* @brief Current channel index into group channel_mask. */ \ + size_t current_channel + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_configuration_group_fields \ + /* ADC VHS register initialization data.*/ \ + uint32_t vhs; \ + /* ADC ADLEN register initialization data.*/ \ + uint32_t adlen; \ + /* ADC AVREFHSEL register initialization data.*/ \ + uint32_t avrefhsel; \ + /* ADC CHS register initialization data. \ + NOTE: The number of bits at logic level one in this register must \ + be equal to the number in the @p num_channels field.*/ \ + uint32_t chs + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adc_lld_serve_interrupt(ADCDriver *adcp); + void adcSN32EnableAVREFHSEL(ADCDriver *adcp); + void adcSN32DisableAVREFHSEL(ADCDriver *adcp); + void adcSN32EnableGCHS(SN_ADC_Type *adc); + void adcSN32DisableGCHS(SN_ADC_Type *adc); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* HAL_ADC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h deleted file mode 100644 index 4eb6f04ff6..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h +++ /dev/null @@ -1,1331 +0,0 @@ -#ifndef __SN32F2XX_CT16_H -#define __SN32F2XX_CT16_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4000 0000 (CT16B0) - 0x4000 2000 (CT16B1) - 0x4000 4000 (CT16B2) -*/ - -/* CT16Bn Timer Control register (0x00) */ -#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit -#define CT16_CEN_EN 1 -#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0) -#define mskCT16_CEN_EN (CT16_CEN_EN<<0) - -#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit -#define mskCT16_CRST (CT16_CRST<<1) - - //[6:4] CT16Bn counting mode selection -#define CT16_CM_EDGE_UP 0 //Edge-aligned Up-counting mode -#define CT16_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode -#define CT16_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period -#define CT16_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period -#define CT16_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. -#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4) -#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4) -#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4) -#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4) -#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4) - -/* CT16Bn Count Control register (0x10) */ - //[1:0] Count/Timer Mode selection. -#define CT16_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. -#define CT16_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. -#define CT16_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. -#define CT16_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. -#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0) -#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0) -#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0) -#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0) - -#define CT16_CIS 0 //[3:2] Count Input Select -#define mskCT16_CIS (CT16_CIS<<2) - -/* CT16Bn Match Control register (0x14) */ -#define CT16_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt -#define CT16_MR0IE_DIS 0 -#define mskCT16_MR0IE_EN (CT16_MR0IE_EN<<0) -#define mskCT16_MR0IE_DIS (CT16_MR0IE_DIS<<0) - -#define CT16_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. -#define CT16_MR0RST_DIS 0 -#define mskCT16_MR0RST_EN (CT16_MR0RST_EN<<1) -#define mskCT16_MR0RST_DIS (CT16_MR0RST_DIS<<1) - -#define CT16_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. -#define CT16_MR0STOP_DIS 0 -#define mskCT16_MR0STOP_EN (CT16_MR0STOP_EN<<2) -#define mskCT16_MR0STOP_DIS (CT16_MR0STOP_DIS<<2) - -#define CT16_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt -#define CT16_MR1IE_DIS 0 -#define mskCT16_MR1IE_EN (CT16_MR1IE_EN<<3) -#define mskCT16_MR1IE_DIS (CT16_MR1IE_DIS<<3) - -#define CT16_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. -#define CT16_MR1RST_DIS 0 -#define mskCT16_MR1RST_EN (CT16_MR1RST_EN<<4) -#define mskCT16_MR1RST_DIS (CT16_MR1RST_DIS<<4) - -#define CT16_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. -#define CT16_MR1STOP_DIS 0 -#define mskCT16_MR1STOP_EN (CT16_MR1STOP_EN<<5) -#define mskCT16_MR1STOP_DIS (CT16_MR1STOP_DIS<<5) - -#define CT16_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt -#define CT16_MR2IE_DIS 0 -#define mskCT16_MR2IE_EN (CT16_MR2IE_EN<<6) -#define mskCT16_MR2IE_DIS (CT16_MR2IE_DIS<<6) - -#define CT16_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. -#define CT16_MR2RST_DIS 0 -#define mskCT16_MR2RST_EN (CT16_MR2RST_EN<<7) -#define mskCT16_MR2RST_DIS (CT16_MR2RST_DIS<<7) - -#define CT16_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. -#define CT16_MR2STOP_DIS 0 -#define mskCT16_MR2STOP_EN (CT16_MR2STOP_EN<<8) -#define mskCT16_MR2STOP_DIS (CT16_MR2STOP_DIS<<8) - -#define CT16_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt -#define CT16_MR3IE_DIS 0 -#define mskCT16_MR3IE_EN (CT16_MR3IE_EN<<9) -#define mskCT16_MR3IE_DIS (CT16_MR3IE_DIS<<9) - -#define CT16_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. -#define CT16_MR3RST_DIS 0 -#define mskCT16_MR3RST_EN (CT16_MR3RST_EN<<10) -#define mskCT16_MR3RST_DIS (CT16_MR3RST_DIS<<10) - -#define CT16_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. -#define CT16_MR3STOP_DIS 0 -#define mskCT16_MR3STOP_EN (CT16_MR3STOP_EN<<11) -#define mskCT16_MR3STOP_DIS (CT16_MR3STOP_DIS<<11) - -#define CT16_MR4IE_EN 1 //[12:12 Enable MR4 match interrupt -#define CT16_MR4IE_DIS 0 -#define mskCT16_MR4IE_EN (CT16_MR4IE_EN<<12) -#define mskCT16_MR4IE_DIS (CT16_MR4IE_DIS<<12) - -#define CT16_MR4RST_EN 1 //[13:13] Enable reset TC when MR4 matches TC. -#define CT16_MR4RST_DIS 0 -#define mskCT16_MR4RST_EN (CT16_MR4RST_EN<<13) -#define mskCT16_MR4RST_DIS (CT16_MR4RST_DIS<<13) - -#define CT16_MR4STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR4 matches TC. -#define CT16_MR4STOP_DIS 0 -#define mskCT16_MR4STOP_EN (CT16_MR4STOP_EN<<14) -#define mskCT16_MR4STOP_DIS (CT16_MR4STOP_DIS<<14) - -#define CT16_MR5IE_EN 1 //[15:15] Enable MR5 match interrupt -#define CT16_MR5IE_DIS 0 -#define mskCT16_MR5IE_EN (CT16_MR5IE_EN<<15) -#define mskCT16_MR5IE_DIS (CT16_MR5IE_DIS<<15) - -#define CT16_MR5RST_EN 1 //[16:16] Enable reset TC when MR5 matches TC. -#define CT16_MR5RST_DIS 0 -#define mskCT16_MR5RST_EN (CT16_MR5RST_EN<<16) -#define mskCT16_MR5RST_DIS (CT16_MR5RST_DIS<<16) - -#define CT16_MR5STOP_EN 1 //[17:17] Enable stop TC and clear CEN when MR5 matches TC. -#define CT16_MR5STOP_DIS 0 -#define mskCT16_MR5STOP_EN (CT16_MR5STOP_EN<<17) -#define mskCT16_MR5STOP_DIS (CT16_MR5STOP_DIS<<17) - -#define CT16_MR6IE_EN 1 //[18:18 Enable MR6 match interrupt -#define CT16_MR6IE_DIS 0 -#define mskCT16_MR6IE_EN (CT16_MR6IE_EN<<18) -#define mskCT16_MR6IE_DIS (CT16_MR6IE_DIS<<18) - -#define CT16_MR6RST_EN 1 //[19:19] Enable reset TC when MR6 matches TC. -#define CT16_MR6RST_DIS 0 -#define mskCT16_MR6RST_EN (CT16_MR6RST_EN<<19) -#define mskCT16_MR6RST_DIS (CT16_MR6RST_DIS<<19) - -#define CT16_MR6STOP_EN 1 //[20:20] Enable stop TC and clear CEN when MR6 matches TC. -#define CT16_MR6STOP_DIS 0 -#define mskCT16_MR6STOP_EN (CT16_MR6STOP_EN<<20) -#define mskCT16_MR6STOP_DIS (CT16_MR6STOP_DIS<<20) - -#define CT16_MR7IE_EN 1 //[21:21 Enable MR7 match interrupt -#define CT16_MR7IE_DIS 0 -#define mskCT16_MR7IE_EN (CT16_MR7IE_EN<<21) -#define mskCT16_MR7IE_DIS (CT16_MR7IE_DIS<<21) - -#define CT16_MR7RST_EN 1 //[22:22] Enable reset TC when MR7 matches TC. -#define CT16_MR7RST_DIS 0 -#define mskCT16_MR7RST_EN (CT16_MR7RST_EN<<22) -#define mskCT16_MR7RST_DIS (CT16_MR7RST_DIS<<22) - -#define CT16_MR7STOP_EN 1 //[23:23] Enable stop TC and clear CEN when MR7 matches TC. -#define CT16_MR7STOP_DIS 0 -#define mskCT16_MR7STOP_EN (CT16_MR7STOP_EN<<23) -#define mskCT16_MR7STOP_DIS (CT16_MR7STOP_DIS<<23) - -#define CT16_MR8IE_EN 1 //[24:24 Enable MR8 match interrupt -#define CT16_MR8IE_DIS 0 -#define mskCT16_MR8IE_EN (CT16_MR8IE_EN<<24) -#define mskCT16_MR8IE_DIS (CT16_MR8IE_DIS<<24) - -#define CT16_MR8RST_EN 1 //[25:25] Enable reset TC when MR8 matches TC. -#define CT16_MR8RST_DIS 0 -#define mskCT16_MR8RST_EN (CT16_MR8RST_EN<<25) -#define mskCT16_MR8RST_DIS (CT16_MR8RST_DIS<<25) - -#define CT16_MR8STOP_EN 1 //[26:26] Enable stop TC and clear CEN when MR8 matches TC. -#define CT16_MR8STOP_DIS 0 -#define mskCT16_MR8STOP_EN (CT16_MR8STOP_EN<<26) -#define mskCT16_MR8STOP_DIS (CT16_MR8STOP_DIS<<26) - -#define CT16_MR9IE_EN 1 //[27:27] Enable MR9 match interrupt -#define CT16_MR9IE_DIS 0 -#define mskCT16_MR9IE_EN (CT16_MR9IE_EN<<27) -#define mskCT16_MR9IE_DIS (CT16_MR9IE_DIS<<27) - -#define CT16_MR9RST_EN 1 //[28:28] Enable reset TC when MR9 matches TC. -#define CT16_MR9RST_DIS 0 -#define mskCT16_MR9RST_EN (CT16_MR9RST_EN<<28) -#define mskCT16_MR9RST_DIS (CT16_MR9RST_DIS<<28) - -#define CT16_MR9STOP_EN 1 //[29:29] Enable stop TC and clear CEN when MR9 matches TC. -#define CT16_MR9STOP_DIS 0 -#define mskCT16_MR9STOP_EN (CT16_MR9STOP_EN<<29) -#define mskCT16_MR9STOP_DIS (CT16_MR9STOP_DIS<<29) - -/* CT16Bn Match Control register 2 (0x18) */ -#define CT16_MR10IE_EN 1 //[0:0] Enable MR10 match interrupt -#define CT16_MR10IE_DIS 0 -#define mskCT16_MR10IE_EN (CT16_MR10IE_EN<<0) -#define mskCT16_MR10IE_DIS (CT16_MR10IE_DIS<<0) - -#define CT16_MR10RST_EN 1 //[1:1] Enable reset TC when MR10 matches TC. -#define CT16_MR10RST_DIS 0 -#define mskCT16_MR10RST_EN (CT16_MR10RST_EN<<1) -#define mskCT16_MR10RST_DIS (CT16_MR10RST_DIS<<1) - -#define CT16_MR10STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR10 matches TC. -#define CT16_MR10STOP_DIS 0 -#define mskCT16_MR10STOP_EN (CT16_MR10STOP_EN<<2) -#define mskCT16_MR10STOP_DIS (CT16_MR10STOP_DIS<<2) - -#define CT16_MR11IE_EN 1 //[3:3] Enable MR11 match interrupt -#define CT16_MR11IE_DIS 0 -#define mskCT16_MR11IE_EN (CT16_MR11IE_EN<<3) -#define mskCT16_MR11IE_DIS (CT16_MR11IE_DIS<<3) - -#define CT16_MR11RST_EN 1 //[4:4] Enable reset TC when MR11 matches TC. -#define CT16_MR11RST_DIS 0 -#define mskCT16_MR11RST_EN (CT16_MR11RST_EN<<4) -#define mskCT16_MR11RST_DIS (CT16_MR11RST_DIS<<4) - -#define CT16_MR11STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR11 matches TC. -#define CT16_MR11STOP_DIS 0 -#define mskCT16_MR11STOP_EN (CT16_MR11STOP_EN<<5) -#define mskCT16_MR11STOP_DIS (CT16_MR11STOP_DIS<<5) - -#define CT16_MR12IE_EN 1 //[6:6] Enable MR12 match interrupt -#define CT16_MR12IE_DIS 0 -#define mskCT16_MR12IE_EN (CT16_MR12IE_EN<<6) -#define mskCT16_MR12IE_DIS (CT16_MR12IE_DIS<<6) - -#define CT16_MR12RST_EN 1 //[7:7] Enable reset TC when MR12 matches TC. -#define CT16_MR12RST_DIS 0 -#define mskCT16_MR12RST_EN (CT16_MR12RST_EN<<7) -#define mskCT16_MR12RST_DIS (CT16_MR12RST_DIS<<7) - -#define CT16_MR12STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR12 matches TC. -#define CT16_MR12STOP_DIS 0 -#define mskCT16_MR12STOP_EN (CT16_MR12STOP_EN<<8) -#define mskCT16_MR12STOP_DIS (CT16_MR12STOP_DIS<<8) - -#define CT16_MR13IE_EN 1 //[9:9] Enable MR13 match interrupt -#define CT16_MR13IE_DIS 0 -#define mskCT16_MR13IE_EN (CT16_MR13IE_EN<<9) -#define mskCT16_MR13IE_DIS (CT16_MR13IE_DIS<<9) - -#define CT16_MR13RST_EN 1 //[10:10] Enable reset TC when MR13 matches TC. -#define CT16_MR13RST_DIS 0 -#define mskCT16_MR13RST_EN (CT16_MR13RST_EN<<10) -#define mskCT16_MR13RST_DIS (CT16_MR13RST_DIS<<10) - -#define CT16_MR13STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR13 matches TC. -#define CT16_MR13STOP_DIS 0 -#define mskCT16_MR13STOP_EN (CT16_MR13STOP_EN<<11) -#define mskCT16_MR13STOP_DIS (CT16_MR13STOP_DIS<<11) - -#define CT16_MR14IE_EN 1 //[12:12 Enable MR14 match interrupt -#define CT16_MR14IE_DIS 0 -#define mskCT16_MR14IE_EN (CT16_MR14IE_EN<<12) -#define mskCT16_MR14IE_DIS (CT16_MR14IE_DIS<<12) - -#define CT16_MR14RST_EN 1 //[13:13] Enable reset TC when MR14 matches TC. -#define CT16_MR14RST_DIS 0 -#define mskCT16_MR14RST_EN (CT16_MR14RST_EN<<13) -#define mskCT16_MR14RST_DIS (CT16_MR14RST_DIS<<13) - -#define CT16_MR14STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR14 matches TC. -#define CT16_MR14STOP_DIS 0 -#define mskCT16_MR14STOP_EN (CT16_MR14STOP_EN<<14) -#define mskCT16_MR14STOP_DIS (CT16_MR14STOP_DIS<<14) - -#define CT16_MR15IE_EN 1 //[15:15 Enable MR15 match interrupt -#define CT16_MR15IE_DIS 0 -#define mskCT16_MR15IE_EN (CT16_MR15IE_EN<<15) -#define mskCT16_MR15IE_DIS (CT16_MR15IE_DIS<<15) - -#define CT16_MR15RST_EN 1 //[16:16] Enable reset TC when MR15 matches TC. -#define CT16_MR15RST_DIS 0 -#define mskCT16_MR15RST_EN (CT16_MR15RST_EN<<16) -#define mskCT16_MR15RST_DIS (CT16_MR15RST_DIS<<16) - -#define CT16_MR15STOP_EN 1 //[17:17] Enable stop TC and clear CEN when MR15 matches TC. -#define CT16_MR15STOP_DIS 0 -#define mskCT16_MR15STOP_EN (CT16_MR15STOP_EN<<17) -#define mskCT16_MR15STOP_DIS (CT16_MR15STOP_DIS<<17) - -#define CT16_MR16IE_EN 1 //[18:18 Enable MR16 match interrupt -#define CT16_MR16IE_DIS 0 -#define mskCT16_MR16IE_EN (CT16_MR16IE_EN<<18) -#define mskCT16_MR16IE_DIS (CT16_MR16IE_DIS<<18) - -#define CT16_MR16RST_EN 1 //[19:19] Enable reset TC when MR16 matches TC. -#define CT16_MR16RST_DIS 0 -#define mskCT16_MR16RST_EN (CT16_MR16RST_EN<<19) -#define mskCT16_MR16RST_DIS (CT16_MR16RST_DIS<<19) - -#define CT16_MR16STOP_EN 1 //[20:20] Enable stop TC and clear CEN when MR16 matches TC. -#define CT16_MR16STOP_DIS 0 -#define mskCT16_MR16STOP_EN (CT16_MR16STOP_EN<<20) -#define mskCT16_MR16STOP_DIS (CT16_MR16STOP_DIS<<20) - -#define CT16_MR17IE_EN 1 //[21:21 Enable MR17 match interrupt -#define CT16_MR17IE_DIS 0 -#define mskCT16_MR17IE_EN (CT16_MR17IE_EN<<21) -#define mskCT16_MR17IE_DIS (CT16_MR17IE_DIS<<21) - -#define CT16_MR17RST_EN 1 //[22:22] Enable reset TC when MR17 matches TC. -#define CT16_MR17RST_DIS 0 -#define mskCT16_MR17RST_EN (CT16_MR17RST_EN<<22) -#define mskCT16_MR17RST_DIS (CT16_MR17RST_DIS<<22) - -#define CT16_MR17STOP_EN 1 //[23:23] Enable stop TC and clear CEN when MR17 matches TC. -#define CT16_MR17STOP_DIS 0 -#define mskCT16_MR17STOP_EN (CT16_MR17STOP_EN<<23) -#define mskCT16_MR17STOP_DIS (CT16_MR17STOP_DIS<<23) - -#define CT16_MR18IE_EN 1 //[24:24 Enable MR18 match interrupt -#define CT16_MR18IE_DIS 0 -#define mskCT16_MR18IE_EN (CT16_MR18IE_EN<<24) -#define mskCT16_MR18IE_DIS (CT16_MR18IE_DIS<<24) - -#define CT16_MR18RST_EN 1 //[25:25] Enable reset TC when MR18 matches TC. -#define CT16_MR18RST_DIS 0 -#define mskCT16_MR18RST_EN (CT16_MR18RST_EN<<25) -#define mskCT16_MR18RST_DIS (CT16_MR18RST_DIS<<25) - -#define CT16_MR18STOP_EN 1 //[26:26] Enable stop TC and clear CEN when MR18 matches TC. -#define CT16_MR18STOP_DIS 0 -#define mskCT16_MR18STOP_EN (CT16_MR18STOP_EN<<26) -#define mskCT16_MR18STOP_DIS (CT16_MR18STOP_DIS<<26) - -#define CT16_MR19IE_EN 1 //[27:27] Enable MR19 match interrupt -#define CT16_MR19IE_DIS 0 -#define mskCT16_MR19IE_EN (CT16_MR19IE_EN<<27) -#define mskCT16_MR19IE_DIS (CT16_MR19IE_DIS<<27) - -#define CT16_MR19RST_EN 1 //[28:28] Enable reset TC when MR19 matches TC. -#define CT16_MR19RST_DIS 0 -#define mskCT16_MR19RST_EN (CT16_MR19RST_EN<<28) -#define mskCT16_MR19RST_DIS (CT16_MR19RST_DIS<<28) - -#define CT16_MR19STOP_EN 1 //[29:29] Enable stop TC and clear CEN when MR19 matches TC. -#define CT16_MR19STOP_DIS 0 -#define mskCT16_MR19STOP_EN (CT16_MR19STOP_EN<<29) -#define mskCT16_MR19STOP_DIS (CT16_MR19STOP_DIS<<29) - -/* CT16Bn Match Control register 3 (0x1C) */ -#define CT16_MR20IE_EN 1 //[0:0] Enable MR20 match interrupt -#define CT16_MR20IE_DIS 0 -#define mskCT16_MR20IE_EN (CT16_MR20IE_EN<<0) -#define mskCT16_MR20IE_DIS (CT16_MR20IE_DIS<<0) - -#define CT16_MR20RST_EN 1 //[1:1] Enable reset TC when MR20 matches TC. -#define CT16_MR20RST_DIS 0 -#define mskCT16_MR20RST_EN (CT16_MR20RST_EN<<1) -#define mskCT16_MR20RST_DIS (CT16_MR20RST_DIS<<1) - -#define CT16_MR20STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR20 matches TC. -#define CT16_MR20STOP_DIS 0 -#define mskCT16_MR20STOP_EN (CT16_MR20STOP_EN<<2) -#define mskCT16_MR20STOP_DIS (CT16_MR20STOP_DIS<<2) - -#define CT16_MR21IE_EN 1 //[3:3] Enable MR21 match interrupt -#define CT16_MR21IE_DIS 0 -#define mskCT16_MR21IE_EN (CT16_MR21IE_EN<<3) -#define mskCT16_MR21IE_DIS (CT16_MR21IE_DIS<<3) - -#define CT16_MR21RST_EN 1 //[4:4] Enable reset TC when MR21 matches TC. -#define CT16_MR21RST_DIS 0 -#define mskCT16_MR21RST_EN (CT16_MR21RST_EN<<4) -#define mskCT16_MR21RST_DIS (CT16_MR21RST_DIS<<4) - -#define CT16_MR21STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR21 matches TC. -#define CT16_MR21STOP_DIS 0 -#define mskCT16_MR21STOP_EN (CT16_MR21STOP_EN<<5) -#define mskCT16_MR21STOP_DIS (CT16_MR21STOP_DIS<<5) - -#define CT16_MR22IE_EN 1 //[6:6] Enable MR22 match interrupt -#define CT16_MR22IE_DIS 0 -#define mskCT16_MR22IE_EN (CT16_MR22IE_EN<<6) -#define mskCT16_MR22IE_DIS (CT16_MR22IE_DIS<<6) - -#define CT16_MR22RST_EN 1 //[7:7] Enable reset TC when MR22 matches TC. -#define CT16_MR22RST_DIS 0 -#define mskCT16_MR22RST_EN (CT16_MR22RST_EN<<7) -#define mskCT16_MR22RST_DIS (CT16_MR22RST_DIS<<7) - -#define CT16_MR22STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR22 matches TC. -#define CT16_MR22STOP_DIS 0 -#define mskCT16_MR22STOP_EN (CT16_MR22STOP_EN<<8) -#define mskCT16_MR22STOP_DIS (CT16_MR22STOP_DIS<<8) - -#define CT16_MR23IE_EN 1 //[9:9] Enable MR23 match interrupt -#define CT16_MR23IE_DIS 0 -#define mskCT16_MR23IE_EN (CT16_MR23IE_EN<<9) -#define mskCT16_MR23IE_DIS (CT16_MR23IE_DIS<<9) - -#define CT16_MR23RST_EN 1 //[10:10] Enable reset TC when MR23 matches TC. -#define CT16_MR23RST_DIS 0 -#define mskCT16_MR23RST_EN (CT16_MR23RST_EN<<10) -#define mskCT16_MR23RST_DIS (CT16_MR23RST_DIS<<10) - -#define CT16_MR23STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR23 matches TC. -#define CT16_MR23STOP_DIS 0 -#define mskCT16_MR23STOP_EN (CT16_MR23STOP_EN<<11) -#define mskCT16_MR23STOP_DIS (CT16_MR23STOP_DIS<<11) - -#define CT16_MR24IE_EN 1 //[12:12] Enable MR24 match interrupt -#define CT16_MR24IE_DIS 0 -#define mskCT16_MR24IE_EN (CT16_MR24IE_EN<<12) -#define mskCT16_MR24IE_DIS (CT16_MR24IE_DIS<<12) - -#define CT16_MR24RST_EN 1 //[13:13] Enable reset TC when MR24 matches TC. -#define CT16_MR24RST_DIS 0 -#define mskCT16_MR24RST_EN (CT16_MR24RST_EN<<13) -#define mskCT16_MR24RST_DIS (CT16_MR24RST_DIS<<13) - -#define CT16_MR24STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR24 matches TC. -#define CT16_MR24STOP_DIS 0 -#define mskCT16_MR24STOP_EN (CT16_MR24STOP_EN<<14) -#define mskCT16_MR24STOP_DIS (CT16_MR24STOP_DIS<<14) - -/* CT16Bn Capture Control register (0x80) */ -#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. -#define CT16_CAP0RE_DIS 0 -#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0) -#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0) - -#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. -#define CT16_CAP0FE_DIS 0 -#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1) -#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1) - -#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. -#define CT16_CAP0IE_DIS 0 -#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2) -#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2) - -#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function. -#define CT16_CAP0EN_DIS 0 -#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3) -#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3) - -/* CT16Bn External Match register (0x88) */ -#define CT16_EM0 1 //[0:0] CT16Bn PWM0 drive state -#define mskCT16_EM0 (CT16_EM0<<0) -#define CT16_EM1 1 //[1:1] CT16Bn PWM1 drive state -#define mskCT16_EM1 (CT16_EM1<<1) -#define CT16_EM2 1 //[2:2] CT16Bn PWM2 drive state -#define mskCT16_EM2 (CT16_EM2<<2) -#define CT16_EM3 1 //[3:3] CT16Bn PWM3 drive state -#define mskCT16_EM3 (CT16_EM3<<3) -#define CT16_EM4 1 //[4:4] CT16Bn PWM4 drive state -#define mskCT16_EM4 (CT16_EM4<<4) -#define CT16_EM5 1 //[5:5] CT16Bn PWM5 drive state -#define mskCT16_EM5 (CT16_EM5<<5) -#define CT16_EM6 1 //[6:6] CT16Bn PWM6 drive state -#define mskCT16_EM6 (CT16_EM6<<6) -#define CT16_EM7 1 //[7:7] CT16Bn PWM7 drive state -#define mskCT16_EM7 (CT16_EM7<<7) -#define CT16_EM8 1 //[8:8] CT16Bn PWM8 drive state -#define mskCT16_EM8 (CT16_EM8<<8) -#define CT16_EM9 1 //[9:9] CT16Bn PWM9 drive state -#define mskCT16_EM9 (CT16_EM9<<9) -#define CT16_EM10 1 //[10:10] CT16Bn PWM10 drive state -#define mskCT16_EM10 (CT16_EM0<<10) -#define CT16_EM11 1 //[11:11] CT16Bn PWM11 drive state -#define mskCT16_EM11 (CT16_EM11<<11) -#define CT16_EM12 1 //[12:12] CT16Bn PWM12 drive state -#define mskCT16_EM12 (CT16_EM12<<12) -#define CT16_EM13 1 //[13:13] CT16Bn PWM13 drive state -#define mskCT16_EM13 (CT16_EM13<<13) -#define CT16_EM14 1 //[14:14] CT16Bn PWM14 drive state -#define mskCT16_EM14 (CT16_EM14<<14) -#define CT16_EM15 1 //[15:15] CT16Bn PWM15 drive state -#define mskCT16_EM15 (CT16_EM15<<15) -#define CT16_EM16 1 //[16:16] CT16Bn PWM16 drive state -#define mskCT16_EM16 (CT16_EM16<<16) -#define CT16_EM17 1 //[17:17] CT16Bn PWM17 drive state -#define mskCT16_EM17 (CT16_EM17<<17) -#define CT16_EM18 1 //[18:18] CT16Bn PWM18 drive state -#define mskCT16_EM18 (CT16_EM18<<8) -#define CT16_EM19 1 //[19:19] CT16Bn PWM19 drive state -#define mskCT16_EM19 (CT16_EM19<<19) -#define CT16_EM20 1 //[20:20] CT16Bn PWM20 drive state -#define mskCT16_EM20 (CT16_EM20<<20) -#define CT16_EM21 1 //[21:21] CT16Bn PWM21 drive state -#define mskCT16_EM21 (CT16_EM21<<21) -#define CT16_EM22 1 //[22:22] CT16Bn PWM22 drive state -#define mskCT16_EM22 (CT16_EM22<<22) -#define CT16_EM23 1 //[23:23] CT16Bn PWM23 drive state -#define mskCT16_EM23 (CT16_EM23<<23) - -/* CT16Bn External Match Control register (0x8C) */ - //[1:0]CT16Bn PWM0 functionality -#define CT16_EMC0_DO_NOTHING 0 //Do nothing. -#define CT16_EMC0_LOW 1 //CT16Bn PWM0 pin is low. -#define CT16_EMC0_HIGH 2 //CT16Bn PWM0 pin is high. -#define CT16_EMC0_TOGGLE 3 //Toggle CT16Bn PWM0 pin. -#define mskCT16_EMC0_DO_NOTHING (CT16_EMC0_LOW<<0) -#define mskCT16_EMC0_LOW (CT16_EMC0_LOW<<0) -#define mskCT16_EMC0_HIGH (CT16_EMC0_HIGH<<0) -#define mskCT16_EMC0_TOGGLE (CT16_EMC0_TOGGLE<<0) - - //[3:2]CT16Bn PWM1 functionality -#define CT16_EMC1_DO_NOTHING 0 //Do nothing. -#define CT16_EMC1_LOW 1 //CT16Bn PWM1 pin is low. -#define CT16_EMC1_HIGH 2 //CT16Bn PWM1 pin is high. -#define CT16_EMC1_TOGGLE 3 //Toggle CT16Bn PWM1 pin. -#define mskCT16_EMC1_DO_NOTHING (CT16_EMC1_LOW<<2) -#define mskCT16_EMC1_LOW (CT16_EMC1_LOW<<2) -#define mskCT16_EMC1_HIGH (CT16_EMC1_HIGH<<2) -#define mskCT16_EMC1_TOGGLE (CT16_EMC1_TOGGLE<<2) - - //[5:4]CT16Bn PWM2 functionality -#define CT16_EMC2_DO_NOTHING 0 //Do nothing. -#define CT16_EMC2_LOW 1 //CT16Bn PWM2 pin is low. -#define CT16_EMC2_HIGH 2 //CT16Bn PWM2 pin is high. -#define CT16_EMC2_TOGGLE 3 //Toggle CT16Bn PWM2 pin. -#define mskCT16_EMC2_DO_NOTHING (CT16_EMC2_LOW<<4) -#define mskCT16_EMC2_LOW (CT16_EMC2_LOW<<4) -#define mskCT16_EMC2_HIGH (CT16_EMC2_HIGH<<4) -#define mskCT16_EMC2_TOGGLE (CT16_EMC2_TOGGLE<<4) - - //[7:6]CT16Bn PWM3 functionality -#define CT16_EMC3_DO_NOTHING 0 //Do nothing. -#define CT16_EMC3_LOW 1 //CT16Bn PWM3 pin is low. -#define CT16_EMC3_HIGH 2 //CT16Bn PWM3 pin is high. -#define CT16_EMC3_TOGGLE 3 //Toggle CT16Bn PWM3 pin. -#define mskCT16_EMC3_DO_NOTHING (CT16_EMC3_LOW<<6) -#define mskCT16_EMC3_LOW (CT16_EMC3_LOW<<6) -#define mskCT16_EMC3_HIGH (CT16_EMC3_HIGH<<6) -#define mskCT16_EMC3_TOGGLE (CT16_EMC3_TOGGLE<<6) - - //[9:8]CT16Bn PWM4 functionality -#define CT16_EMC4_DO_NOTHING 0 //Do nothing. -#define CT16_EMC4_LOW 1 //CT16Bn PWM4 pin is low. -#define CT16_EMC4_HIGH 2 //CT16Bn PWM4 pin is high. -#define CT16_EMC4_TOGGLE 3 //Toggle CT16Bn PWM4 pin. -#define mskCT16_EMC4_DO_NOTHING (CT16_EMC4_LOW<<8) -#define mskCT16_EMC4_LOW (CT16_EMC4_LOW<<8) -#define mskCT16_EMC4_HIGH (CT16_EMC4_HIGH<<8) -#define mskCT16_EMC4_TOGGLE (CT16_EMC4_TOGGLE<<8) - - //[11:10]CT16Bn PWM5 functionality -#define CT16_EMC5_DO_NOTHING 0 //Do nothing. -#define CT16_EMC5_LOW 1 //CT16Bn PWM5 pin is low. -#define CT16_EMC5_HIGH 2 //CT16Bn PWM5 pin is high. -#define CT16_EMC5_TOGGLE 3 //Toggle CT16Bn PWM5 pin. -#define mskCT16_EMC5_DO_NOTHING (CT16_EMC5_LOW<<10) -#define mskCT16_EMC5_LOW (CT16_EMC5_LOW<<10) -#define mskCT16_EMC5_HIGH (CT16_EMC5_HIGH<<10) -#define mskCT16_EMC5_TOGGLE (CT16_EMC5_TOGGLE<<10) - - //[13:12]CT16Bn PWM6 functionality -#define CT16_EMC6_DO_NOTHING 0 //Do nothing. -#define CT16_EMC6_LOW 1 //CT16Bn PWM6 pin is low. -#define CT16_EMC6_HIGH 2 //CT16Bn PWM6 pin is high. -#define CT16_EMC6_TOGGLE 3 //Toggle CT16Bn PWM6 pin. -#define mskCT16_EMC6_DO_NOTHING (CT16_EMC6_LOW<<12) -#define mskCT16_EMC6_LOW (CT16_EMC6_LOW<<12) -#define mskCT16_EMC6_HIGH (CT16_EMC6_HIGH<<12) -#define mskCT16_EMC6_TOGGLE (CT16_EMC6_TOGGLE<<12) - - //[15:14]CT16Bn PWM7 functionality -#define CT16_EMC7_DO_NOTHING 0 //Do nothing. -#define CT16_EMC7_LOW 1 //CT16Bn PWM7 pin is low. -#define CT16_EMC7_HIGH 2 //CT16Bn PWM7 pin is high. -#define CT16_EMC7_TOGGLE 3 //Toggle CT16Bn PWM7 pin. -#define mskCT16_EMC7_DO_NOTHING (CT16_EMC7_LOW<<14) -#define mskCT16_EMC7_LOW (CT16_EMC7_LOW<<14) -#define mskCT16_EMC7_HIGH (CT16_EMC7_HIGH<<14) -#define mskCT16_EMC7_TOGGLE (CT16_EMC7_TOGGLE<<14) - - //[17:16]CT16Bn PWM8 functionality -#define CT16_EMC8_DO_NOTHING 0 //Do nothing. -#define CT16_EMC8_LOW 1 //CT16Bn PWM8 pin is low. -#define CT16_EMC8_HIGH 2 //CT16Bn PWM8 pin is high. -#define CT16_EMC8_TOGGLE 3 //Toggle CT16Bn PWM8 pin. -#define mskCT16_EMC8_DO_NOTHING (CT16_EMC8_LOW<<16) -#define mskCT16_EMC8_LOW (CT16_EMC8_LOW<<16) -#define mskCT16_EMC8_HIGH (CT16_EMC8_HIGH<<16) -#define mskCT16_EMC8_TOGGLE (CT16_EMC8_TOGGLE<<16) - - //[19:18]CT16Bn PWM9 functionality -#define CT16_EMC9_DO_NOTHING 0 //Do nothing. -#define CT16_EMC9_LOW 1 //CT16Bn PWM9 pin is low. -#define CT16_EMC9_HIGH 2 //CT16Bn PWM9 pin is high. -#define CT16_EMC9_TOGGLE 3 //Toggle CT16Bn PWM9 pin. -#define mskCT16_EMC9_DO_NOTHING (CT16_EMC9_LOW<<18) -#define mskCT16_EMC9_LOW (CT16_EMC9_LOW<<18) -#define mskCT16_EMC9_HIGH (CT16_EMC9_HIGH<<18) -#define mskCT16_EMC9_TOGGLE (CT16_EMC9_TOGGLE<<18) - - //[21:20]CT16Bn PWM10 functionality -#define CT16_EMC10_DO_NOTHING 0 //Do nothing. -#define CT16_EMC10_LOW 1 //CT16Bn PWM10 pin is low. -#define CT16_EMC10_HIGH 2 //CT16Bn PWM10 pin is high. -#define CT16_EMC10_TOGGLE 3 //Toggle CT16Bn PWM10 pin. -#define mskCT16_EMC10_DO_NOTHING (CT16_EMC10_LOW<<20) -#define mskCT16_EMC10_LOW (CT16_EMC10_LOW<<20) -#define mskCT16_EMC10_HIGH (CT16_EMC10_HIGH<<20) -#define mskCT16_EMC10_TOGGLE (CT16_EMC10_TOGGLE<<20) - - //[23:22]CT16Bn PWM11 functionality -#define CT16_EMC11_DO_NOTHING 0 //Do nothing. -#define CT16_EMC11_LOW 1 //CT16Bn PWM11 pin is low. -#define CT16_EMC11_HIGH 2 //CT16Bn PWM11 pin is high. -#define CT16_EMC11_TOGGLE 3 //Toggle CT16Bn PWM11 pin. -#define mskCT16_EMC11_DO_NOTHING (CT16_EMC11_LOW<<22) -#define mskCT16_EMC11_LOW (CT16_EMC11_LOW<<22) -#define mskCT16_EMC11_HIGH (CT16_EMC11_HIGH<<22) -#define mskCT16_EMC11_TOGGLE (CT16_EMC11_TOGGLE<<22) - - //[25:24]CT16Bn PWM12 functionality -#define CT16_EMC12_DO_NOTHING 0 //Do nothing. -#define CT16_EMC12_LOW 1 //CT16Bn PWM12 pin is low. -#define CT16_EMC12_HIGH 2 //CT16Bn PWM12 pin is high. -#define CT16_EMC12_TOGGLE 3 //Toggle CT16Bn PWM12 pin. -#define mskCT16_EMC12_DO_NOTHING (CT16_EMC12_LOW<<24) -#define mskCT16_EMC12_LOW (CT16_EMC12_LOW<<24) -#define mskCT16_EMC12_HIGH (CT16_EMC12_HIGH<<24) -#define mskCT16_EMC12_TOGGLE (CT16_EMC12_TOGGLE<<24) - - //[27:26]CT16Bn PWM13 functionality -#define CT16_EMC13_DO_NOTHING 0 //Do nothing. -#define CT16_EMC13_LOW 1 //CT16Bn PWM13 pin is low. -#define CT16_EMC13_HIGH 2 //CT16Bn PWM13 pin is high. -#define CT16_EMC13_TOGGLE 3 //Toggle CT16Bn PWM13 pin. -#define mskCT16_EMC13_DO_NOTHING (CT16_EMC13_LOW<<26) -#define mskCT16_EMC13_LOW (CT16_EMC13_LOW<<26) -#define mskCT16_EMC13_HIGH (CT16_EMC13_HIGH<<26) -#define mskCT16_EMC13_TOGGLE (CT16_EMC13_TOGGLE<<26) - - //[29:28]CT16Bn PWM14 functionality -#define CT16_EMC14_DO_NOTHING 0 //Do nothing. -#define CT16_EMC14_LOW 1 //CT16Bn PWM14 pin is low. -#define CT16_EMC14_HIGH 2 //CT16Bn PWM14 pin is high. -#define CT16_EMC14_TOGGLE 3 //Toggle CT16Bn PWM14 pin. -#define mskCT16_EMC14_DO_NOTHING (CT16_EMC14_LOW<<28) -#define mskCT16_EMC14_LOW (CT16_EMC14_LOW<<28) -#define mskCT16_EMC14_HIGH (CT16_EMC14_HIGH<<28) -#define mskCT16_EMC14_TOGGLE (CT16_EMC14_TOGGLE<<28) - - //[31:30]CT16Bn PWM15 functionality -#define CT16_EMC15_DO_NOTHING 0 //Do nothing. -#define CT16_EMC15_LOW 1 //CT16Bn PWM15 pin is low. -#define CT16_EMC15_HIGH 2 //CT16Bn PWM15 pin is high. -#define CT16_EMC15_TOGGLE 3 //Toggle CT16Bn PWM15 pin. -#define mskCT16_EMC15_DO_NOTHING (CT16_EMC15_LOW<<30) -#define mskCT16_EMC15_LOW (CT16_EMC15_LOW<<30) -#define mskCT16_EMC15_HIGH (CT16_EMC15_HIGH<<30) -#define mskCT16_EMC15_TOGGLE (CT16_EMC15_TOGGLE<<30) - -/* CT16Bn External Match Control register2 (0x90) */ - //[1:0]CT16Bn PWM16 functionality -#define CT16_EMC16_DO_NOTHING 0 //Do nothing. -#define CT16_EMC16_LOW 1 //CT16Bn PWM16 pin is low. -#define CT16_EMC16_HIGH 2 //CT16Bn PWM16 pin is high. -#define CT16_EMC16_TOGGLE 3 //Toggle CT16Bn PWM16 pin. -#define mskCT16_EMC16_DO_NOTHING (CT16_EMC16_LOW<<0) -#define mskCT16_EMC16_LOW (CT16_EMC16_LOW<<0) -#define mskCT16_EMC16_HIGH (CT16_EMC16_HIGH<<0) -#define mskCT16_EMC16_TOGGLE (CT16_EMC16_TOGGLE<<0) - - //[3:2]CT16Bn PWM17 functionality -#define CT16_EMC17_DO_NOTHING 0 //Do nothing. -#define CT16_EMC17_LOW 1 //CT16Bn PWM17 pin is low. -#define CT16_EMC17_HIGH 2 //CT16Bn PWM17 pin is high. -#define CT16_EMC17_TOGGLE 3 //Toggle CT16Bn PWM17 pin. -#define mskCT16_EMC17_DO_NOTHING (CT16_EMC17_LOW<<2) -#define mskCT16_EMC17_LOW (CT16_EMC17_LOW<<2) -#define mskCT16_EMC17_HIGH (CT16_EMC17_HIGH<<2) -#define mskCT16_EMC17_TOGGLE (CT16_EMC17_TOGGLE<<2) - - //[5:4]CT16Bn PWM18 functionality -#define CT16_EMC18_DO_NOTHING 0 //Do nothing. -#define CT16_EMC18_LOW 1 //CT16Bn PWM18 pin is low. -#define CT16_EMC18_HIGH 2 //CT16Bn PWM18 pin is high. -#define CT16_EMC18_TOGGLE 3 //Toggle CT16Bn PWM18 pin. -#define mskCT16_EMC18_DO_NOTHING (CT16_EMC18_LOW<<4) -#define mskCT16_EMC18_LOW (CT16_EMC18_LOW<<4) -#define mskCT16_EMC18_HIGH (CT16_EMC18_HIGH<<4) -#define mskCT16_EMC18_TOGGLE (CT16_EMC18_TOGGLE<<4) - - //[7:6]CT16Bn PWM19 functionality -#define CT16_EMC19_DO_NOTHING 0 //Do nothing. -#define CT16_EMC19_LOW 1 //CT16Bn PWM19 pin is low. -#define CT16_EMC19_HIGH 2 //CT16Bn PWM19 pin is high. -#define CT16_EMC19_TOGGLE 3 //Toggle CT16Bn PWM19 pin. -#define mskCT16_EMC19_DO_NOTHING (CT16_EMC19_LOW<<6) -#define mskCT16_EMC19_LOW (CT16_EMC19_LOW<<6) -#define mskCT16_EMC19_HIGH (CT16_EMC19_HIGH<<6) -#define mskCT16_EMC19_TOGGLE (CT16_EMC19_TOGGLE<<6) - - //[9:8]CT16Bn PWM20 functionality -#define CT16_EMC20_DO_NOTHING 0 //Do nothing. -#define CT16_EMC20_LOW 1 //CT16Bn PWM20 pin is low. -#define CT16_EMC20_HIGH 2 //CT16Bn PWM20 pin is high. -#define CT16_EMC20_TOGGLE 3 //Toggle CT16Bn PWM20 pin. -#define mskCT16_EMC20_DO_NOTHING (CT16_EMC20_LOW<<8) -#define mskCT16_EMC20_LOW (CT16_EMC20_LOW<<8) -#define mskCT16_EMC20_HIGH (CT16_EMC20_HIGH<<8) -#define mskCT16_EMC20_TOGGLE (CT16_EMC20_TOGGLE<<8) - - //[11:10]CT16Bn PWM21 functionality -#define CT16_EMC21_DO_NOTHING 0 //Do nothing. -#define CT16_EMC21_LOW 1 //CT16Bn PWM21 pin is low. -#define CT16_EMC21_HIGH 2 //CT16Bn PWM21 pin is high. -#define CT16_EMC21_TOGGLE 3 //Toggle CT16Bn PWM21 pin. -#define mskCT16_EMC21_DO_NOTHING (CT16_EMC21_LOW<<10) -#define mskCT16_EMC21_LOW (CT16_EMC21_LOW<<10) -#define mskCT16_EMC21_HIGH (CT16_EMC21_HIGH<<10) -#define mskCT16_EMC21_TOGGLE (CT16_EMC21_TOGGLE<<10) - - //[13:12]CT16Bn PWM22 functionality -#define CT16_EMC22_DO_NOTHING 0 //Do nothing. -#define CT16_EMC22_LOW 1 //CT16Bn PWM22 pin is low. -#define CT16_EMC22_HIGH 2 //CT16Bn PWM22 pin is high. -#define CT16_EMC22_TOGGLE 3 //Toggle CT16Bn PWM22 pin. -#define mskCT16_EMC22_DO_NOTHING (CT16_EMC22_LOW<<12) -#define mskCT16_EMC22_LOW (CT16_EMC22_LOW<<12) -#define mskCT16_EMC22_HIGH (CT16_EMC22_HIGH<<12) -#define mskCT16_EMC22_TOGGLE (CT16_EMC22_TOGGLE<<12) - - //[15:14]CT16Bn PWM23 functionality -#define CT16_EMC23_DO_NOTHING 0 //Do nothing. -#define CT16_EMC23_LOW 1 //CT16Bn PWM23 pin is low. -#define CT16_EMC23_HIGH 2 //CT16Bn PWM23 pin is high. -#define CT16_EMC23_TOGGLE 3 //Toggle CT16Bn PWM23 pin. -#define mskCT16_EMC23_DO_NOTHING (CT16_EMC23_LOW<<14) -#define mskCT16_EMC23_LOW (CT16_EMC23_LOW<<14) -#define mskCT16_EMC23_HIGH (CT16_EMC23_HIGH<<14) -#define mskCT16_EMC23_TOGGLE (CT16_EMC23_TOGGLE<<14) - -/* CT16Bn PWM Control register (0x94) */ - //[1:0] CT16Bn PWM0 output mode. -#define CT16_PWM0MODE_1 0 // PWM mode 1. -#define CT16_PWM0MODE_2 1 // PWM mode 2. -#define CT16_PWM0MODE_FORCE_0 2 // Force 0. -#define CT16_PWM0MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM0MODE_1 (CT16_PWM0MODE_1<<0) -#define mskCT16_PWM0MODE_2 (CT16_PWM0MODE_2<<0) -#define mskCT16_PWM0MODE_FORCE_0 (CT16_PWM0MODE_FORCE_0<<0) -#define mskCT16_PWM0MODE_FORCE_1 (CT16_PWM0MODE_FORCE_1<<0) - - //[3:2] CT16Bn PWM1 output mode. -#define CT16_PWM1MODE_1 0 // PWM mode 1. -#define CT16_PWM1MODE_2 1 // PWM mode 2. -#define CT16_PWM1MODE_FORCE_0 2 // Force 0. -#define CT16_PWM1MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM1MODE_1 (CT16_PWM1MODE_1<<2) -#define mskCT16_PWM1MODE_2 (CT16_PWM1MODE_2<<2) -#define mskCT16_PWM1MODE_FORCE_0 (CT16_PWM1MODE_FORCE_0<<2) -#define mskCT16_PWM1MODE_FORCE_1 (CT16_PWM1MODE_FORCE_1<<2) - - //[5:4] CT16Bn PWM2 output mode. -#define CT16_PWM2MODE_1 0 // PWM mode 1. -#define CT16_PWM2MODE_2 1 // PWM mode 2. -#define CT16_PWM2MODE_FORCE_0 2 // Force 0. -#define CT16_PWM2MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM2MODE_1 (CT16_PWM2MODE_1<<4) -#define mskCT16_PWM2MODE_2 (CT16_PWM2MODE_2<<4) -#define mskCT16_PWM2MODE_FORCE_0 (CT16_PWM2MODE_FORCE_0<<4) -#define mskCT16_PWM2MODE_FORCE_1 (CT16_PWM2MODE_FORCE_1<<4) - - //[7:6] CT16Bn PWM3 output mode. -#define CT16_PWM3MODE_1 0 // PWM mode 1. -#define CT16_PWM3MODE_2 1 // PWM mode 2. -#define CT16_PWM3MODE_FORCE_0 2 // Force 0. -#define CT16_PWM3MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM3MODE_1 (CT16_PWM3MODE_1<<6) -#define mskCT16_PWM3MODE_2 (CT16_PWM3MODE_2<<6) -#define mskCT16_PWM3MODE_FORCE_0 (CT16_PWM3MODE_FORCE_0<<6) -#define mskCT16_PWM3MODE_FORCE_1 (CT16_PWM3MODE_FORCE_1<<6) - - //[9:8] CT16Bn PWM4 output mode. -#define CT16_PWM4MODE_1 0 // PWM mode 1. -#define CT16_PWM4MODE_2 1 // PWM mode 2. -#define CT16_PWM4MODE_FORCE_0 2 // Force 0. -#define CT16_PWM4MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM4MODE_1 (CT16_PWM4MODE_1<<8) -#define mskCT16_PWM4MODE_2 (CT16_PWM4MODE_2<<8) -#define mskCT16_PWM4MODE_FORCE_0 (CT16_PWM4MODE_FORCE_0<<8) -#define mskCT16_PWM4MODE_FORCE_1 (CT16_PWM4MODE_FORCE_1<<8) - - //[11:10] CT16Bn PWM5 output mode. -#define CT16_PWM5MODE_1 0 // PWM mode 1. -#define CT16_PWM5MODE_2 1 // PWM mode 2. -#define CT16_PWM5MODE_FORCE_0 2 // Force 0. -#define CT16_PWM5MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM5MODE_1 (CT16_PWM5MODE_1<<10) -#define mskCT16_PWM5MODE_2 (CT16_PWM5MODE_2<<10) -#define mskCT16_PWM5MODE_FORCE_0 (CT16_PWM5MODE_FORCE_0<<10) -#define mskCT16_PWM5MODE_FORCE_1 (CT16_PWM5MODE_FORCE_1<<10) - - //[13:12] CT16Bn PWM6 output mode. -#define CT16_PWM6MODE_1 0 // PWM mode 1. -#define CT16_PWM6MODE_2 1 // PWM mode 2. -#define CT16_PWM6MODE_FORCE_0 2 // Force 0. -#define CT16_PWM6MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM6MODE_1 (CT16_PWM6MODE_1<<12) -#define mskCT16_PWM6MODE_2 (CT16_PWM6MODE_2<<12) -#define mskCT16_PWM6MODE_FORCE_0 (CT16_PWM6MODE_FORCE_0<<12) -#define mskCT16_PWM6MODE_FORCE_1 (CT16_PWM6MODE_FORCE_1<<12) - - //[15:14] CT16Bn PWM7 output mode. -#define CT16_PWM7MODE_1 0 // PWM mode 1. -#define CT16_PWM7MODE_2 1 // PWM mode 2. -#define CT16_PWM7MODE_FORCE_0 2 // Force 0. -#define CT16_PWM7MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM7MODE_1 (CT16_PWM7MODE_1<<14) -#define mskCT16_PWM7MODE_2 (CT16_PWM7MODE_2<<14) -#define mskCT16_PWM7MODE_FORCE_0 (CT16_PWM7MODE_FORCE_0<<14) -#define mskCT16_PWM7MODE_FORCE_1 (CT16_PWM7MODE_FORCE_1<<14) - - //[17:16] CT16Bn PWM8 output mode. -#define CT16_PWM8MODE_1 0 // PWM mode 1. -#define CT16_PWM8MODE_2 1 // PWM mode 2. -#define CT16_PWM8MODE_FORCE_0 2 // Force 0. -#define CT16_PWM8MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM8MODE_1 (CT16_PWM8MODE_1<<16) -#define mskCT16_PWM8MODE_2 (CT16_PWM8MODE_2<<16) -#define mskCT16_PWM8MODE_FORCE_0 (CT16_PWM8MODE_FORCE_0<<16) -#define mskCT16_PWM8MODE_FORCE_1 (CT16_PWM8MODE_FORCE_1<<16) - - //[19:18] CT16Bn PWM9 output mode. -#define CT16_PWM9MODE_1 0 // PWM mode 1. -#define CT16_PWM9MODE_2 1 // PWM mode 2. -#define CT16_PWM9MODE_FORCE_0 2 // Force 0. -#define CT16_PWM9MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM9MODE_1 (CT16_PWM9MODE_1<<18) -#define mskCT16_PWM9MODE_2 (CT16_PWM9MODE_2<<18) -#define mskCT16_PWM9MODE_FORCE_0 (CT16_PWM9MODE_FORCE_0<<18) -#define mskCT16_PWM9MODE_FORCE_1 (CT16_PWM9MODE_FORCE_1<<18) - - //[21:20] CT16Bn PWM10 output mode. -#define CT16_PWM10MODE_1 0 // PWM mode 1. -#define CT16_PWM10MODE_2 1 // PWM mode 2. -#define CT16_PWM10MODE_FORCE_0 2 // Force 0. -#define CT16_PWM10MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM10MODE_1 (CT16_PWM10MODE_1<<20) -#define mskCT16_PWM10MODE_2 (CT16_PWM10MODE_2<<20) -#define mskCT16_PWM10MODE_FORCE_0 (CT16_PWM10MODE_FORCE_0<<20) -#define mskCT16_PWM10MODE_FORCE_1 (CT16_PWM10MODE_FORCE_1<<20) - - //[23:22] CT16Bn PWM11 output mode. -#define CT16_PWM11MODE_1 0 // PWM mode 1. -#define CT16_PWM11MODE_2 1 // PWM mode 2. -#define CT16_PWM11MODE_FORCE_0 2 // Force 0. -#define CT16_PWM11MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM11MODE_1 (CT16_PWM11MODE_1<<22) -#define mskCT16_PWM11MODE_2 (CT16_PWM11MODE_2<<22) -#define mskCT16_PWM11MODE_FORCE_0 (CT16_PWM11MODE_FORCE_0<<22) -#define mskCT16_PWM11MODE_FORCE_1 (CT16_PWM11MODE_FORCE_1<<22) - - //[25:24] CT16Bn PWM12 output mode. -#define CT16_PWM12MODE_1 0 // PWM mode 1. -#define CT16_PWM12MODE_2 1 // PWM mode 2. -#define CT16_PWM12MODE_FORCE_0 2 // Force 0. -#define CT16_PWM12MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM12MODE_1 (CT16_PWM12MODE_1<<24) -#define mskCT16_PWM12MODE_2 (CT16_PWM12MODE_2<<24) -#define mskCT16_PWM12MODE_FORCE_0 (CT16_PWM12MODE_FORCE_0<<24) -#define mskCT16_PWM12MODE_FORCE_1 (CT16_PWM12MODE_FORCE_1<<24) - - //[27:26] CT16Bn PWM13 output mode. -#define CT16_PWM13MODE_1 0 // PWM mode 1. -#define CT16_PWM13MODE_2 1 // PWM mode 2. -#define CT16_PWM13MODE_FORCE_0 2 // Force 0. -#define CT16_PWM13MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM13MODE_1 (CT16_PWM13MODE_1<<26) -#define mskCT16_PWM13MODE_2 (CT16_PWM13MODE_2<<26) -#define mskCT16_PWM13MODE_FORCE_0 (CT16_PWM13MODE_FORCE_0<<26) -#define mskCT16_PWM13MODE_FORCE_1 (CT16_PWM13MODE_FORCE_1<<26) - - //[29:28] CT16Bn PWM14 output mode. -#define CT16_PWM14MODE_1 0 // PWM mode 1. -#define CT16_PWM14MODE_2 1 // PWM mode 2. -#define CT16_PWM14MODE_FORCE_0 2 // Force 0. -#define CT16_PWM14MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM14MODE_1 (CT16_PWM14MODE_1<<28) -#define mskCT16_PWM14MODE_2 (CT16_PWM14MODE_2<<28) -#define mskCT16_PWM14MODE_FORCE_0 (CT16_PWM14MODE_FORCE_0<<28) -#define mskCT16_PWM14MODE_FORCE_1 (CT16_PWM14MODE_FORCE_1<<28) - - //[31:30] CT16Bn PWM15 output mode. -#define CT16_PWM15MODE_1 0 // PWM mode 1. -#define CT16_PWM15MODE_2 1 // PWM mode 2. -#define CT16_PWM15MODE_FORCE_0 2 // Force 0. -#define CT16_PWM15MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM15MODE_1 (CT16_PWM15MODE_1<<30) -#define mskCT16_PWM15MODE_2 (CT16_PWM15MODE_2<<30) -#define mskCT16_PWM15MODE_FORCE_0 (CT16_PWM15MODE_FORCE_0<<30) -#define mskCT16_PWM15MODE_FORCE_1 (CT16_PWM15MODE_FORCE_1<<30) - -/* CT16Bn PWM Control register (0x98) */ - //[1:0] CT16Bn PWM16 output mode. -#define CT16_PWM16MODE_1 0 // PWM mode 1. -#define CT16_PWM16MODE_2 1 // PWM mode 2. -#define CT16_PWM16MODE_FORCE_0 2 // Force 0. -#define CT16_PWM16MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM16MODE_1 (CT16_PWM16MODE_1<<0) -#define mskCT16_PWM16MODE_2 (CT16_PWM16MODE_2<<0) -#define mskCT16_PWM16MODE_FORCE_0 (CT16_PWM16MODE_FORCE_0<<0) -#define mskCT16_PWM16MODE_FORCE_1 (CT16_PWM16MODE_FORCE_1<<0) - - //[3:2] CT16Bn PWM17 output mode. -#define CT16_PWM17MODE_1 0 // PWM mode 1. -#define CT16_PWM17MODE_2 1 // PWM mode 2. -#define CT16_PWM17MODE_FORCE_0 2 // Force 0. -#define CT16_PWM17MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM17MODE_1 (CT16_PWM17MODE_1<<2) -#define mskCT16_PWM17MODE_2 (CT16_PWM17MODE_2<<2) -#define mskCT16_PWM17MODE_FORCE_0 (CT16_PWM17MODE_FORCE_0<<2) -#define mskCT16_PWM17MODE_FORCE_1 (CT16_PWM17MODE_FORCE_1<<2) - - //[5:4] CT16Bn PWM18 output mode. -#define CT16_PWM18MODE_1 0 // PWM mode 1. -#define CT16_PWM18MODE_2 1 // PWM mode 2. -#define CT16_PWM18MODE_FORCE_0 2 // Force 0. -#define CT16_PWM18MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM18MODE_1 (CT16_PWM18MODE_1<<4) -#define mskCT16_PWM18MODE_2 (CT16_PWM18MODE_2<<4) -#define mskCT16_PWM18MODE_FORCE_0 (CT16_PWM18MODE_FORCE_0<<4) -#define mskCT16_PWM18MODE_FORCE_1 (CT16_PWM18MODE_FORCE_1<<4) - - //[7:6] CT16Bn PWM19 output mode. -#define CT16_PWM19MODE_1 0 // PWM mode 1. -#define CT16_PWM19MODE_2 1 // PWM mode 2. -#define CT16_PWM19MODE_FORCE_0 2 // Force 0. -#define CT16_PWM19MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM19MODE_1 (CT16_PWM19MODE_1<<6) -#define mskCT16_PWM19MODE_2 (CT16_PWM19MODE_2<<6) -#define mskCT16_PWM19MODE_FORCE_0 (CT16_PWM19MODE_FORCE_0<<6) -#define mskCT16_PWM19MODE_FORCE_1 (CT16_PWM19MODE_FORCE_1<<6) - - //[9:8] CT16Bn PWM20 output mode. -#define CT16_PWM20MODE_1 0 // PWM mode 1. -#define CT16_PWM20MODE_2 1 // PWM mode 2. -#define CT16_PWM20MODE_FORCE_0 2 // Force 0. -#define CT16_PWM20MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM20MODE_1 (CT16_PWM20MODE_1<<8) -#define mskCT16_PWM20MODE_2 (CT16_PWM20MODE_2<<8) -#define mskCT16_PWM20MODE_FORCE_0 (CT16_PWM20MODE_FORCE_0<<8) -#define mskCT16_PWM20MODE_FORCE_1 (CT16_PWM20MODE_FORCE_1<<8) - - //[11:10] CT16Bn PWM21 output mode. -#define CT16_PWM21MODE_1 0 // PWM mode 1. -#define CT16_PWM21MODE_2 1 // PWM mode 2. -#define CT16_PWM21MODE_FORCE_0 2 // Force 0. -#define CT16_PWM21MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM21MODE_1 (CT16_PWM21MODE_1<<10) -#define mskCT16_PWM21MODE_2 (CT16_PWM21MODE_2<<10) -#define mskCT16_PWM21MODE_FORCE_0 (CT16_PWM21MODE_FORCE_0<<10) -#define mskCT16_PWM21MODE_FORCE_1 (CT16_PWM21MODE_FORCE_1<<10) - - //[13:12] CT16Bn PWM22 output mode. -#define CT16_PWM22MODE_1 0 // PWM mode 1. -#define CT16_PWM22MODE_2 1 // PWM mode 2. -#define CT16_PWM22MODE_FORCE_0 2 // Force 0. -#define CT16_PWM22MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM22MODE_1 (CT16_PWM22MODE_1<<12) -#define mskCT16_PWM22MODE_2 (CT16_PWM22MODE_2<<12) -#define mskCT16_PWM22MODE_FORCE_0 (CT16_PWM22MODE_FORCE_0<<12) -#define mskCT16_PWM22MODE_FORCE_1 (CT16_PWM22MODE_FORCE_1<<12) - - //[15:14] CT16Bn PWM23 output mode. -#define CT16_PWM23MODE_1 0 // PWM mode 1. -#define CT16_PWM23MODE_2 1 // PWM mode 2. -#define CT16_PWM23MODE_FORCE_0 2 // Force 0. -#define CT16_PWM23MODE_FORCE_1 3 // Force 1. -#define mskCT16_PWM23MODE_1 (CT16_PWM23MODE_1<<14) -#define mskCT16_PWM23MODE_2 (CT16_PWM23MODE_2<<14) -#define mskCT16_PWM23MODE_FORCE_0 (CT16_PWM23MODE_FORCE_0<<14) -#define mskCT16_PWM23MODE_FORCE_1 (CT16_PWM23MODE_FORCE_1<<14) - -/* CT16Bn PWM Enable register (0x9C) */ - //[0:0] CT16Bn PWM0 enable. -#define CT16_PWM0EN_EN 1 // CT16Bn PWM0 is enabled for PWM mode. -#define CT16_PWM0EN_EM0 0 // CT16Bn PWM0 is controlled by EM0. -#define mskCT16_PWM0EN_EN (CT16_PWM0EN_EN<<0) -#define mskCT16_PWM0EN_EM0 (CT16_PWM0EN_EM0<<0) - - //[1:1] CT16Bn PWM1 enable. -#define CT16_PWM1EN_EN 1 // CT16Bn PWM1 is enabled for PWM mode. -#define CT16_PWM1EN_EM1 0 // CT16Bn PWM1 is controlled by EM1. -#define mskCT16_PWM1EN_EN (CT16_PWM1EN_EN<<1) -#define mskCT16_PWM1EN_EM1 (CT16_PWM1EN_EM1<<1) - - //[2:2] CT16Bn PWM2 enable. -#define CT16_PWM2EN_EN 1 // CT16Bn PWM2 is enabled for PWM mode. -#define CT16_PWM2EN_EM2 0 // CT16Bn PWM2 is controlled by EM2. -#define mskCT16_PWM2EN_EN (CT16_PWM2EN_EN<<2) -#define mskCT16_PWM2EN_EM2 (CT16_PWM2EN_EM2<<2) - - //[3:3] CT16Bn PWM3 enable. -#define CT16_PWM3EN_EN 1 // CT16Bn PWM3 is enabled for PWM mode. -#define CT16_PWM3EN_EM3 0 // CT16Bn PWM3 is controlled by EM3. -#define mskCT16_PWM3EN_EN (CT16_PWM3EN_EN<<3) -#define mskCT16_PWM3EN_EM3 (CT16_PWM3EN_EM3<<3) - - //[4:4] CT16Bn PWM4 enable. -#define CT16_PWM4EN_EN 1 // CT16Bn PWM4 is enabled for PWM mode. -#define CT16_PWM4EN_EM4 0 // CT16Bn PWM4 is controlled by EM4. -#define mskCT16_PWM4EN_EN (CT16_PWM4EN_EN<<4) -#define mskCT16_PWM4EN_EM4 (CT16_PWM4EN_EM4<<4) - - //[5:5] CT16Bn PWM5 enable. -#define CT16_PWM5EN_EN 1 // CT16Bn PWM5 is enabled for PWM mode. -#define CT16_PWM5EN_EM5 0 // CT16Bn PWM5 is controlled by EM5. -#define mskCT16_PWM5EN_EN (CT16_PWM5EN_EN<<5) -#define mskCT16_PWM5EN_EM5 (CT16_PWM5EN_EM5<<5) - - //[6:6] CT16Bn PWM6 enable. -#define CT16_PWM6EN_EN 1 // CT16Bn PWM6 is enabled for PWM mode. -#define CT16_PWM6EN_EM6 0 // CT16Bn PWM6 is controlled by EM6. -#define mskCT16_PWM6EN_EN (CT16_PWM6EN_EN<<6) -#define mskCT16_PWM6EN_EM6 (CT16_PWM6EN_EM6<<6) - - //[7:7] CT16Bn PWM7 enable. -#define CT16_PWM7EN_EN 1 // CT16Bn PWM7 is enabled for PWM mode. -#define CT16_PWM7EN_EM7 0 // CT16Bn PWM7 is controlled by EM7. -#define mskCT16_PWM7EN_EN (CT16_PWM7EN_EN<<7) -#define mskCT16_PWM7EN_EM7 (CT16_PWM7EN_EM7<<7) - - //[8:8] CT16Bn PWM8 enable. -#define CT16_PWM8EN_EN 1 // CT16Bn PWM8 is enabled for PWM mode. -#define CT16_PWM8EN_EM8 0 // CT16Bn PWM8 is controlled by EM8. -#define mskCT16_PWM8EN_EN (CT16_PWM8EN_EN<<8) -#define mskCT16_PWM8EN_EM8 (CT16_PWM8EN_EM8<<8) - - //[9:9] CT16Bn PWM9 enable. -#define CT16_PWM9EN_EN 1 // CT16Bn PWM9 is enabled for PWM mode. -#define CT16_PWM9EN_EM9 0 // CT16Bn PWM9 is controlled by EM9. -#define mskCT16_PWM9EN_EN (CT16_PWM9EN_EN<<9) -#define mskCT16_PWM9EN_EM9 (CT16_PWM9EN_EM9<<9) - - //[10:10] CT16Bn PWM10 enable. -#define CT16_PWM10EN_EN 1 // CT16Bn PWM10 is enabled for PWM mode. -#define CT16_PWM10EN_EM10 0 // CT16Bn PWM10 is controlled by EM10. -#define mskCT16_PWM10EN_EN (CT16_PWM10EN_EN<<10) -#define mskCT16_PWM10EN_EM10 (CT16_PWM10EN_EM10<<10) - - //[11:11] CT16Bn PWM11 enable. -#define CT16_PWM11EN_EN 1 // CT16Bn PWM11 is enabled for PWM mode. -#define CT16_PWM11EN_EM11 0 // CT16Bn PWM11 is controlled by EM11. -#define mskCT16_PWM11EN_EN (CT16_PWM11EN_EN<<11) -#define mskCT16_PWM11EN_EM11 (CT16_PWM11EN_EM11<<11) - - //[12:12] CT16Bn PWM12 enable. -#define CT16_PWM12EN_EN 1 // CT16Bn PWM12 is enabled for PWM mode. -#define CT16_PWM12EN_EM12 0 // CT16Bn PWM12 is controlled by EM12. -#define mskCT16_PWM12EN_EN (CT16_PWM12EN_EN<<12) -#define mskCT16_PWM12EN_EM12 (CT16_PWM12EN_EM12<<12) - - //[13:13] CT16Bn PWM13 enable. -#define CT16_PWM13EN_EN 1 // CT16Bn PWM13 is enabled for PWM mode. -#define CT16_PWM13EN_EM13 0 // CT16Bn PWM13 is controlled by EM13. -#define mskCT16_PWM13EN_EN (CT16_PWM13EN_EN<<13) -#define mskCT16_PWM13EN_EM13 (CT16_PWM13EN_EM13<<13) - - //[14:14] CT16Bn PWM14 enable. -#define CT16_PWM14EN_EN 1 // CT16Bn PWM14 is enabled for PWM mode. -#define CT16_PWM14EN_EM14 0 // CT16Bn PWM14 is controlled by EM14. -#define mskCT16_PWM14EN_EN (CT16_PWM14EN_EN<<14) -#define mskCT16_PWM14EN_EM14 (CT16_PWM14EN_EM14<<14) - - //[15:15] CT16Bn PWM15 enable. -#define CT16_PWM15EN_EN 1 // CT16Bn PWM15 is enabled for PWM mode. -#define CT16_PWM15EN_EM15 0 // CT16Bn PWM15 is controlled by EM15. -#define mskCT16_PWM15EN_EN (CT16_PWM15EN_EN<<15) -#define mskCT16_PWM15EN_EM15 (CT16_PWM15EN_EM15<<15) - - //[16:16] CT16Bn PWM16 enable. -#define CT16_PWM16EN_EN 1 // CT16Bn PWM16 is enabled for PWM mode. -#define CT16_PWM16EN_EM16 0 // CT16Bn PWM16 is controlled by EM16. -#define mskCT16_PWM16EN_EN (CT16_PWM16EN_EN<<16) -#define mskCT16_PWM16EN_EM16 (CT16_PWM16EN_EM16<<16) - - //[17:17] CT16Bn PWM17 enable. -#define CT16_PWM17EN_EN 1 // CT16Bn PWM17 is enabled for PWM mode. -#define CT16_PWM17EN_EM17 0 // CT16Bn PWM17 is controlled by EM17. -#define mskCT16_PWM17EN_EN (CT16_PWM17EN_EN<<17) -#define mskCT16_PWM17EN_EM17 (CT16_PWM17EN_EM17<<17) - - //[18:18] CT16Bn PWM18 enable. -#define CT16_PWM18EN_EN 1 // CT16Bn PWM18 is enabled for PWM mode. -#define CT16_PWM18EN_EM18 0 // CT16Bn PWM18 is controlled by EM18. -#define mskCT16_PWM18EN_EN (CT16_PWM18EN_EN<<18) -#define mskCT16_PWM18EN_EM18 (CT16_PWM18EN_EM18<<18) - - //[19:19] CT16Bn PWM19 enable. -#define CT16_PWM19EN_EN 1 // CT16Bn PWM19 is enabled for PWM mode. -#define CT16_PWM19EN_EM19 0 // CT16Bn PWM19 is controlled by EM19. -#define mskCT16_PWM19EN_EN (CT16_PWM19EN_EN<<19) -#define mskCT16_PWM19EN_EM19 (CT16_PWM19EN_EM19<<19) - - //[20:20] CT16Bn PWM20 enable. -#define CT16_PWM20EN_EN 1 // CT16Bn PWM20 is enabled for PWM mode. -#define CT16_PWM20EN_EM20 0 // CT16Bn PWM20 is controlled by EM20. -#define mskCT16_PWM20EN_EN (CT16_PWM20EN_EN<<20) -#define mskCT16_PWM20EN_EM20 (CT16_PWM20EN_EM20<<20) - - //[21:21] CT16Bn PWM21 enable. -#define CT16_PWM21EN_EN 1 // CT16Bn PWM21 is enabled for PWM mode. -#define CT16_PWM21EN_EM21 0 // CT16Bn PWM21 is controlled by EM21. -#define mskCT16_PWM21EN_EN (CT16_PWM21EN_EN<<21) -#define mskCT16_PWM21EN_EM21 (CT16_PWM21EN_EM21<<21) - - //[22:22] CT16Bn PWM22 enable. -#define CT16_PWM22EN_EN 1 // CT16Bn PWM22 is enabled for PWM mode. -#define CT16_PWM22EN_EM22 0 // CT16Bn PWM22 is controlled by EM22. -#define mskCT16_PWM22EN_EN (CT16_PWM22EN_EN<<22) -#define mskCT16_PWM22EN_EM22 (CT16_PWM22EN_EM22<<22) - - //[23:23] CT16Bn PWM23 enable. -#define CT16_PWM23EN_EN 1 // CT16Bn PWM23 is enabled for PWM mode. -#define CT16_PWM23EN_EM23 0 // CT16Bn PWM23 is controlled by EM23. -#define mskCT16_PWM23EN_EN (CT16_PWM23EN_EN<<23) -#define mskCT16_PWM23EN_EM23 (CT16_PWM23EN_EM23<<23) - -/* CT16Bn PWM IO Enable register (0xA0) */ - //[0:0] CT16Bn PWM0 IO selection. -#define CT16_PWM0IOEN_EN 1 // PWM0 pin acts as match output. -#define CT16_PWM0IOEN_DIS 0 // PWM0 pin acts as GPIO. -#define mskCT16_PWM0IOEN_EN (CT16_PWM0IOEN_EN<<0) -#define mskCT16_PWM0IOEN_DIS (CT16_PWM0IOEN_DIS<<0) - - //[1:1] CT16Bn PWM1 IO selection. -#define CT16_PWM1IOEN_EN 1 // PWM1 pin acts as match output. -#define CT16_PWM1IOEN_DIS 0 // PWM1 pin acts as GPIO. -#define mskCT16_PWM1IOEN_EN (CT16_PWM1IOEN_EN<<1) -#define mskCT16_PWM1IOEN_DIS (CT16_PWM1IOEN_DIS<<1) - - //[2:2] CT16Bn PWM2 IO selection. -#define CT16_PWM2IOEN_EN 1 // PWM2 pin acts as match output. -#define CT16_PWM2IOEN_DIS 0 // PWM2 pin acts as GPIO. -#define mskCT16_PWM2IOEN_EN (CT16_PWM2IOEN_EN<<2) -#define mskCT16_PWM2IOEN_DIS (CT16_PWM2IOEN_DIS<<2) - - //[3:3] CT16Bn PWM3 IO selection. -#define CT16_PWM3IOEN_EN 1 // PWM3 pin acts as match output. -#define CT16_PWM3IOEN_DIS 0 // PWM3 pin acts as GPIO. -#define mskCT16_PWM3IOEN_EN (CT16_PWM3IOEN_EN<<3) -#define mskCT16_PWM3IOEN_DIS (CT16_PWM3IOEN_DIS<<3) - - //[4:4] CT16Bn PWM4 IO selection. -#define CT16_PWM4IOEN_EN 1 // PWM4 pin acts as match output. -#define CT16_PWM4IOEN_DIS 0 // PWM4 pin acts as GPIO. -#define mskCT16_PWM4IOEN_EN (CT16_PWM4IOEN_EN<<4) -#define mskCT16_PWM4IOEN_DIS (CT16_PWM4IOEN_DIS<<4) - - //[5:5] CT16Bn PWM5 IO selection. -#define CT16_PWM5IOEN_EN 1 // PWM5 pin acts as match output. -#define CT16_PWM5IOEN_DIS 0 // PWM5 pin acts as GPIO. -#define mskCT16_PWM5IOEN_EN (CT16_PWM5IOEN_EN<<5) -#define mskCT16_PWM5IOEN_DIS (CT16_PWM5IOEN_DIS<<5) - - //[6:6] CT16Bn PWM6 IO selection. -#define CT16_PWM6IOEN_EN 1 // PWM6 pin acts as match output. -#define CT16_PWM6IOEN_DIS 0 // PWM6 pin acts as GPIO. -#define mskCT16_PWM6IOEN_EN (CT16_PWM6IOEN_EN<<6) -#define mskCT16_PWM6IOEN_DIS (CT16_PWM6IOEN_DIS<<6) - - //[7:7] CT16Bn PWM7 IO selection. -#define CT16_PWM7IOEN_EN 1 // PWM7 pin acts as match output. -#define CT16_PWM7IOEN_DIS 0 // PWM7 pin acts as GPIO. -#define mskCT16_PWM7IOEN_EN (CT16_PWM7IOEN_EN<<7) -#define mskCT16_PWM7IOEN_DIS (CT16_PWM7IOEN_DIS<<7) - - //[8:8] CT16Bn PWM8 IO selection. -#define CT16_PWM8IOEN_EN 1 // PWM8 pin acts as match output. -#define CT16_PWM8IOEN_DIS 0 // PWM8 pin acts as GPIO. -#define mskCT16_PWM8IOEN_EN (CT16_PWM8IOEN_EN<<8) -#define mskCT16_PWM8IOEN_DIS (CT16_PWM8IOEN_DIS<<8) - - //[9:9] CT16Bn PWM9 IO selection. -#define CT16_PWM9IOEN_EN 1 // PWM9 pin acts as match output. -#define CT16_PWM9IOEN_DIS 0 // PWM9 pin acts as GPIO. -#define mskCT16_PWM9IOEN_EN (CT16_PWM9IOEN_EN<<9) -#define mskCT16_PWM9IOEN_DIS (CT16_PWM9IOEN_DIS<<9) - - //[10:10] CT16Bn PWM10 IO selection. -#define CT16_PWM10IOEN_EN 1 // PWM10 pin acts as match output. -#define CT16_PWM10IOEN_DIS 0 // PWM10 pin acts as GPIO. -#define mskCT16_PWM10IOEN_EN (CT16_PWM10IOEN_EN<<10) -#define mskCT16_PWM10IOEN_DIS (CT16_PWM10IOEN_DIS<<10) - - //[11:11] CT16Bn PWM11 IO selection. -#define CT16_PWM11IOEN_EN 1 // PWM11 pin acts as match output. -#define CT16_PWM11IOEN_DIS 0 // PWM11 pin acts as GPIO. -#define mskCT16_PWM11IOEN_EN (CT16_PWM11IOEN_EN<<11) -#define mskCT16_PWM11IOEN_DIS (CT16_PWM11IOEN_DIS<<11) - - //[12:12] CT16Bn PWM12 IO selection. -#define CT16_PWM12IOEN_EN 1 // PWM12 pin acts as match output. -#define CT16_PWM12IOEN_DIS 0 // PWM12 pin acts as GPIO. -#define mskCT16_PWM12IOEN_EN (CT16_PWM12IOEN_EN<<12) -#define mskCT16_PWM12IOEN_DIS (CT16_PWM12IOEN_DIS<<12) - - //[13:13] CT16Bn PWM13 IO selection. -#define CT16_PWM13IOEN_EN 1 // PWM13 pin acts as match output. -#define CT16_PWM13IOEN_DIS 0 // PWM13 pin acts as GPIO. -#define mskCT16_PWM13IOEN_EN (CT16_PWM13IOEN_EN<<13) -#define mskCT16_PWM13IOEN_DIS (CT16_PWM13IOEN_DIS<<13) - - //[14:14] CT16Bn PWM14 IO selection. -#define CT16_PWM14IOEN_EN 1 // PWM14 pin acts as match output. -#define CT16_PWM14IOEN_DIS 0 // PWM14 pin acts as GPIO. -#define mskCT16_PWM14IOEN_EN (CT16_PWM14IOEN_EN<<14) -#define mskCT16_PWM14IOEN_DIS (CT16_PWM14IOEN_DIS<<14) - - //[15:15] CT16Bn PWM15 IO selection. -#define CT16_PWM15IOEN_EN 1 // PWM15 pin acts as match output. -#define CT16_PWM15IOEN_DIS 0 // PWM15 pin acts as GPIO. -#define mskCT16_PWM15IOEN_EN (CT16_PWM15IOEN_EN<<15) -#define mskCT16_PWM15IOEN_DIS (CT16_PWM15IOEN_DIS<<15) - - //[16:16] CT16Bn PWM16 IO selection. -#define CT16_PWM16IOEN_EN 1 // PWM16 pin acts as match output. -#define CT16_PWM16IOEN_DIS 0 // PWM16 pin acts as GPIO. -#define mskCT16_PWM16IOEN_EN (CT16_PWM16IOEN_EN<<16) -#define mskCT16_PWM16IOEN_DIS (CT16_PWM16IOEN_DIS<<16) - - //[17:17] CT16Bn PWM17 IO selection. -#define CT16_PWM17IOEN_EN 1 // PWM17 pin acts as match output. -#define CT16_PWM17IOEN_DIS 0 // PWM17 pin acts as GPIO. -#define mskCT16_PWM17IOEN_EN (CT16_PWM17IOEN_EN<<17) -#define mskCT16_PWM17IOEN_DIS (CT16_PWM17IOEN_DIS<<17) - - //[18:18] CT16Bn PWM18 IO selection. -#define CT16_PWM18IOEN_EN 1 // PWM18 pin acts as match output. -#define CT16_PWM18IOEN_DIS 0 // PWM18 pin acts as GPIO. -#define mskCT16_PWM18IOEN_EN (CT16_PWM18IOEN_EN<<18) -#define mskCT16_PWM18IOEN_DIS (CT16_PWM18IOEN_DIS<<18) - - //[19:19] CT16Bn PWM19 IO selection. -#define CT16_PWM19IOEN_EN 1 // PWM19 pin acts as match output. -#define CT16_PWM19IOEN_DIS 0 // PWM19 pin acts as GPIO. -#define mskCT16_PWM19IOEN_EN (CT16_PWM19IOEN_EN<<19) -#define mskCT16_PWM19IOEN_DIS (CT16_PWM19IOEN_DIS<<19) - - //[20:20] CT16Bn PWM20 IO selection. -#define CT16_PWM20IOEN_EN 1 // PWM20 pin acts as match output. -#define CT16_PWM20IOEN_DIS 0 // PWM20 pin acts as GPIO. -#define mskCT16_PWM20IOEN_EN (CT16_PWM20IOEN_EN<<20) -#define mskCT16_PWM20IOEN_DIS (CT16_PWM20IOEN_DIS<<20) - - //[21:21] CT16Bn PWM21 IO selection. -#define CT16_PWM21IOEN_EN 1 // PWM21 pin acts as match output. -#define CT16_PWM21IOEN_DIS 0 // PWM21 pin acts as GPIO. -#define mskCT16_PWM21IOEN_EN (CT16_PWM21IOEN_EN<<21) -#define mskCT16_PWM21IOEN_DIS (CT16_PWM21IOEN_DIS<<21) - - //[22:22] CT16Bn PWM22 IO selection. -#define CT16_PWM22IOEN_EN 1 // PWM22 pin acts as match output. -#define CT16_PWM22IOEN_DIS 0 // PWM22 pin acts as GPIO. -#define mskCT16_PWM22IOEN_EN (CT16_PWM22IOEN_EN<<22) -#define mskCT16_PWM22IOEN_DIS (CT16_PWM22IOEN_DIS<<22) - - //[23:23] CT16Bn PWM23 IO selection. -#define CT16_PWM23IOEN_EN 1 // PWM23 pin acts as match output. -#define CT16_PWM23IOEN_DIS 0 // PWM23 pin acts as GPIO. -#define mskCT16_PWM23IOEN_EN (CT16_PWM23IOEN_EN<<23) -#define mskCT16_PWM23IOEN_DIS (CT16_PWM23IOEN_DIS<<23) - - -/* CT16Bn Timer Raw Interrupt Status register (0xA4) */ -/* CT16Bn Timer Interrupt Clear register (0xA8) */ -/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/ -#define mskCT16_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 -#define mskCT16_MR0IC mskCT16_MR0IF -#define mskCT16_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 -#define mskCT16_MR1IC mskCT16_MR1IF -#define mskCT16_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 -#define mskCT16_MR2IC mskCT16_MR2IF -#define mskCT16_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 -#define mskCT16_MR3IC mskCT16_MR3IF -#define mskCT16_MR4IF (0x1<<4) //[4:4] Interrupt flag for match channel 4 -#define mskCT16_MR4IC mskCT16_MR4IF -#define mskCT16_MR5IF (0x1<<5) //[5:5] Interrupt flag for match channel 5 -#define mskCT16_MR5IC mskCT16_MR5IF -#define mskCT16_MR6IF (0x1<<6) //[6:6] Interrupt flag for match channel 6 -#define mskCT16_MR6IC mskCT16_MR6IF -#define mskCT16_MR7IF (0x1<<7) //[7:7] Interrupt flag for match channel 7 -#define mskCT16_MR7IC mskCT16_MR7IF -#define mskCT16_MR8IF (0x1<<8) //[8:8] Interrupt flag for match channel 8 -#define mskCT16_MR8IC mskCT16_MR8IF -#define mskCT16_MR9IF (0x1<<9) //[9:9] Interrupt flag for match channel 9 -#define mskCT16_MR9IC mskCT16_MR9IF -#define mskCT16_MR10IF (0x1<<10) //[10:10] Interrupt flag for match channel 10 -#define mskCT16_MR10IC mskCT16_MR10IF -#define mskCT16_MR11IF (0x1<<11) //[11:11] Interrupt flag for match channel 11 -#define mskCT16_MR11IC mskCT16_MR11IF -#define mskCT16_MR12IF (0x1<<12) //[12:12] Interrupt flag for match channel 12 -#define mskCT16_MR12IC mskCT16_MR12IF -#define mskCT16_MR13IF (0x1<<13) //[13:13] Interrupt flag for match channel 13 -#define mskCT16_MR13IC mskCT16_MR13IF -#define mskCT16_MR14IF (0x1<<14) //[14:14] Interrupt flag for match channel 14 -#define mskCT16_MR14IC mskCT16_MR14IF -#define mskCT16_MR15IF (0x1<<15) //[15:15] Interrupt flag for match channel 15 -#define mskCT16_MR15IC mskCT16_MR15IF -#define mskCT16_MR16IF (0x1<<16) //[16:16] Interrupt flag for match channel 16 -#define mskCT16_MR16IC mskCT16_MR16IF -#define mskCT16_MR17IF (0x1<<17) //[17:17] Interrupt flag for match channel 17 -#define mskCT16_MR17IC mskCT16_MR17IF -#define mskCT16_MR18IF (0x1<<18) //[18:18] Interrupt flag for match channel 18 -#define mskCT16_MR18IC mskCT16_MR18IF -#define mskCT16_MR19IF (0x1<<19) //[19:19] Interrupt flag for match channel 19 -#define mskCT16_MR19IC mskCT16_MR19IF -#define mskCT16_MR20IF (0x1<<20) //[20:20] Interrupt flag for match channel 20 -#define mskCT16_MR20IC mskCT16_MR20IF -#define mskCT16_MR21IF (0x1<<21) //[21:21] Interrupt flag for match channel 21 -#define mskCT16_MR21IC mskCT16_MR21IF -#define mskCT16_MR22IF (0x1<<22) //[22:22] Interrupt flag for match channel 22 -#define mskCT16_MR22IC mskCT16_MR22IF -#define mskCT16_MR23IF (0x1<<23) //[23:23] Interrupt flag for match channel 23 -#define mskCT16_MR23IC mskCT16_MR23IF -#define mskCT16_MR24IF (0x1<<24) //[24:24] Interrupt flag for match channel 24 -#define mskCT16_MR24IC mskCT16_MR24IF -#define mskCT16_CAP0IF (0x1<<25) //[25:25] Interrupt flag for capture channel 25 -#define mskCT16_CAP0IC mskCT16_CAP0IF -/*_____ M A C R O S ________________________________________________________*/ - -#endif //*__SN32F2XX_CT16_H diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c deleted file mode 100644 index 492e24a5a4..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c +++ /dev/null @@ -1,146 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT16B0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "sn32_ct.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT16B0_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -void CT16B0_Init (void); -void CT16B0_NvicEnable (void); -void CT16B0_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : CT16B0_Init -* Description : Initialization of CT16B0 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_Init (void) -{ - //Enable P_CLOCK for CT16B0. - sys1EnableCT16B0(); - - //CT16B0 PCLK prescalar setting - // SN_SYS1->APBCP1_b.CT16B0PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP0_b.CT16B0PRE = 0x04; //PCLK = HCLK/16 -} -/***************************************************************************** -* Function : CT16B0_ResetTimer -* Description : Reset of CT16B0 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_ResetTimer (void) -{ - //Set CT16B0 as the up-counting mode. - SN_CT16B0->TMRCTRL = (mskCT16_CRST); - - // Wait until timer reset done. - while (SN_CT16B0->TMRCTRL & mskCT16_CRST); -} -/***************************************************************************** -* Function : CT16B0_NvicEnable -* Description : Enable CT16B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT16B0_IRQn); - NVIC_EnableIRQ(CT16B0_IRQn); - //NVIC_SetPriority(CT16B0_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT16B0_NvicEnable -* Description : Disable CT16B0 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_NvicDisable (void) -{ - NVIC_DisableIRQ(CT16B0_IRQn); -} - - - -/***************************************************************************** -* Function : CT16B0_IRQHandler -* Description : ISR of CT16B0 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B0_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT16B0->RIS; //Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT16B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT16_MR0IF) - { - iwCT16B0_IrqEvent |= mskCT16_MR0IF; - SN_CT16B0->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status - } - } - //CAP0 - if (SN_CT16B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? - { - if(iwRisStatus & mskCT16_CAP0IF) //CAP0 - { - iwCT16B0_IrqEvent |= mskCT16_CAP0IF; - SN_CT16B0->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status - } - } -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h deleted file mode 100644 index 6b8237385f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __SN32F240_CT16B0_H -#define __SN32F240_CT16B0_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt - //POLLING_METHOD: Enable CT16B0 timer ONLY - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -extern void CT16B0_Init(void); -extern void CT16B0_ResetTimer(void); -extern void CT16B0_NvicEnable (void); -extern void CT16B0_NvicDisable (void); -#endif /*__SN32F240_CT16B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c deleted file mode 100644 index 51176ebdc1..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c +++ /dev/null @@ -1,355 +0,0 @@ -/******************** (C) COPYRIGHT 2013 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2013/12 -* AUTHOR: SA1 -* IC: SN32F240/230/220 -* DESCRIPTION: CT16B1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2013/12/17 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "sn32_ct.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint32_t iwCT16B1_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -void CT16B1_Init (void); -void CT16B1_NvicEnable (void); -void CT16B1_NvicDisable (void); - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : CT16B1_Init -* Description : Initialization of CT16B1 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_Init (void) -{ - //Enable P_CLOCK for CT16B1. - sys1EnableCT16B1(); - - //CT16B1 PCLK prescalar setting - //SN_SYS1->APBCP1_b.CT16B1PRE = 0x00; //PCLK = HCLK/1 - //SN_SYS1->APBCP1_b.CT16B1PRE = 0x01; //PCLK = HCLK/2 - //SN_SYS1->APBCP1_b.CT16B1PRE = 0x02; //PCLK = HCLK/4 - //SN_SYS1->APBCP1_b.CT16B1PRE = 0x03; //PCLK = HCLK/8 - //SN_SYS1->APBCP1_b.CT16B1PRE = 0x04; //PCLK = HCLK/16 -} - -/***************************************************************************** -* Function : CT16B1_ResetTimer -* Description : Reset of CT16B1 timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_ResetTimer (void) -{ - //Set CT16B1 as the up-counting mode. - SN_CT16B1->TMRCTRL = (mskCT16_CRST); - - // Wait until timer reset done. - while (SN_CT16B1->TMRCTRL & mskCT16_CRST); -} - -/***************************************************************************** -* Function : CT16B1_NvicEnable -* Description : Enable CT16B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_NvicEnable (void) -{ - NVIC_ClearPendingIRQ(CT16B1_IRQn); - NVIC_EnableIRQ(CT16B1_IRQn); - //NVIC_SetPriority(CT16B1_IRQn,0); // Set interrupt priority (default) -} - -/***************************************************************************** -* Function : CT16B1_NvicDisable -* Description : Enable CT16B1 timer interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_NvicDisable (void) -{ - NVIC_DisableIRQ(CT16B1_IRQn); -} - -/***************************************************************************** -* Function : CT16B1_IRQHandler -* Description : ISR of CT16B1 interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void CT16B1_IRQHandler(void) -{ - uint32_t iwRisStatus; - - iwRisStatus = SN_CT16B1->RIS; //Save the interrupt status. - - //Before checking the status, always re-check the interrupt enable register first. - //In practice, user might use only one or two timer interrupt source. - //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. - //User can add the directive pair of "#if 0" and "#endif" pair - //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. - - //Check the status in oder. - //MR0 - if (SN_CT16B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? - { - if(iwRisStatus & mskCT16_MR0IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR0IF; - SN_CT16B1->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status - } - } - //MR1 - if (SN_CT16B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? - { - if(iwRisStatus & mskCT16_MR1IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR1IF; - SN_CT16B1->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status - } - } - //MR2 - if (SN_CT16B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? - { - if(iwRisStatus & mskCT16_MR2IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR2IF; - SN_CT16B1->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status - } - } - //MR3 - if (SN_CT16B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? - { - if(iwRisStatus & mskCT16_MR3IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR3IF; - SN_CT16B1->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status - } - } - //MR4 - if (SN_CT16B1->MCTRL_b.MR4IE) //Check if MR4 IE enables? - { - if(iwRisStatus & mskCT16_MR4IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR4IF; - SN_CT16B1->IC = mskCT16_MR4IC; //Clear MR4 match interrupt status - } - } - //MR5 - if (SN_CT16B1->MCTRL_b.MR5IE) //Check if MR5 IE enables? - { - if(iwRisStatus & mskCT16_MR5IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR5IF; - SN_CT16B1->IC = mskCT16_MR5IC; //Clear MR5 match interrupt status - } - } - //MR6 - if (SN_CT16B1->MCTRL_b.MR6IE) //Check if MR6 IE enables? - { - if(iwRisStatus & mskCT16_MR6IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR6IF; - SN_CT16B1->IC = mskCT16_MR6IC; //Clear MR6 match interrupt status - } - } - //MR7 - if (SN_CT16B1->MCTRL_b.MR7IE) //Check if MR7 IE enables? - { - if(iwRisStatus & mskCT16_MR7IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR7IF; - SN_CT16B1->IC = mskCT16_MR7IC; //Clear MR7 match interrupt status - } - } - //MR8 - if (SN_CT16B1->MCTRL_b.MR8IE) //Check if MR8 IE enables? - { - if(iwRisStatus & mskCT16_MR8IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR8IF; - SN_CT16B1->IC = mskCT16_MR8IC; //Clear MR8 match interrupt status - } - } - //MR9 - if (SN_CT16B1->MCTRL_b.MR9IE) //Check if MR9 IE enables? - { - if(iwRisStatus & mskCT16_MR9IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR9IF; - SN_CT16B1->IC = mskCT16_MR9IC; //Clear MR9 match interrupt status - } - } - //MR10 - if (SN_CT16B1->MCTRL2_b.MR10IE) //Check if MR10 IE enables? - { - if(iwRisStatus & mskCT16_MR10IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR10IF; - SN_CT16B1->IC = mskCT16_MR10IC; //Clear MR10 match interrupt status - } - } - //MR11 - if (SN_CT16B1->MCTRL2_b.MR11IE) //Check if MR11 IE enables? - { - if(iwRisStatus & mskCT16_MR11IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR11IF; - SN_CT16B1->IC = mskCT16_MR11IC; //Clear MR11 match interrupt status - } - } - //MR12 - if (SN_CT16B1->MCTRL2_b.MR12IE) //Check if MR12 IE enables? - { - if(iwRisStatus & mskCT16_MR12IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR12IF; - SN_CT16B1->IC = mskCT16_MR12IC; //Clear MR12 match interrupt status - } - } - //MR13 - if (SN_CT16B1->MCTRL2_b.MR13IE) //Check if MR13 IE enables? - { - if(iwRisStatus & mskCT16_MR13IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR13IF; - SN_CT16B1->IC = mskCT16_MR13IC; //Clear MR13 match interrupt status - } - } - //MR14 - if (SN_CT16B1->MCTRL2_b.MR14IE) //Check if MR14 IE enables? - { - if(iwRisStatus & mskCT16_MR14IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR14IF; - SN_CT16B1->IC = mskCT16_MR14IC; //Clear MR14 match interrupt status - } - } - //MR15 - if (SN_CT16B1->MCTRL2_b.MR15IE) //Check if MR15 IE enables? - { - if(iwRisStatus & mskCT16_MR15IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR15IF; - SN_CT16B1->IC = mskCT16_MR15IC; //Clear MR15 match interrupt status - } - } - //MR16 - if (SN_CT16B1->MCTRL2_b.MR16IE) //Check if MR16 IE enables? - { - if(iwRisStatus & mskCT16_MR16IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR16IF; - SN_CT16B1->IC = mskCT16_MR16IC; //Clear MR16 match interrupt status - } - } - //MR17 - if (SN_CT16B1->MCTRL2_b.MR17IE) //Check if MR17 IE enables? - { - if(iwRisStatus & mskCT16_MR17IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR17IF; - SN_CT16B1->IC = mskCT16_MR17IC; //Clear MR17 match interrupt status - } - } - //MR18 - if (SN_CT16B1->MCTRL2_b.MR18IE) //Check if MR18 IE enables? - { - if(iwRisStatus & mskCT16_MR18IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR18IF; - SN_CT16B1->IC = mskCT16_MR18IC; //Clear MR18 match interrupt status - } - } - //MR19 - if (SN_CT16B1->MCTRL2_b.MR19IE) //Check if MR19 IE enables? - { - if(iwRisStatus & mskCT16_MR19IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR19IF; - SN_CT16B1->IC = mskCT16_MR19IC; //Clear MR19 match interrupt status - } - } - //MR20 - if (SN_CT16B1->MCTRL3_b.MR20IE) //Check if MR20 IE enables? - { - if(iwRisStatus & mskCT16_MR20IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR20IF; - SN_CT16B1->IC = mskCT16_MR20IC; //Clear MR20 match interrupt status - } - } - //MR21 - if (SN_CT16B1->MCTRL3_b.MR21IE) //Check if MR21 IE enables? - { - if(iwRisStatus & mskCT16_MR21IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR21IF; - SN_CT16B1->IC = mskCT16_MR21IC; //Clear MR21 match interrupt status - } - } - //MR22 - if (SN_CT16B1->MCTRL3_b.MR22IE) //Check if MR22 IE enables? - { - if(iwRisStatus & mskCT16_MR22IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR22IF; - SN_CT16B1->IC = mskCT16_MR22IC; //Clear MR22 match interrupt status - } - } - //MR23 - if (SN_CT16B1->MCTRL3_b.MR23IE) //Check if MR23 IE enables? - { - if(iwRisStatus & mskCT16_MR23IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR23IF; - SN_CT16B1->IC = mskCT16_MR23IC; //Clear MR23 match interrupt status - } - } -#if SN32_CT16B1_CHANNELS > 23 - //MR24 - if (SN_CT16B1->MCTRL3_b.MR24IE) //Check if MR24 IE enables? - { - if(iwRisStatus & mskCT16_MR24IF) - { - iwCT16B1_IrqEvent |= mskCT16_MR24IF; - SN_CT16B1->IC = mskCT16_MR24IC; //Clear MR24 match interrupt status - } - } -#endif -} - - - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h deleted file mode 100644 index bd7ad6976b..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __SN32F2XX_CT16B1_H -#define __SN32F2XX_CT16B1_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt - //POLLING_METHOD: Enable CT16B1 timer ONLY - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS - -extern void CT16B1_Init(void); -extern void CT16B1_ResetTimer(void); -extern void CT16B1_NvicEnable(void); -extern void CT16B1_NvicDisable(void); -extern void CT16B1_IRQHandler(void); -#endif /*__SN32F2XX_CT16B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk index bc6c94ddfa..d7247a19e1 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk @@ -1,8 +1,4 @@ ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c -endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c endif @@ -10,8 +6,6 @@ ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c endif else -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c endif diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c index 4c37029cf6..37fc0c1fb4 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c @@ -29,7 +29,7 @@ /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ -#define GPT_CLK SN32_HCLK +# define GPT_CLK SN32_HCLK /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -38,17 +38,50 @@ * @brief GPTD1 driver identifier. * @note The driver GPTD1 allocates the complex timer CT16B0 when enabled. */ -#if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) +# if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) GPTDriver GPTD1; -#endif +# endif /** * @brief GPTD2 driver identifier. - * @note The driver GPTD2 allocates the timer CT16B1 when enabled. + * @note The driver GPTD2 allocates the complex timer CT16B1 when enabled. */ -#if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) +# if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) GPTDriver GPTD2; -#endif +# endif + +/** + * @brief GPTD3 driver identifier. + * @note The driver GPTD3 allocates the complex timer CT16B2 when enabled. + */ +# if SN32_GPT_USE_CT16B2 || defined(__DOXYGEN__) +GPTDriver GPTD3; +# endif + +/** + * @brief GPTD4 driver identifier. + * @note The driver GPTD4 allocates the complex timer CT16B3 when enabled. + */ +# if SN32_GPT_USE_CT16B3 || defined(__DOXYGEN__) +GPTDriver GPTD4; +# endif + +/** + * @brief GPTD5 driver identifier. + * @note The driver GPTD5 allocates the complex timer CT16B4 when enabled. + */ +# if SN32_GPT_USE_CT16B4 || defined(__DOXYGEN__) +GPTDriver GPTD5; +# endif + +/** + * @brief GPTD6 driver identifier. + * @note The driver GPTD6 allocates the complex timer CT16B5 when enabled. + */ +# if SN32_GPT_USE_CT16B5 || defined(__DOXYGEN__) +GPTDriver GPTD6; +# endif + /*===========================================================================*/ /* Driver local variables and types. */ @@ -62,47 +95,125 @@ GPTDriver GPTD2; /* Driver interrupt handlers. */ /*===========================================================================*/ -#if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) -#if !defined(SN32_CT16B0_SUPPRESS_ISR) -#if !defined(SN32_CT16B0_HANDLER) -#error "SN32_CT16B0_HANDLER not defined" -#endif +# if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B0_SUPPRESS_ISR) +# if !defined(SN32_CT16B0_HANDLER) +# error "SN32_CT16B0_HANDLER not defined" +# endif /** * @brief CT16B0 interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(SN32_CT16B0_HANDLER) { + OSAL_IRQ_PROLOGUE(); - OSAL_IRQ_PROLOGUE(); + gpt_lld_serve_interrupt(&GPTD1); - gpt_lld_serve_interrupt(&GPTD1); - - OSAL_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } -#endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ -#endif /* SN32_GPT_USE_CT16B0 */ - -#if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) -#if !defined(SN32_CT16B1_SUPPRESS_ISR) -#if !defined(SN32_CT16B1_HANDLER) -#error "SN32_CT16B1_HANDLER not defined" -#endif +# endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B0 */ + +# if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B1_SUPPRESS_ISR) +# if !defined(SN32_CT16B1_HANDLER) +# error "SN32_CT16B1_HANDLER not defined" +# endif /** * @brief CT16B1 interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { + OSAL_IRQ_PROLOGUE(); - OSAL_IRQ_PROLOGUE(); + gpt_lld_serve_interrupt(&GPTD2); - gpt_lld_serve_interrupt(&GPTD2); + OSAL_IRQ_EPILOGUE(); +} +# endif /* !defined(SN32_CT16B1_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B1 */ + +# if SN32_GPT_USE_CT16B2 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B2_SUPPRESS_ISR) +# if !defined(SN32_CT16B2_HANDLER) +# error "SN32_CT16B2_HANDLER not defined" +# endif +/** + * @brief CT16B2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + OSAL_IRQ_EPILOGUE(); +} +# endif /* !defined(SN32_CT16B2_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B2 */ + +# if SN32_GPT_USE_CT16B3 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B3_SUPPRESS_ISR) +# if !defined(SN32_CT16B3_HANDLER) +# error "SN32_CT16B3_HANDLER not defined" +# endif +/** + * @brief CT16B3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); - OSAL_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } -#endif /* !defined(SN32_CT16B1_SUPPRESS_ISR) */ -#endif /* SN32_GPT_USE_CT16B1 */ +# endif /* !defined(SN32_CT16B3_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B3 */ + +# if SN32_GPT_USE_CT16B4 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B4_SUPPRESS_ISR) +# if !defined(SN32_CT16B4_HANDLER) +# error "SN32_CT16B4_HANDLER not defined" +# endif +/** + * @brief CT16B4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B4_HANDLER) { + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD5); + + OSAL_IRQ_EPILOGUE(); +} +# endif /* !defined(SN32_CT16B4_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B4 */ + +# if SN32_GPT_USE_CT16B5 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B5_SUPPRESS_ISR) +# if !defined(SN32_CT16B5_HANDLER) +# error "SN32_CT16B5_HANDLER not defined" +# endif +/** + * @brief CT16B5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B5_HANDLER) { + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD6); + + OSAL_IRQ_EPILOGUE(); +} +# endif /* !defined(SN32_CT16B5_SUPPRESS_ISR) */ +# endif /* SN32_GPT_USE_CT16B5 */ /*===========================================================================*/ /* Driver exported functions. */ @@ -114,18 +225,30 @@ OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { * @notapi */ void gpt_lld_init(void) { - -#if SN32_GPT_USE_CT16B0 - /* Driver initialization.*/ - GPTD1.ct = SN32_CT16B0; - gptObjectInit(&GPTD1); -#endif - -#if SN32_GPT_USE_CT16B1 - /* Driver initialization.*/ - GPTD2.ct = SN32_CT16B1; - gptObjectInit(&GPTD2); -#endif +# if SN32_GPT_USE_CT16B0 + /* Driver initialization.*/ + gptObjectInit(&GPTD1); +# endif +# if SN32_GPT_USE_CT16B1 + /* Driver initialization.*/ + gptObjectInit(&GPTD2); +# endif +# if SN32_GPT_USE_CT16B2 + /* Driver initialization.*/ + gptObjectInit(&GPTD3); +# endif +# if SN32_GPT_USE_CT16B3 + /* Driver initialization.*/ + gptObjectInit(&GPTD4); +# endif +# if SN32_GPT_USE_CT16B4 + /* Driver initialization.*/ + gptObjectInit(&GPTD5); +# endif +# if SN32_GPT_USE_CT16B5 + /* Driver initialization.*/ + gptObjectInit(&GPTD6); +# endif } /** @@ -136,57 +259,115 @@ void gpt_lld_init(void) { * @notapi */ void gpt_lld_start(GPTDriver *gptp) { - uint16_t psc; - - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if SN32_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { - sys1EnableCT16B0(); - CT16B0_ResetTimer(); -#if !defined(SN32_CT16B0_SUPPRESS_ISR) - nvicEnableVector(SN32_CT16B0_NUMBER, SN32_GPT_CT16B0_IRQ_PRIORITY); -#endif - gptp->clock = GPT_CLK; + uint16_t psc; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +# if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + sys1EnableCT16B0(); + CT16B0_ResetTimer(); +# if !defined(SN32_CT16B0_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B0_NUMBER, SN32_GPT_CT16B0_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif +# if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + sys1EnableCT16B1(); + CT16B1_ResetTimer(); +# if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B1_NUMBER, SN32_GPT_CT16B1_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif +# if SN32_GPT_USE_CT16B2 + if (&GPTD3 == gptp) { + sys1EnableCT16B2(); + CT16B2_ResetTimer(); +# if !defined(SN32_CT16B2_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B2_NUMBER, SN32_GPT_CT16B2_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif +# if SN32_GPT_USE_CT16B3 + if (&GPTD4 == gptp) { + sys1EnableCT16B3(); + CT16B3_ResetTimer(); +# if !defined(SN32_CT16B3_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B3_NUMBER, SN32_GPT_CT16B3_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif +# if SN32_GPT_USE_CT16B4 + if (&GPTD5 == gptp) { + sys1EnableCT16B4(); + CT16B4_ResetTimer(); +# if !defined(SN32_CT16B4_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B4_NUMBER, SN32_GPT_CT16B4_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif +# if SN32_GPT_USE_CT16B5 + if (&GPTD6 == gptp) { + sys1EnableCT16B5(); + CT16B6_ResetTimer(); +# if !defined(SN32_CT16B5_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B5_NUMBER, SN32_GPT_CT16B5_IRQ_PRIORITY); +# endif + gptp->clock = GPT_CLK; + } +# endif + } else { + /* Driver re-configuration scenario, it must be stopped first.*/ + SN32_CT_GPT_SET(gptp, config.TMRCTRL, CT16_CEN_DIS); /* Timer disabled.*/ +# if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + CT16B0_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + CT16B1_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B2 + if (&GPTD3 == gptp) { + CT16B2_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B3 + if (&GPTD4 == gptp) { + CT16B3_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B4 + if (&GPTD5 == gptp) { + CT16B4_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B5 + if (&GPTD6 == gptp) { + CT16B4_ResetTimer(); /* Counter reset to zero.*/ + } +# endif } -#endif -#if SN32_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { - sys1EnableCT16B1(); - CT16B1_ResetTimer(); -#if !defined(SN32_CT16B1_SUPPRESS_ISR) - nvicEnableVector(SN32_CT16B1_NUMBER, SN32_GPT_CT16B1_IRQ_PRIORITY); -#endif - gptp->clock = GPT_CLK; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ -#if SN32_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { - CT16B0_ResetTimer(); /* Counter reset to zero. */ - } -#endif -#if SN32_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { - CT16B1_ResetTimer(); /* Counter reset to zero. */ - } -#endif - } - - /* Prescaler value calculation.*/ - psc = ((gptp->clock / gptp->config->frequency) - 1); - osalDbgAssert((psc <= 0xFF) && /* Prescaler calculation. */ - ((psc + 1) * gptp->config->frequency) == gptp->clock, - "invalid frequency"); - - /* Timer configuration.*/ - gptp->ct->CNTCTRL = gptp->config->cntctrl; - gptp->ct->PRE = psc; /* Prescaler value. */ - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + /* Prescaler value calculation.*/ + psc = ((gptp->clock / gptp->config->frequency) - 1); + osalDbgAssert((psc <= SN32_CT16_PRE_LIMIT) && /* Prescaler calculation.*/ + ((psc + 1) * gptp->config->frequency) == gptp->clock, + "invalid frequency"); + + /* Timer configuration.*/ + SN32_CT_GPT_SET(gptp, config.CNTCTRL, gptp->config->cntctrl); + SN32_CT_GPT_SET(gptp, config.PRE, psc); /* Prescaler value.*/ + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ } /** @@ -197,29 +378,59 @@ void gpt_lld_start(GPTDriver *gptp) { * @notapi */ void gpt_lld_stop(GPTDriver *gptp) { - - if (gptp->state == GPT_READY) { - gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ - -#if SN32_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { -#if !defined(SN32_CT16B0_SUPPRESS_ISR) - nvicDisableVector(SN32_CT16B0_NUMBER); -#endif - sys1DisableCT16B0(); - } -#endif - -#if SN32_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { -#if !defined(SN32_CT16B1_SUPPRESS_ISR) - nvicDisableVector(SN32_CT16B1_NUMBER); -#endif - sys1DisableCT16B1(); + if (gptp->state == GPT_READY) { + SN32_CT_GPT_SET(gptp, config.TMRCTRL, CT16_CEN_DIS); /* Timer disabled.*/ + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ + +# if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { +# if !defined(SN32_CT16B0_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B0_NUMBER); +# endif + sys1DisableCT16B0(); + } +# endif +# if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { +# if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B1_NUMBER); +# endif + sys1DisableCT16B1(); + } +# endif +# if SN32_GPT_USE_CT16B2 + if (&GPTD3 == gptp) { +# if !defined(SN32_CT16B2_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B2_NUMBER); +# endif + sys1DisableCT16B2(); + } +# endif +# if SN32_GPT_USE_CT16B3 + if (&GPTD4 == gptp) { +# if !defined(SN32_CT16B3_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B3_NUMBER); +# endif + sys1DisableCT16B3(); + } +# endif +# if SN32_GPT_USE_CT16B4 + if (&GPTD5 == gptp) { +# if !defined(SN32_CT16B4_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B4_NUMBER); +# endif + sys1DisableCT16B4(); + } +# endif +# if SN32_GPT_USE_CT16B5 + if (&GPTD5 == gptp) { +# if !defined(SN32_CT16B5_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B5_NUMBER); +# endif + sys1DisableCT16B5(); + } +# endif } -#endif - } } /** @@ -231,22 +442,56 @@ void gpt_lld_stop(GPTDriver *gptp) { * @notapi */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - - gptp->ct->MR0 = (uint32_t)(interval - 1U); /* Time constant. */ -#if SN32_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { - CT16B0_ResetTimer(); /* Counter reset to zero. */ - } -#endif -#if SN32_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { - CT16B1_ResetTimer(); /* Counter reset to zero. */ - } -#endif - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ - if (NULL != gptp->config->callback) - gptp->ct->MCTRL |= mskCT16_MR0IE_EN; - gptp->ct->TMRCTRL |= mskCT16_CEN_EN; +# if ( (defined(SN32F280) || defined(SN32F290)) && \ + (defined(SN32_GPT_USE_CT16B0) || defined(SN32_GPT_USE_CT16B2) || \ + defined(SN32_GPT_USE_CT16B3) || defined(SN32_GPT_USE_CT16B4) || \ + defined(SN32_GPT_USE_CT16B5)) ) + SN32_CT_GPT_SET(gptp, MR[0], CT16_PWM_UNLOCK(interval - 1U)); /* Time constant.*/ +# else + SN32_CT_GPT_SET(gptp, MR[0], (interval - 1U)); /* Time constant.*/ +# endif +# if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + CT16B0_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + CT16B1_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B2 + if (&GPTD3 == gptp) { + CT16B2_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B3 + if (&GPTD4 == gptp) { + CT16B3_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B4 + if (&GPTD5 == gptp) { + CT16B4_ResetTimer(); /* Counter reset to zero.*/ + } +# endif +# if SN32_GPT_USE_CT16B5 + if (&GPTD6 == gptp) { + CT16B5_ResetTimer(); /* Counter reset to zero.*/ + } +# endif + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ + if (NULL != gptp->config->callback) +# if ( (defined(SN32F280) || defined(SN32F290)) && \ + (defined(SN32_GPT_USE_CT16B0) || defined(SN32_GPT_USE_CT16B2) || \ + defined(SN32_GPT_USE_CT16B3) || defined(SN32_GPT_USE_CT16B4) || \ + defined(SN32_GPT_USE_CT16B5)) ) + SN32_CT_GPT_OR(gptp, match.MCTRL, CT16_PWM_UNLOCK(mskCT16_MRnIE_EN(0))); +# else + SN32_CT_GPT_OR(gptp, match.MCTRL, mskCT16_MRnIE_EN(0)); +# endif + + SN32_CT_GPT_OR(gptp, config.TMRCTRL, mskCT16_CEN_EN); } /** @@ -257,11 +502,16 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { * @notapi */ void gpt_lld_stop_timer(GPTDriver *gptp) { - - gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Initially stopped. */ - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ - gptp->ct->MCTRL &= ~mskCT16_MR0IE_EN; /* Disable the interrupt */ - + SN32_CT_GPT_SET(gptp, config.TMRCTRL, CT16_CEN_DIS); /* Initially stopped.*/ + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ +# if ( (defined(SN32F280) || defined(SN32F290)) && \ + (defined(SN32_GPT_USE_CT16B0) || defined(SN32_GPT_USE_CT16B2) || \ + defined(SN32_GPT_USE_CT16B3) || defined(SN32_GPT_USE_CT16B4) || \ + defined(SN32_GPT_USE_CT16B5)) ) + SN32_CT_GPT_SET(gptp, match.MCTRL, (SN32_CT_GPT_GET(gptp, match.MCTRL) & ~mskCT16_MRnIE_EN(0))); /* Disable the interrupt */ +# else + SN32_CT_GPT_AND(gptp, match.MCTRL, ~mskCT16_MRnIE_EN(0)); /* Disable the interrupt*/ +# endif } /** @@ -276,14 +526,21 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { * @notapi */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - - gptp->ct->MR0 = (uint32_t)(interval - 1U); /* Time constant. */ - gptp->ct->MCTRL = (mskCT16_MR0IE_EN | mskCT16_MR0STOP_EN); - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ - gptp->ct->TMRCTRL |= mskCT16_CEN_EN; - while ((gptp->ct->RIS & mskCT16_MR0IF)!= 0) - ; - gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ +# if ( (defined(SN32F280) || defined(SN32F290)) && \ + (defined(SN32_GPT_USE_CT16B0) || defined(SN32_GPT_USE_CT16B2) || \ + defined(SN32_GPT_USE_CT16B3) || defined(SN32_GPT_USE_CT16B4) || \ + defined(SN32_GPT_USE_CT16B5)) ) + SN32_CT_GPT_SET(gptp, MR[0], CT16_PWM_UNLOCK(interval - 1U)); /* Time constant.*/ + SN32_CT_GPT_SET(gptp, match.MCTRL, CT16_PWM_UNLOCK(mskCT16_MRnIE_EN(0) | mskCT16_MRnSTOP_EN(0))); +# else + SN32_CT_GPT_SET(gptp, MR[0], (interval - 1U)); /* Time constant.*/ + SN32_CT_GPT_SET(gptp, match.MCTRL, (mskCT16_MRnIE_EN(0) | mskCT16_MRnSTOP_EN(0))); +# endif + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ + SN32_CT_GPT_OR(gptp, config.TMRCTRL, mskCT16_CEN_EN); + while ((SN32_CT_GPT_GET(gptp, irq.RIS) & mskCT16_MRnIF(0)) != 0) + ; + SN32_CT_GPT_AND(gptp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ } /** @@ -294,12 +551,11 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { * @notapi */ void gpt_lld_serve_interrupt(GPTDriver *gptp) { - uint32_t ris; + uint32_t ris; - ris = gptp->ct->RIS; - gptp->ct->IC = ris; - if ((ris & mskCT16_MR0IF) != 0) - _gpt_isr_invoke_cb(gptp); + ris = SN32_CT_GPT_GET(gptp, irq.RIS); + SN32_CT_GPT_SET(gptp, irq.IC, ris); + if ((ris & mskCT16_MRnIF(0)) != 0) _gpt_isr_invoke_cb(gptp); } #endif /* HAL_USE_GPT */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h index 5d4870e3fb..2e6104d0b6 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h @@ -59,6 +59,42 @@ #define SN32_GPT_USE_CT16B1 FALSE #endif +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B2) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B2 FALSE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B3) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B3 FALSE +#endif + +/** + * @brief GPTD5 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B4) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B4 FALSE +#endif + +/** + * @brief GPTD6 driver enable switch. + * @details If set to @p TRUE the support for GPTD6 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B5) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B5 FALSE +#endif + /** * @brief GPTD1 interrupt priority level setting. */ @@ -72,20 +108,40 @@ #if !defined(SN32_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define SN32_GPT_CT16B1_IRQ_PRIORITY 3 #endif -/** @} */ -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/** + * @brief GPTD3 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B2_IRQ_PRIORITY 3 +#endif -#if !defined(SN32_HAS_CT16B0) -#define SN32_HAS_CT16B0 FALSE +/** + * @brief GPTD4 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B3_IRQ_PRIORITY 3 #endif -#if !defined(SN32_HAS_CT16B1) -#define SN32_HAS_CT16B1 FALSE +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B4_IRQ_PRIORITY 3 #endif +/** + * @brief GPTD6 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B5_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + #if SN32_GPT_USE_CT16B0 && !SN32_HAS_CT16B0 #error "CT16B0 not present in the selected device" #endif @@ -94,8 +150,28 @@ #error "CT16B1 not present in the selected device" #endif +#if SN32_GPT_USE_CT16B2 && !SN32_HAS_CT16B2 +#error "CT16B2 not present in the selected device" +#endif + +#if SN32_GPT_USE_CT16B3 && !SN32_HAS_CT16B3 +#error "CT16B3 not present in the selected device" +#endif + +#if SN32_GPT_USE_CT16B4 && !SN32_HAS_CT16B4 +#error "CT16B4 not present in the selected device" +#endif + +#if SN32_GPT_USE_CT16B5 && !SN32_HAS_CT16B5 +#error "CT16B5 not present in the selected device" +#endif + #if !SN32_GPT_USE_CT16B0 && !SN32_GPT_USE_CT16B0 && \ - !SN32_GPT_USE_CT16B1 && !SN32_GPT_USE_CT16B1 + !SN32_GPT_USE_CT16B1 && !SN32_GPT_USE_CT16B1 && \ + !SN32_GPT_USE_CT16B2 && !SN32_GPT_USE_CT16B2 && \ + !SN32_GPT_USE_CT16B3 && !SN32_GPT_USE_CT16B3 && \ + !SN32_GPT_USE_CT16B4 && !SN32_GPT_USE_CT16B4 && \ + !SN32_GPT_USE_CT16B5 && !SN32_GPT_USE_CT16B5 #error "GPT driver activated but no CT16 peripheral assigned" #endif @@ -116,6 +192,38 @@ #endif #endif +#if SN32_GPT_USE_CT16B2 +#if defined(SN32_CT16B2_IS_USED) +#error "GPTD3 requires CT16B2 but the timer is already used" +#else +#define SN32_CT16B2_IS_USED +#endif +#endif + +#if SN32_GPT_USE_CT16B3 +#if defined(SN32_CT16B3_IS_USED) +#error "GPTD4 requires CT16B3 but the timer is already used" +#else +#define SN32_CT16B3_IS_USED +#endif +#endif + +#if SN32_GPT_USE_CT16B4 +#if defined(SN32_CT16B4_IS_USED) +#error "GPTD5 requires CT16B4 but the timer is already used" +#else +#define SN32_CT16B4_IS_USED +#endif +#endif + +#if SN32_GPT_USE_CT16B5 +#if defined(SN32_CT16B5_IS_USED) +#error "GPTD6 requires CT16B5 but the timer is already used" +#else +#define SN32_CT16B5_IS_USED +#endif +#endif + /* IRQ priority checks.*/ #if SN32_GPT_USE_CT16B0 && !defined(SN32_CT16B0_SUPPRESS_ISR) && \ !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B0_IRQ_PRIORITY) @@ -127,6 +235,26 @@ #error "Invalid IRQ priority assigned to CT16B1" #endif +#if SN32_GPT_USE_CT16B2 && !defined(SN32_CT16B2_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B2" +#endif + +#if SN32_GPT_USE_CT16B3 && !defined(SN32_CT16B3_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B3" +#endif + +#if SN32_GPT_USE_CT16B4 && !defined(SN32_CT16B4_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B4" +#endif + +#if SN32_GPT_USE_CT16B5 && !defined(SN32_CT16B5_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B5" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -139,7 +267,7 @@ typedef uint32_t gptfreq_t; /** * @brief GPT counter type. */ -typedef uint32_t gptcnt_t; +typedef uint16_t gptcnt_t; /** * @brief Driver configuration structure. @@ -187,15 +315,284 @@ struct GPTDriver { * @brief Timer base clock. */ uint32_t clock; - /** - * @brief Pointer to the CT registers block. - */ - sn32_ct_t *ct; }; /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ +#if SN32_GPT_USE_CT16B0 +#define SN32_CT_GPT_SET_CT16B0(timer, field, value) \ + do { if ((timer) == &GPTD1) SN32_CT_GPT_SET_TIMER(SN32_CT16B0, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B0(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B1 +#define SN32_CT_GPT_SET_CT16B1(timer, field, value) \ + do { if ((timer) == &GPTD2) SN32_CT_GPT_SET_TIMER(SN32_CT16B1, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B1(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B2 +#define SN32_CT_GPT_SET_CT16B2(timer, field, value) \ + do { if ((timer) == &GPTD3) SN32_CT_GPT_SET_TIMER(SN32_CT16B2, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B2(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B3 +#define SN32_CT_GPT_SET_CT16B3(timer, field, value) \ + do { if ((timer) == &GPTD4) SN32_CT_GPT_SET_TIMER(SN32_CT16B3, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B3(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B4 +#define SN32_CT_GPT_SET_CT16B4(timer, field, value) \ + do { if ((timer) == &GPTD5) SN32_CT_GPT_SET_TIMER(SN32_CT16B4, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B4(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B5 +#define SN32_CT_GPT_SET_CT16B5(timer, field, value) \ + do { if ((timer) == &GPTD6) SN32_CT_GPT_SET_TIMER(SN32_CT16B5, field, value); } while (0) +#else +#define SN32_CT_GPT_SET_CT16B5(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_GPT_SET_TIMER(timer, field, value) \ + do { \ + (timer)->field = (value); \ + } while (0) + +#define SN32_CT_GPT_SET(timer, field, value) \ + do { \ + SN32_CT_GPT_SET_CT16B0(timer, field, value); \ + SN32_CT_GPT_SET_CT16B1(timer, field, value); \ + SN32_CT_GPT_SET_CT16B2(timer, field, value); \ + SN32_CT_GPT_SET_CT16B3(timer, field, value); \ + SN32_CT_GPT_SET_CT16B4(timer, field, value); \ + SN32_CT_GPT_SET_CT16B5(timer, field, value); \ + } while (0) + +#if SN32_GPT_USE_CT16B0 +#define SN32_CT_GPT_OR_CT16B0(timer, field, value) \ + do { if ((timer) == &GPTD1) SN32_CT_GPT_OR_TIMER(SN32_CT16B0, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B0(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B1 +#define SN32_CT_GPT_OR_CT16B1(timer, field, value) \ + do { if ((timer) == &GPTD2) SN32_CT_GPT_OR_TIMER(SN32_CT16B1, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B1(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B2 +#define SN32_CT_GPT_OR_CT16B2(timer, field, value) \ + do { if ((timer) == &GPTD3) SN32_CT_GPT_OR_TIMER(SN32_CT16B2, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B2(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B3 +#define SN32_CT_GPT_OR_CT16B3(timer, field, value) \ + do { if ((timer) == &GPTD4) SN32_CT_GPT_OR_TIMER(SN32_CT16B3, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B3(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B4 +#define SN32_CT_GPT_OR_CT16B4(timer, field, value) \ + do { if ((timer) == &GPTD5) SN32_CT_GPT_OR_TIMER(SN32_CT16B4, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B4(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B5 +#define SN32_CT_GPT_OR_CT16B5(timer, field, value) \ + do { if ((timer) == &GPTD6) SN32_CT_GPT_OR_TIMER(SN32_CT16B5, field, value); } while (0) +#else +#define SN32_CT_GPT_OR_CT16B5(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_GPT_OR_TIMER(timer, field, value) \ + do { \ + (timer)->field |= (value); \ + } while (0) + +#define SN32_CT_GPT_OR(timer, field, value) \ + do { \ + SN32_CT_GPT_OR_CT16B0(timer, field, value); \ + SN32_CT_GPT_OR_CT16B1(timer, field, value); \ + SN32_CT_GPT_OR_CT16B2(timer, field, value); \ + SN32_CT_GPT_OR_CT16B3(timer, field, value); \ + SN32_CT_GPT_OR_CT16B4(timer, field, value); \ + SN32_CT_GPT_OR_CT16B5(timer, field, value); \ + } while (0) + +#if SN32_GPT_USE_CT16B0 +#define SN32_CT_GPT_AND_CT16B0(timer, field, value) \ + do { if ((timer) == &GPTD1) SN32_CT_GPT_AND_TIMER(SN32_CT16B0, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B0(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B1 +#define SN32_CT_GPT_AND_CT16B1(timer, field, value) \ + do { if ((timer) == &GPTD2) SN32_CT_GPT_AND_TIMER(SN32_CT16B1, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B1(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B2 +#define SN32_CT_GPT_AND_CT16B2(timer, field, value) \ + do { if ((timer) == &GPTD3) SN32_CT_GPT_AND_TIMER(SN32_CT16B2, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B2(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B3 +#define SN32_CT_GPT_AND_CT16B3(timer, field, value) \ + do { if ((timer) == &GPTD4) SN32_CT_GPT_AND_TIMER(SN32_CT16B3, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B3(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B4 +#define SN32_CT_GPT_AND_CT16B4(timer, field, value) \ + do { if ((timer) == &GPTD5) SN32_CT_GPT_AND_TIMER(SN32_CT16B4, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B4(timer, field, value) \ + do { } while (0) +#endif +#if SN32_GPT_USE_CT16B5 +#define SN32_CT_GPT_AND_CT16B5(timer, field, value) \ + do { if ((timer) == &GPTD6) SN32_CT_GPT_AND_TIMER(SN32_CT16B5, field, value); } while (0) +#else +#define SN32_CT_GPT_AND_CT16B5(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_GPT_AND_TIMER(timer, field, value) \ + do { \ + (timer)->field &= (value); \ + } while (0) + +#define SN32_CT_GPT_AND(timer, field, value) \ + do { \ + SN32_CT_GPT_AND_CT16B0(timer, field, value); \ + SN32_CT_GPT_AND_CT16B1(timer, field, value); \ + SN32_CT_GPT_AND_CT16B2(timer, field, value); \ + SN32_CT_GPT_AND_CT16B3(timer, field, value); \ + SN32_CT_GPT_AND_CT16B4(timer, field, value); \ + SN32_CT_GPT_AND_CT16B5(timer, field, value); \ + } while (0) + +#if SN32_GPT_USE_CT16B0 +# define SN32_CT_GPT_GET_CT16B0(timer, field) \ + ((timer) == &GPTD1 ? (SN32_CT16B0)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B0(timer, field) (0) +#endif +#if SN32_GPT_USE_CT16B1 +# define SN32_CT_GPT_GET_CT16B1(timer, field) \ + ((timer) == &GPTD2 ? (SN32_CT16B1)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B1(timer, field) (0) +#endif +#if SN32_GPT_USE_CT16B2 +# define SN32_CT_GPT_GET_CT16B2(timer, field) \ + ((timer) == &GPTD3 ? (SN32_CT16B2)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B2(timer, field) (0) +#endif +#if SN32_GPT_USE_CT16B3 +# define SN32_CT_GPT_GET_CT16B3(timer, field) \ + ((timer) == &GPTD4 ? (SN32_CT16B3)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B3(timer, field) (0) +#endif +#if SN32_GPT_USE_CT16B4 +# define SN32_CT_GPT_GET_CT16B4(timer, field) \ + ((timer) == &GPTD5 ? (SN32_CT16B4)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B4(timer, field) (0) +#endif +#if SN32_GPT_USE_CT16B5 +# define SN32_CT_GPT_GET_CT16B5(timer, field) \ + ((timer) == &GPTD6 ? (SN32_CT16B5)->field : 0) +#else +# define SN32_CT_GPT_GET_CT16B5(timer, field) (0) +#endif + +#define SN32_CT_GPT_GET(timer, field) \ + (SN32_CT_GPT_GET_CT16B0(timer, field) | \ + SN32_CT_GPT_GET_CT16B1(timer, field) | \ + SN32_CT_GPT_GET_CT16B2(timer, field) | \ + SN32_CT_GPT_GET_CT16B3(timer, field) | \ + SN32_CT_GPT_GET_CT16B4(timer, field) | \ + SN32_CT_GPT_GET_CT16B5(timer, field)) + +#if SN32_GPT_USE_CT16B0 +# define SN32_CT_GPT_GET_ADDR_CT16B0(timer, field) \ + ((timer) == &GPTD1 ? &((SN32_CT16B0)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B0(timer, field) (NULL) +#endif + +#if SN32_GPT_USE_CT16B1 +# define SN32_CT_GPT_GET_ADDR_CT16B1(timer, field) \ + ((timer) == &GPTD2 ? &((SN32_CT16B1)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B1(timer, field) (NULL) +#endif + +#if SN32_GPT_USE_CT16B2 +# define SN32_CT_GPT_GET_ADDR_CT16B2(timer, field) \ + ((timer) == &GPTD3 ? &((SN32_CT16B2)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B2(timer, field) (NULL) +#endif + +#if SN32_GPT_USE_CT16B3 +# define SN32_CT_GPT_GET_ADDR_CT16B3(timer, field) \ + ((timer) == &GPTD4 ? &((SN32_CT16B3)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B3(timer, field) (NULL) +#endif + +#if SN32_GPT_USE_CT16B4 +# define SN32_CT_GPT_GET_ADDR_CT16B4(timer, field) \ + ((timer) == &GPTD5 ? &((SN32_CT16B4)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B4(timer, field) (NULL) +#endif + +#if SN32_GPT_USE_CT16B5 +# define SN32_CT_GPT_GET_ADDR_CT16B5(timer, field) \ + ((timer) == &GPTD6 ? &((SN32_CT16B5)->field) : NULL) +#else +# define SN32_CT_GPT_GET_ADDR_CT16B5(timer, field) (NULL) +#endif + +#define SN32_CT_GPT_GET_ADDR(timer, field) \ + (SN32_CT_GPT_GET_ADDR_CT16B0(timer, field) ? \ + SN32_CT_GPT_GET_ADDR_CT16B0(timer, field) : \ + (SN32_CT_GPT_GET_ADDR_CT16B1(timer, field) ? \ + SN32_CT_GPT_GET_ADDR_CT16B1(timer, field) : \ + (SN32_CT_GPT_GET_ADDR_CT16B2(timer, field) ? \ + SN32_CT_GPT_GET_ADDR_CT16B2(timer, field) : \ + (SN32_CT_GPT_GET_ADDR_CT16B3(timer, field) ? \ + SN32_CT_GPT_GET_ADDR_CT16B3(timer, field) : \ + (SN32_CT_GPT_GET_ADDR_CT16B4(timer, field) ? \ + SN32_CT_GPT_GET_ADDR_CT16B4(timer, field) : \ + SN32_CT_GPT_GET_ADDR_CT16B5(timer, field)))))) /** * @brief Changes the interval of GPT peripheral. @@ -209,9 +606,16 @@ struct GPTDriver { * * @notapi */ +#if ( (defined(SN32F280) || defined(SN32F290)) && \ + (defined(SN32_GPT_USE_CT16B0) || defined(SN32_GPT_USE_CT16B2) || \ + defined(SN32_GPT_USE_CT16B3) || defined(SN32_GPT_USE_CT16B4) || \ + defined(SN32_GPT_USE_CT16B5)) ) #define gpt_lld_change_interval(gptp, interval) \ - ((gptp)->ct->MR0 = (uint32_t)((interval) - 1U)) - + SN32_CT_GPT_SET((gptp), MR[0], CT16_PWM_UNLOCK((interval) - 1U)) +#else +#define gpt_lld_change_interval(gptp, interval) \ + SN32_CT_GPT_SET((gptp), MR[0], ((interval) - 1U)) +#endif /** * @brief Returns the interval of GPT peripheral. * @pre The GPT unit must be running in continuous mode. @@ -221,7 +625,7 @@ struct GPTDriver { * * @notapi */ -#define gpt_lld_get_interval(gptp) ((gptcnt_t)((gptp)->ct->MR0 + 1U)) +#define gpt_lld_get_interval(gptp) (gptcnt_t)(SN32_CT_GPT_GET((gptp), MR[0] & SN32_CT16_TC_LIMIT) + 1U) /** * @brief Returns the counter value of GPT peripheral. @@ -234,7 +638,7 @@ struct GPTDriver { * * @notapi */ -#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->ct->TC) +#define gpt_lld_get_counter(gptp) (gptcnt_t)SN32_CT_GPT_GET((gptp), config.TC) /*===========================================================================*/ /* External declarations. */ @@ -248,6 +652,22 @@ extern GPTDriver GPTD1; extern GPTDriver GPTD2; #endif +#if SN32_GPT_USE_CT16B2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if SN32_GPT_USE_CT16B3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#if SN32_GPT_USE_CT16B4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD5; +#endif + +#if SN32_GPT_USE_CT16B5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD6; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c index 300d554209..12e366e9c3 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c @@ -29,7 +29,7 @@ /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ -#define PWM_CLK SN32_HCLK +# define PWM_CLK SN32_HCLK /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -38,9 +38,9 @@ * @brief PWMD1 driver identifier. * @note The driver PWMD1 allocates the complex timer CT16B1 when enabled. */ -#if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) +# if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) PWMDriver PWMD1; -#endif +# endif /*===========================================================================*/ /* Driver local variables and types. */ @@ -54,26 +54,25 @@ PWMDriver PWMD1; /* Driver interrupt handlers. */ /*===========================================================================*/ -#if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) -#if !defined(SN32_CT16B1_SUPPRESS_ISR) -#if !defined(SN32_CT16B1_HANDLER) -#error "SN32_CT16B1_HANDLER not defined" -#endif +# if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) +# if !defined(SN32_CT16B1_SUPPRESS_ISR) +# if !defined(SN32_CT16B1_HANDLER) +# error "SN32_CT16B1_HANDLER not defined" +# endif /** * @brief CT16B1 interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { + OSAL_IRQ_PROLOGUE(); - OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD1); - pwm_lld_serve_interrupt(&PWMD1); - - OSAL_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } -#endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ -#endif /* SN32_PWM_USE_CT16B1 */ +# endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ +# endif /* SN32_PWM_USE_CT16B1 */ /*===========================================================================*/ /* Driver exported functions. */ @@ -85,13 +84,11 @@ OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { * @notapi */ void pwm_lld_init(void) { - -#if SN32_PWM_USE_CT16B1 - /* Driver initialization.*/ - pwmObjectInit(&PWMD1); - PWMD1.channels = PWM_CHANNELS; - PWMD1.ct = SN32_CT16B1; -#endif +# if SN32_PWM_USE_CT16B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.channels = PWM_CHANNELS; +# endif } /** @@ -104,369 +101,96 @@ void pwm_lld_init(void) { * @notapi */ void pwm_lld_start(PWMDriver *pwmp) { - uint32_t psc; - uint32_t pwmctrl; - uint32_t pwmctrl2; - uint32_t pwmen; - uint32_t pwmioen; - - if (pwmp->state == PWM_STOP) { - /* Clock activation and timer reset.*/ -#if SN32_PWM_USE_CT16B1 - if (&PWMD1 == pwmp) { - sys1EnableCT16B1(); - CT16B1_ResetTimer(); -#if !defined(SN32_CT16B1_SUPPRESS_ISR) - nvicEnableVector(SN32_CT16B1_NUMBER, SN32_PWM_CT16B1_IRQ_PRIORITY); -#endif - pwmp->clock = PWM_CLK; + uint32_t psc; + uint32_t pwmctrl; + uint32_t pwmctrl2; + uint32_t pwmen; + uint32_t pwmioen; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +# if SN32_PWM_USE_CT16B1 + if (&PWMD1 == pwmp) { + sys1EnableCT16B1(); + CT16B1_ResetTimer(); +# if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B1_NUMBER, SN32_PWM_CT16B1_IRQ_PRIORITY); +# endif + pwmp->clock = PWM_CLK; + } +# endif + +# if (defined(SN32F240B) || defined(SN32F240C)) + /* PFPA - Map all PWM outputs to their PWM A pins */ + SN_PFPA->CT16B1 = 0x00000000; + /* PFPA assignment for PWM B-pin mapping.*/ + for (uint8_t i = 0; i < PWM_CHANNELS; i++) { + if (pwmp->config->channels[i].pfpamsk != 0) { + SN_PFPA->CT16B1 |= (1 << i); + } + } +# endif + + /* Channel PWM mode selection and polarities setup.*/ + pwmctrl = 0; + pwmctrl2 = 0; + pwmen = 0; + pwmioen = 0; + volatile uint32_t *pwmctrl_registers[] = {&pwmctrl, &pwmctrl2}; + for (uint8_t i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + *pwmctrl_registers[(i > 15) ? 1 : 0] |= mskCT16_PWMnMODE_1(i); + pwmen |= mskCT16_PWMnEN_EN(i); + pwmioen |= mskCT16_PWMnIOEN_EN(i); + break; + case PWM_OUTPUT_ACTIVE_HIGH: + *pwmctrl_registers[(i > 15) ? 1 : 0] |= mskCT16_PWMnMODE_2(i); + pwmen |= mskCT16_PWMnEN_EN(i); + pwmioen |= mskCT16_PWMnIOEN_EN(i); + break; + } + } + SN32_CT_PWM_SET(pwmp, pwm.PWMCTRL, pwmctrl); + SN32_CT_PWM_SET(pwmp, pwm.PWMCTRL2, pwmctrl2); + SN32_CT_PWM_SET(pwmp, pwm.PWMENB, pwmen); + SN32_CT_PWM_SET(pwmp, pwm.PWMIOENB, pwmioen); + } else { + /* Driver re-configuration scenario, it must be stopped first.*/ + SN32_CT_PWM_SET(pwmp, config.TMRCTRL, CT16_CEN_DIS); /* Timer disabled.*/ + /* Counter reset to zero.*/ + SN32_CT_PWM_SET(pwmp, config.TMRCTRL, mskCT16_CRST); // Set CT16B1 as the up-counting mode. + while (SN32_CT_PWM_GET(pwmp, config.TMRCTRL) & mskCT16_CRST) + ; // Wait until timer reset done. } -#endif -#if defined(SN32F240B) - /* PFPA - Map all PWM outputs to their PWM A pins */ - SN_PFPA->CT16B1 = 0x00000000; - /* PFPA assignment for PWM B-pin mapping.*/ - for(uint8_t i=0; iconfig->channels[i].pfpamsk != 0) { - SN_PFPA->CT16B1 |= (1<clock / pwmp->config->frequency) - 1; + osalDbgAssert((psc <= SN32_CT16_PRE_LIMIT) && /* Prescaler calculation.*/ + ((psc + 1) * pwmp->config->frequency) == pwmp->clock, + "invalid frequency"); + SN32_CT_PWM_SET(pwmp, config.PRE, psc); + SN32_CT_PWM_SET(pwmp, MR[PWM_CHANNELS], pwmp->period - 1); + +# if SN32_PWM_USE_ONESHOT || defined(__DOXYGEN__) + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg |= mskCT16_MRnSTOP_EN(PWM_CHANNELS); } - } -#endif - - /* Channel PWM mode selection and polarities setup.*/ - pwmctrl = 0; - pwmctrl2 = 0; - pwmen = 0; - pwmioen = 0; - switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM0MODE_1; - pwmen |= mskCT16_PWM0EN_EN; - pwmioen |= mskCT16_PWM0IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM0MODE_2; - pwmen |= mskCT16_PWM0EN_EN; - pwmioen |= mskCT16_PWM0IOEN_EN; - break; - } - switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM1MODE_1; - pwmen |= mskCT16_PWM1EN_EN; - pwmioen |= mskCT16_PWM1IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM1MODE_2; - pwmen |= mskCT16_PWM1EN_EN; - pwmioen |= mskCT16_PWM1IOEN_EN; - break; - } - switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM2MODE_1; - pwmen |= mskCT16_PWM2EN_EN; - pwmioen |= mskCT16_PWM2IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM2MODE_2; - pwmen |= mskCT16_PWM2EN_EN; - pwmioen |= mskCT16_PWM2IOEN_EN; - break; - } - switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM3MODE_1; - pwmen |= mskCT16_PWM3EN_EN; - pwmioen |= mskCT16_PWM3IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM3MODE_2; - pwmen |= mskCT16_PWM3EN_EN; - pwmioen |= mskCT16_PWM3IOEN_EN; - break; - } - switch (pwmp->config->channels[4].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM4MODE_1; - pwmen |= mskCT16_PWM4EN_EN; - pwmioen |= mskCT16_PWM4IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM4MODE_2; - pwmen |= mskCT16_PWM4EN_EN; - pwmioen |= mskCT16_PWM4IOEN_EN; - break; - } - switch (pwmp->config->channels[5].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM5MODE_1; - pwmen |= mskCT16_PWM5EN_EN; - pwmioen |= mskCT16_PWM5IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM5MODE_2; - pwmen |= mskCT16_PWM5EN_EN; - pwmioen |= mskCT16_PWM5IOEN_EN; - break; - } - switch (pwmp->config->channels[6].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM6MODE_1; - pwmen |= mskCT16_PWM6EN_EN; - pwmioen |= mskCT16_PWM6IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM6MODE_2; - pwmen |= mskCT16_PWM6EN_EN; - pwmioen |= mskCT16_PWM6IOEN_EN; - break; - } - switch (pwmp->config->channels[7].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM7MODE_1; - pwmen |= mskCT16_PWM7EN_EN; - pwmioen |= mskCT16_PWM7IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM7MODE_2; - pwmen |= mskCT16_PWM7EN_EN; - pwmioen |= mskCT16_PWM7IOEN_EN; - break; - } - switch (pwmp->config->channels[8].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM8MODE_1; - pwmen |= mskCT16_PWM8EN_EN; - pwmioen |= mskCT16_PWM8IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM8MODE_2; - pwmen |= mskCT16_PWM8EN_EN; - pwmioen |= mskCT16_PWM8IOEN_EN; - break; - } - switch (pwmp->config->channels[9].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM9MODE_1; - pwmen |= mskCT16_PWM9EN_EN; - pwmioen |= mskCT16_PWM9IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM9MODE_2; - pwmen |= mskCT16_PWM9EN_EN; - pwmioen |= mskCT16_PWM9IOEN_EN; - break; - } - switch (pwmp->config->channels[10].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM10MODE_1; - pwmen |= mskCT16_PWM10EN_EN; - pwmioen |= mskCT16_PWM10IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM10MODE_2; - pwmen |= mskCT16_PWM10EN_EN; - pwmioen |= mskCT16_PWM10IOEN_EN; - break; - } - switch (pwmp->config->channels[11].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM11MODE_1; - pwmen |= mskCT16_PWM11EN_EN; - pwmioen |= mskCT16_PWM11IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM11MODE_2; - pwmen |= mskCT16_PWM11EN_EN; - pwmioen |= mskCT16_PWM11IOEN_EN; - break; - } - switch (pwmp->config->channels[12].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM12MODE_1; - pwmen |= mskCT16_PWM12EN_EN; - pwmioen |= mskCT16_PWM12IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM12MODE_2; - pwmen |= mskCT16_PWM12EN_EN; - pwmioen |= mskCT16_PWM12IOEN_EN; - break; - } - switch (pwmp->config->channels[13].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM13MODE_1; - pwmen |= mskCT16_PWM13EN_EN; - pwmioen |= mskCT16_PWM13IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM13MODE_2; - pwmen |= mskCT16_PWM13EN_EN; - pwmioen |= mskCT16_PWM13IOEN_EN; - break; - } - switch (pwmp->config->channels[14].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM14MODE_1; - pwmen |= mskCT16_PWM14EN_EN; - pwmioen |= mskCT16_PWM14IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM14MODE_2; - pwmen |= mskCT16_PWM14EN_EN; - pwmioen |= mskCT16_PWM14IOEN_EN; - break; - } - switch (pwmp->config->channels[15].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl |= mskCT16_PWM15MODE_1; - pwmen |= mskCT16_PWM15EN_EN; - pwmioen |= mskCT16_PWM15IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl |= mskCT16_PWM15MODE_2; - pwmen |= mskCT16_PWM15EN_EN; - pwmioen |= mskCT16_PWM15IOEN_EN; - break; - } - switch (pwmp->config->channels[16].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM16MODE_1; - pwmen |= mskCT16_PWM16EN_EN; - pwmioen |= mskCT16_PWM16IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM16MODE_2; - pwmen |= mskCT16_PWM16EN_EN; - pwmioen |= mskCT16_PWM16IOEN_EN; - break; - } - switch (pwmp->config->channels[17].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM17MODE_1; - pwmen |= mskCT16_PWM17EN_EN; - pwmioen |= mskCT16_PWM17IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM17MODE_2; - pwmen |= mskCT16_PWM17EN_EN; - pwmioen |= mskCT16_PWM17IOEN_EN; - break; - } - switch (pwmp->config->channels[18].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM18MODE_1; - pwmen |= mskCT16_PWM18EN_EN; - pwmioen |= mskCT16_PWM18IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM18MODE_2; - pwmen |= mskCT16_PWM18EN_EN; - pwmioen |= mskCT16_PWM18IOEN_EN; - break; - } - switch (pwmp->config->channels[19].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM19MODE_1; - pwmen |= mskCT16_PWM19EN_EN; - pwmioen |= mskCT16_PWM19IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM19MODE_2; - pwmen |= mskCT16_PWM19EN_EN; - pwmioen |= mskCT16_PWM19IOEN_EN; - break; - } - switch (pwmp->config->channels[20].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM20MODE_1; - pwmen |= mskCT16_PWM20EN_EN; - pwmioen |= mskCT16_PWM20IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM20MODE_2; - pwmen |= mskCT16_PWM20EN_EN; - pwmioen |= mskCT16_PWM20IOEN_EN; - break; - } - switch (pwmp->config->channels[21].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM21MODE_1; - pwmen |= mskCT16_PWM21EN_EN; - pwmioen |= mskCT16_PWM21IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM21MODE_2; - pwmen |= mskCT16_PWM21EN_EN; - pwmioen |= mskCT16_PWM21IOEN_EN; - break; - } - switch (pwmp->config->channels[22].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM22MODE_1; - pwmen |= mskCT16_PWM22EN_EN; - pwmioen |= mskCT16_PWM22IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM22MODE_2; - pwmen |= mskCT16_PWM22EN_EN; - pwmioen |= mskCT16_PWM22IOEN_EN; - break; - } -#if PWM_CHANNELS > 23 - switch (pwmp->config->channels[23].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - pwmctrl2 |= mskCT16_PWM23MODE_1; - pwmen |= mskCT16_PWM23EN_EN; - pwmioen |= mskCT16_PWM23IOEN_EN; - break; - case PWM_OUTPUT_ACTIVE_HIGH: - pwmctrl2 |= mskCT16_PWM23MODE_2; - pwmen |= mskCT16_PWM23EN_EN; - pwmioen |= mskCT16_PWM23IOEN_EN; - break; - } -#endif - pwmp->ct->PWMCTRL = pwmctrl; - pwmp->ct->PWMCTRL2 = pwmctrl2; - pwmp->ct->PWMENB = pwmen; - pwmp->ct->PWMIOENB = pwmioen; - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ - CT16B1_ResetTimer(); /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (pwmp->clock / pwmp->config->frequency) - 1; - osalDbgAssert((psc <= 0xFF) && /* Prescaler calculation. */ - ((psc + 1) * pwmp->config->frequency) == pwmp->clock, - "invalid frequency"); - pwmp->ct->PRE = psc; -#if PWM_CHANNELS > 23 - pwmp->ct->MR24 = pwmp->period - 1; - -#if SN32_PWM_USE_ONESHOT || defined(__DOXYGEN__) - pwmp->ct->MCTRL3 |= mskCT16_MR24STOP_EN; -#elif !defined(SN32_PWM_NO_RESET) - pwmp->ct->MCTRL3 |= mskCT16_MR24RST_EN; -#endif -#else - pwmp->ct->MR23 = pwmp->period - 1; - -#if SN32_PWM_USE_ONESHOT || defined(__DOXYGEN__) - pwmp->ct->MCTRL3 |= mskCT16_MR23STOP_EN; -#elif !defined(SN32_PWM_NO_RESET) - pwmp->ct->MCTRL3 |= mskCT16_MR23RST_EN; -#endif -#endif - pwmp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ +# elif !defined(SN32_PWM_NO_RESET) + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg |= mskCT16_MRnRST_EN(PWM_CHANNELS); + } +# endif + SN32_CT_PWM_AND(pwmp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ - /* Timer configured and started.*/ - pwmp->ct->TMRCTRL |= mskCT16_CEN_EN; + /* Timer configured and started.*/ + SN32_CT_PWM_OR(pwmp, config.TMRCTRL, mskCT16_CEN_EN); } /** @@ -477,21 +201,20 @@ void pwm_lld_start(PWMDriver *pwmp) { * @notapi */ void pwm_lld_stop(PWMDriver *pwmp) { - - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { - pwmp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ - pwmp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ - -#if SN32_PWM_USE_CT16B1 - if (&PWMD1 == pwmp) { -#if !defined(SN32_CT16B1_SUPPRESS_ISR) - nvicDisableVector(SN32_CT16B1_NUMBER); -#endif - sys1DisableCT16B1(); + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + SN32_CT_PWM_SET(pwmp, config.TMRCTRL, CT16_CEN_DIS); /* Timer disabled. */ + SN32_CT_PWM_AND(pwmp, irq.IC, mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS)); /* Clear pending IRQs.*/ + +# if SN32_PWM_USE_CT16B1 + if (&PWMD1 == pwmp) { +# if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B1_NUMBER); +# endif + sys1DisableCT16B1(); + } +# endif } -#endif - } } /** @@ -507,113 +230,12 @@ void pwm_lld_stop(PWMDriver *pwmp) { * * @notapi */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - /* Changing channel duty cycle on the fly.*/ - switch(channel){ - case 0: - pwmp->ct->MR0 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM0IOEN_EN; - break; - case 1: - pwmp->ct->MR1 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM1IOEN_EN; - break; - case 2: - pwmp->ct->MR2 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM2IOEN_EN; - break; - case 3: - pwmp->ct->MR3 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM3IOEN_EN; - break; - case 4: - pwmp->ct->MR4 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM4IOEN_EN; - break; - case 5: - pwmp->ct->MR5 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM5IOEN_EN; - break; - case 6: - pwmp->ct->MR6 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM6IOEN_EN; - break; - case 7: - pwmp->ct->MR7 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM7IOEN_EN; - break; - case 8: - pwmp->ct->MR8 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM8IOEN_EN; - break; - case 9: - pwmp->ct->MR9 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM9IOEN_EN; - break; - case 10: - pwmp->ct->MR10 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM10IOEN_EN; - break; - case 11: - pwmp->ct->MR11 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM11IOEN_EN; - break; - case 12: - pwmp->ct->MR12 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM12IOEN_EN; - break; - case 13: - pwmp->ct->MR13 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM13IOEN_EN; - break; - case 14: - pwmp->ct->MR14 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM14IOEN_EN; - break; - case 15: - pwmp->ct->MR15 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM15IOEN_EN; - break; - case 16: - pwmp->ct->MR16 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM16IOEN_EN; - break; - case 17: - pwmp->ct->MR17 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM17IOEN_EN; - break; - case 18: - pwmp->ct->MR18 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM18IOEN_EN; - break; - case 19: - pwmp->ct->MR19 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM19IOEN_EN; - break; - case 20: - pwmp->ct->MR20 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM20IOEN_EN; - break; - case 21: - pwmp->ct->MR21 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM21IOEN_EN; - break; - case 22: - pwmp->ct->MR22 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM22IOEN_EN; - break; -#if PWM_CHANNELS > 23 - case 23: - pwmp->ct->MR23 = width; - pwmp->ct->PWMIOENB |= mskCT16_PWM23IOEN_EN; - break; -#endif - default: - ; - } +void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width) { + if (channel < PWM_CHANNELS) { + /* Changing channel duty cycle on the fly.*/ + SN32_CT_PWM_SET(pwmp, MR[channel], width); + SN32_CT_PWM_OR(pwmp, pwm.PWMIOENB, mskCT16_PWMnIOEN_EN(channel)); + } } /** @@ -629,109 +251,10 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, * @notapi */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - - switch(channel){ - case 0: - pwmp->ct->IC |= mskCT16_MR0IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM0IOEN_EN; - break; - case 1: - pwmp->ct->IC |= mskCT16_MR1IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM1IOEN_EN; - break; - case 2: - pwmp->ct->IC |= mskCT16_MR2IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM2IOEN_EN; - break; - case 3: - pwmp->ct->IC |= mskCT16_MR3IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM3IOEN_EN; - break; - case 4: - pwmp->ct->IC |= mskCT16_MR4IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM4IOEN_EN; - break; - case 5: - pwmp->ct->IC |= mskCT16_MR5IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM5IOEN_EN; - break; - case 6: - pwmp->ct->IC |= mskCT16_MR6IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM6IOEN_EN; - break; - case 7: - pwmp->ct->IC |= mskCT16_MR7IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM7IOEN_EN; - break; - case 8: - pwmp->ct->IC |= mskCT16_MR8IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM8IOEN_EN; - break; - case 9: - pwmp->ct->IC |= mskCT16_MR9IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM9IOEN_EN; - break; - case 10: - pwmp->ct->IC |= mskCT16_MR10IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM10IOEN_EN; - break; - case 11: - pwmp->ct->IC |= mskCT16_MR11IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM11IOEN_EN; - break; - case 12: - pwmp->ct->IC |= mskCT16_MR12IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM12IOEN_EN; - break; - case 13: - pwmp->ct->IC |= mskCT16_MR13IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM13IOEN_EN; - break; - case 14: - pwmp->ct->IC |= mskCT16_MR14IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM14IOEN_EN; - break; - case 15: - pwmp->ct->IC |= mskCT16_MR15IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM15IOEN_EN; - break; - case 16: - pwmp->ct->IC |= mskCT16_MR16IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM16IOEN_EN; - break; - case 17: - pwmp->ct->IC |= mskCT16_MR17IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM17IOEN_EN; - break; - case 18: - pwmp->ct->IC |= mskCT16_MR18IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM18IOEN_EN; - break; - case 19: - pwmp->ct->IC |= mskCT16_MR19IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM19IOEN_EN; - break; - case 20: - pwmp->ct->IC |= mskCT16_MR20IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM20IOEN_EN; - break; - case 21: - pwmp->ct->IC |= mskCT16_MR21IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM21IOEN_EN; - break; - case 22: - pwmp->ct->IC |= mskCT16_MR22IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM22IOEN_EN; - break; -#if PWM_CHANNELS > 23 - case 23: - pwmp->ct->IC |= mskCT16_MR23IC; - pwmp->ct->PWMIOENB &= ~mskCT16_PWM23IOEN_EN; - break; -#endif - default: - ; - } + if (channel < PWM_CHANNELS) { + SN32_CT_PWM_OR(pwmp, irq.IC, mskCT16_MRnIC(channel)); + SN32_CT_PWM_AND(pwmp, pwm.PWMIOENB, ~mskCT16_PWMnIOEN_EN(channel)); + } } /** @@ -744,11 +267,12 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { * @notapi */ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { -#if PWM_CHANNELS > 23 - pwmp->ct->MCTRL3 |= mskCT16_MR24IE_EN; -#else - pwmp->ct->MCTRL3 |= mskCT16_MR23IE_EN; -#endif + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg |= mskCT16_MRnIE_EN(PWM_CHANNELS); + } } /** @@ -761,13 +285,12 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { * @notapi */ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { -#if PWM_CHANNELS > 23 - pwmp->ct->IC |= mskCT16_MR24IC; - pwmp->ct->MCTRL3 &= ~mskCT16_MR24IE_EN; -#else - pwmp->ct->IC |= mskCT16_MR23IC; - pwmp->ct->MCTRL3 &= ~mskCT16_MR23IE_EN; -#endif + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg &= ~mskCT16_MRnIE_EN(PWM_CHANNELS); + } } /** @@ -781,86 +304,13 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { * * @notapi */ -void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - switch(channel){ - case 0: - pwmp->ct->MCTRL |= mskCT16_MR0IE_EN; - break; - case 1: - pwmp->ct->MCTRL |= mskCT16_MR1IE_EN; - break; - case 2: - pwmp->ct->MCTRL |= mskCT16_MR2IE_EN; - break; - case 3: - pwmp->ct->MCTRL |= mskCT16_MR3IE_EN; - break; - case 4: - pwmp->ct->MCTRL |= mskCT16_MR4IE_EN; - break; - case 5: - pwmp->ct->MCTRL |= mskCT16_MR5IE_EN; - break; - case 6: - pwmp->ct->MCTRL |= mskCT16_MR6IE_EN; - break; - case 7: - pwmp->ct->MCTRL |= mskCT16_MR7IE_EN; - break; - case 8: - pwmp->ct->MCTRL |= mskCT16_MR8IE_EN; - break; - case 9: - pwmp->ct->MCTRL |= mskCT16_MR9IE_EN; - break; - case 10: - pwmp->ct->MCTRL2 |= mskCT16_MR10IE_EN; - break; - case 11: - pwmp->ct->MCTRL2 |= mskCT16_MR11IE_EN; - break; - case 12: - pwmp->ct->MCTRL2 |= mskCT16_MR12IE_EN; - break; - case 13: - pwmp->ct->MCTRL2 |= mskCT16_MR13IE_EN; - break; - case 14: - pwmp->ct->MCTRL2 |= mskCT16_MR14IE_EN; - break; - case 15: - pwmp->ct->MCTRL2 |= mskCT16_MR15IE_EN; - break; - case 16: - pwmp->ct->MCTRL2 |= mskCT16_MR16IE_EN; - break; - case 17: - pwmp->ct->MCTRL2 |= mskCT16_MR17IE_EN; - break; - case 18: - pwmp->ct->MCTRL2 |= mskCT16_MR18IE_EN; - break; - case 19: - pwmp->ct->MCTRL2 |= mskCT16_MR19IE_EN; - break; - case 20: - pwmp->ct->MCTRL3 |= mskCT16_MR20IE_EN; - break; - case 21: - pwmp->ct->MCTRL3 |= mskCT16_MR21IE_EN; - break; - case 22: - pwmp->ct->MCTRL3 |= mskCT16_MR22IE_EN; - break; -#if PWM_CHANNELS > 23 - case 23: - pwmp->ct->MCTRL3 |= mskCT16_MR23IE_EN; - break; -#endif - default: - ; - } +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg |= mskCT16_MRnIE_EN(channel); + } } /** @@ -874,86 +324,14 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, * * @notapi */ -void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - switch(channel){ - case 0: - pwmp->ct->MCTRL &= ~mskCT16_MR0IE_EN; - break; - case 1: - pwmp->ct->MCTRL &= ~mskCT16_MR1IE_EN; - break; - case 2: - pwmp->ct->MCTRL &= ~mskCT16_MR2IE_EN; - break; - case 3: - pwmp->ct->MCTRL &= ~mskCT16_MR3IE_EN; - break; - case 4: - pwmp->ct->MCTRL &= ~mskCT16_MR4IE_EN; - break; - case 5: - pwmp->ct->MCTRL &= ~mskCT16_MR5IE_EN; - break; - case 6: - pwmp->ct->MCTRL &= ~mskCT16_MR6IE_EN; - break; - case 7: - pwmp->ct->MCTRL &= ~mskCT16_MR7IE_EN; - break; - case 8: - pwmp->ct->MCTRL &= ~mskCT16_MR8IE_EN; - break; - case 9: - pwmp->ct->MCTRL &= ~mskCT16_MR9IE_EN; - break; - case 10: - pwmp->ct->MCTRL2 &= ~mskCT16_MR10IE_EN; - break; - case 11: - pwmp->ct->MCTRL2 &= ~mskCT16_MR11IE_EN; - break; - case 12: - pwmp->ct->MCTRL2 &= ~mskCT16_MR12IE_EN; - break; - case 13: - pwmp->ct->MCTRL2 &= ~mskCT16_MR13IE_EN; - break; - case 14: - pwmp->ct->MCTRL2 &= ~mskCT16_MR14IE_EN; - break; - case 15: - pwmp->ct->MCTRL2 &= ~mskCT16_MR15IE_EN; - break; - case 16: - pwmp->ct->MCTRL2 &= ~mskCT16_MR16IE_EN; - break; - case 17: - pwmp->ct->MCTRL2 &= ~mskCT16_MR17IE_EN; - break; - case 18: - pwmp->ct->MCTRL2 &= ~mskCT16_MR18IE_EN; - break; - case 19: - pwmp->ct->MCTRL2 &= ~mskCT16_MR19IE_EN; - break; - case 20: - pwmp->ct->MCTRL3 &= ~mskCT16_MR20IE_EN; - break; - case 21: - pwmp->ct->MCTRL3 &= ~mskCT16_MR21IE_EN; - break; - case 22: - pwmp->ct->MCTRL3 &= ~mskCT16_MR22IE_EN; - break; -#if PWM_CHANNELS > 23 - case 23: - pwmp->ct->MCTRL3 &= ~mskCT16_MR23IE_EN; - break; -#endif - default: - ; - }} +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { + volatile uint32_t *mctrl_registers[] = {SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL2), SN32_CT_PWM_GET_ADDR(pwmp, match.MCTRL3)}; + // Determine which MCTRL register to use + volatile uint32_t *reg = mctrl_registers[MCTRL_INDEX]; + if (reg != NULL) { + *reg &= ~mskCT16_MRnIE_EN(channel); + } +} /** * @brief Common CT IRQ handler. @@ -966,89 +344,14 @@ void pwm_lld_disable_channel_notification(PWMDriver *pwmp, * @notapi */ void pwm_lld_serve_interrupt(PWMDriver *pwmp) { - uint32_t ris; + uint32_t ris; - ris = pwmp->ct->RIS; - pwmp->ct->IC = ris; - if (((ris & mskCT16_MR0IF) != 0) && - (pwmp->config->channels[0].callback != NULL)) - pwmp->config->channels[0].callback(pwmp); - if (((ris & mskCT16_MR1IF) != 0) && - (pwmp->config->channels[1].callback != NULL)) - pwmp->config->channels[1].callback(pwmp); - if (((ris & mskCT16_MR2IF) != 0) && - (pwmp->config->channels[2].callback != NULL)) - pwmp->config->channels[2].callback(pwmp); - if (((ris & mskCT16_MR3IF) != 0) && - (pwmp->config->channels[3].callback != NULL)) - pwmp->config->channels[3].callback(pwmp); - if (((ris & mskCT16_MR4IF) != 0) && - (pwmp->config->channels[4].callback != NULL)) - pwmp->config->channels[4].callback(pwmp); - if (((ris & mskCT16_MR5IF) != 0) && - (pwmp->config->channels[5].callback != NULL)) - pwmp->config->channels[5].callback(pwmp); - if (((ris & mskCT16_MR6IF) != 0) && - (pwmp->config->channels[6].callback != NULL)) - pwmp->config->channels[6].callback(pwmp); - if (((ris & mskCT16_MR7IF) != 0) && - (pwmp->config->channels[7].callback != NULL)) - pwmp->config->channels[7].callback(pwmp); - if (((ris & mskCT16_MR8IF) != 0) && - (pwmp->config->channels[8].callback != NULL)) - pwmp->config->channels[8].callback(pwmp); - if (((ris & mskCT16_MR9IF) != 0) && - (pwmp->config->channels[9].callback != NULL)) - pwmp->config->channels[9].callback(pwmp); - if (((ris & mskCT16_MR10IF) != 0) && - (pwmp->config->channels[10].callback != NULL)) - pwmp->config->channels[10].callback(pwmp); - if (((ris & mskCT16_MR11IF) != 0) && - (pwmp->config->channels[11].callback != NULL)) - pwmp->config->channels[11].callback(pwmp); - if (((ris & mskCT16_MR12IF) != 0) && - (pwmp->config->channels[12].callback != NULL)) - pwmp->config->channels[12].callback(pwmp); - if (((ris & mskCT16_MR13IF) != 0) && - (pwmp->config->channels[13].callback != NULL)) - pwmp->config->channels[13].callback(pwmp); - if (((ris & mskCT16_MR14IF) != 0) && - (pwmp->config->channels[14].callback != NULL)) - pwmp->config->channels[14].callback(pwmp); - if (((ris & mskCT16_MR15IF) != 0) && - (pwmp->config->channels[15].callback != NULL)) - pwmp->config->channels[15].callback(pwmp); - if (((ris & mskCT16_MR16IF) != 0) && - (pwmp->config->channels[16].callback != NULL)) - pwmp->config->channels[16].callback(pwmp); - if (((ris & mskCT16_MR17IF) != 0) && - (pwmp->config->channels[17].callback != NULL)) - pwmp->config->channels[17].callback(pwmp); - if (((ris & mskCT16_MR18IF) != 0) && - (pwmp->config->channels[18].callback != NULL)) - pwmp->config->channels[18].callback(pwmp); - if (((ris & mskCT16_MR19IF) != 0) && - (pwmp->config->channels[19].callback != NULL)) - pwmp->config->channels[19].callback(pwmp); - if (((ris & mskCT16_MR20IF) != 0) && - (pwmp->config->channels[20].callback != NULL)) - pwmp->config->channels[20].callback(pwmp); - if (((ris & mskCT16_MR21IF) != 0) && - (pwmp->config->channels[21].callback != NULL)) - pwmp->config->channels[21].callback(pwmp); - if (((ris & mskCT16_MR22IF) != 0) && - (pwmp->config->channels[22].callback != NULL)) - pwmp->config->channels[22].callback(pwmp); -#if PWM_CHANNELS > 23 - if (((ris & mskCT16_MR23IF) != 0) && - (pwmp->config->channels[23].callback != NULL)) - pwmp->config->channels[23].callback(pwmp); - if (((ris & mskCT16_MR24IF) != 0) && (pwmp->config->callback != NULL)) - pwmp->config->callback(pwmp); -#else - if (((ris & mskCT16_MR23IF) != 0) && (pwmp->config->callback != NULL)) - pwmp->config->callback(pwmp); -#endif + ris = SN32_CT_PWM_GET(pwmp, irq.RIS); + SN32_CT_PWM_SET(pwmp, irq.IC, ris); + for (int i = 0; i < PWM_CHANNELS; i++) { + if (((ris & mskCT16_MRnIF(i)) != 0) && (pwmp->config->channels[i].callback != NULL)) pwmp->config->channels[i].callback(pwmp); + } + if (((ris & mskCT16_MRnIF(PWM_CHANNELS)) != 0) && (pwmp->config->callback != NULL)) pwmp->config->callback(pwmp); } #endif /* HAL_USE_PWM */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h index 7c6ea68958..195a6346c5 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h @@ -36,8 +36,8 @@ /** * @brief Number of PWM channels per PWM driver. */ -#define PWM_CHANNELS SN32_CT16B1_CHANNELS - +#define PWM_CHANNELS (SN32_CT16B1_CHANNELS - 1) +#define MCTRL_INDEX (PWM_CHANNELS / 10) /** @} */ /*===========================================================================*/ @@ -69,10 +69,6 @@ /* Configuration checks. */ /*===========================================================================*/ -#if !defined(SN32_HAS_CT16B1) -#define SN32_HAS_CT16B1 FALSE -#endif - #if SN32_PWM_USE_CT16B1 && !SN32_HAS_CT16B1 #error "CT16B1 not present in the selected device" #endif @@ -208,15 +204,69 @@ struct PWMDriver { * @brief Timer base clock. */ uint32_t clock; - /** - * @brief Pointer to the CT registers block. - */ - sn32_ct_t *ct; }; /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ +#if SN32_PWM_USE_CT16B1 +#define SN32_CT_PWM_SET_CT16B1(timer, field, value) \ + do { if ((timer) == &PWMD1) (SN32_CT16B1)->field = (value); } while (0) +#else +#define SN32_CT_PWM_SET_CT16B1(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_PWM_SET(timer, field, value) \ + do { \ + SN32_CT_PWM_SET_CT16B1(timer, field, value); \ + } while (0) + +#if SN32_PWM_USE_CT16B1 +#define SN32_CT_PWM_OR_CT16B1(timer, field, value) \ + do { if ((timer) == &PWMD1) (SN32_CT16B1)->field |= (value); } while (0) +#else +#define SN32_CT_PWM_OR_CT16B1(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_PWM_OR(timer, field, value) \ + do { \ + SN32_CT_PWM_OR_CT16B1(timer, field, value); \ + } while (0) + +#if SN32_PWM_USE_CT16B1 +#define SN32_CT_PWM_AND_CT16B1(timer, field, value) \ + do { if ((timer) == &PWMD1) (SN32_CT16B1)->field &= (value); } while (0) +#else +#define SN32_CT_PWM_AND_CT16B1(timer, field, value) \ + do { } while (0) +#endif + +#define SN32_CT_PWM_AND(timer, field, value) \ + do { \ + SN32_CT_PWM_AND_CT16B1(timer, field, value); \ + } while (0) + +#if SN32_PWM_USE_CT16B1 +#define SN32_CT_PWM_GET_CT16B1(timer, cmd) \ + ((timer) == &PWMD1 ? (SN32_CT16B1)->cmd : 0) +#else +#define SN32_CT_PWM_GET_CT16B1(timer, cmd) (0) +#endif + +#define SN32_CT_PWM_GET(timer, cmd) \ + (SN32_CT_PWM_GET_CT16B1(timer, cmd)) + +#if SN32_PWM_USE_CT16B1 +#define SN32_CT_PWM_GET_ADDR_CT16B1(timer, cmd) \ + ((timer) == &PWMD1 ? &(SN32_CT16B1)->cmd : NULL) +#else +#define SN32_CT_PWM_GET_ADDR_CT16B1(timer, cmd) (NULL) +#endif + +#define SN32_CT_PWM_GET_ADDR(timer, cmd) \ + (SN32_CT_PWM_GET_ADDR_CT16B1(timer, cmd)) /** * @brief Changes the period of the PWM peripheral. @@ -234,13 +284,8 @@ struct PWMDriver { * * @notapi */ -#if PWM_CHANNELS > 23 -#define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->ct->MR24 = ((period) - 1)) -#else #define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->ct->MR23 = ((period) - 1)) -#endif + SN32_CT_PWM_SET((pwmp), MR[PWM_CHANNELS], ((period) - 1)) /** * @brief Changes the timer counter of the PWM peripheral. @@ -256,7 +301,7 @@ struct PWMDriver { * @notapi */ #define pwm_lld_change_counter(pwmp, counter) \ - ((pwmp)->ct->TC = (counter)) + SN32_CT_PWM_SET((pwmp), config.TC, (counter)) /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h index 847bf96b08..7e615ab168 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h @@ -26,9 +26,6 @@ #define SN32_CT_H #include -#include "CT16.h" -#include "CT16B0.h" -#include "CT16B1.h" /*===========================================================================*/ /* Driver constants. */ @@ -38,15 +35,92 @@ * @name CT units references * @{ */ -#define SN32_CT16B0 ((sn32_ct_t *)SN_CT16B0_BASE) -#define SN32_CT16B1 ((sn32_ct_t *)SN_CT16B1_BASE) -#if defined(SN32F240B) -#define SN32_CT16B1_CHANNELS 24 +#if !defined(SN32_HAS_CT16B0) +# define SN32_HAS_CT16B0 FALSE +#endif +#if !defined(SN32_HAS_CT16B1) +# define SN32_HAS_CT16B1 FALSE +#endif +#if !defined(SN32_HAS_CT16B2) +# define SN32_HAS_CT16B2 FALSE +#endif +#if !defined(SN32_HAS_CT16B3) +# define SN32_HAS_CT16B3 FALSE +#endif +#if !defined(SN32_HAS_CT16B4) +# define SN32_HAS_CT16B4 FALSE +#endif +#if !defined(SN32_HAS_CT16B5) +# define SN32_HAS_CT16B5 FALSE +#endif + +#if defined(SN32F240) +# define SN32_CT16_PRE_LIMIT UINT16_MAX +# define SN32_CT16_TC_LIMIT UINT16_MAX +# define SN32_CT32_PRE_LIMIT UINT32_MAX +# define SN32_CT32_TC_LIMIT UINT32_MAX +# define SN32_CT16B0_CHANNELS 4 +# define SN32_CT16B1_CHANNELS 4 +# define SN32_CT16B2_CHANNELS 4 +# define SN32_CT32B0_CHANNELS 4 +# define SN32_CT32B1_CHANNELS 4 +# define SN32_CT32B2_CHANNELS 4 +# define SN32_CT32_MAX_CHANNELS 4 +# define SN32_CT16B0_MAX_CHANNELS 4 +# define SN32_CT16B1_MAX_CHANNELS 4 +# define SN32_CT16B2_MAX_CHANNELS 4 +# define SN32_CT16B0 ((sn32_ct16b0_240_t *)SN_CT16B0_BASE) +# define SN32_CT16B1 ((sn32_ct16b0_240_t *)SN_CT16B1_BASE) +# define SN32_CT16B2 ((sn32_ct16b0_240_t *)SN_CT16B2_BASE) +# define SN32_CT32B0 ((sn32_ct32_t *)SN_CT32B0_BASE) +# define SN32_CT32B1 ((sn32_ct32_t *)SN_CT32B1_BASE) +# define SN32_CT32B2 ((sn32_ct32_t *)SN_CT32B2_BASE) +#elif (defined(SN32F240B)|| defined(SN32F240C)) +# define SN32_CT16_PRE_LIMIT UINT8_MAX +# define SN32_CT16_TC_LIMIT UINT16_MAX +# define SN32_CT16B0_CHANNELS 1 +# define SN32_CT16B1_CHANNELS 25 +# define SN32_CT16B0_MAX_CHANNELS 24 +# define SN32_CT16B1_MAX_CHANNELS 25 +# define SN32_CT16B0 ((sn32_ct16b0_240b_t *)SN_CT16B0_BASE) +# define SN32_CT16B1 ((sn32_ct16b1_240b_t *)SN_CT16B1_BASE) #elif defined(SN32F260) -#define SN32_CT16B1_CHANNELS 23 +# define SN32_CT16_PRE_LIMIT UINT8_MAX +# define SN32_CT16_TC_LIMIT UINT16_MAX +# define SN32_CT16B0_CHANNELS 1 +# define SN32_CT16B1_CHANNELS 24 +# define SN32_CT16B0_MAX_CHANNELS 24 +# define SN32_CT16B1_MAX_CHANNELS 25 +# define SN32_CT16B0 ((sn32_ct16b0_240b_t *)SN_CT16B0_BASE) +# define SN32_CT16B1 ((sn32_ct16b1_240b_t *)SN_CT16B1_BASE) +#elif (defined(SN32F280) || defined(SN32F290)) +# define SN32_CT16_PRE_LIMIT UINT16_MAX +# define SN32_CT16_TC_LIMIT UINT16_MAX +# define SN32_CT16B0_CHANNELS 5 +# define SN32_CT16B1_CHANNELS 13 +# define SN32_CT16B2_CHANNELS 5 +# define SN32_CT16B3_CHANNELS 5 +# define SN32_CT16B4_CHANNELS 5 +# define SN32_CT16B5_CHANNELS 5 +# define SN32_CT16B0_PWMN_CHANNELS 4 +# define SN32_CT16B3_PWMN_CHANNELS 2 +# define SN32_CT16B4_PWMN_CHANNELS 2 +# define SN32_CT16B0_MAX_CHANNELS 25 +# define SN32_CT16B1_MAX_CHANNELS 25 +# define SN32_CT16B2_MAX_CHANNELS 25 +# define SN32_CT16B3_MAX_CHANNELS 25 +# define SN32_CT16B4_MAX_CHANNELS 25 +# define SN32_CT16B5_MAX_CHANNELS 25 +# define SN32_CT16B0 ((sn32_ct16b0_290_t *)SN_CT16B0_BASE) +# define SN32_CT16B1 ((sn32_ct16b1_290_t *)SN_CT16B1_BASE) +# define SN32_CT16B2 ((sn32_ct16b0_240b_t *)SN_CT16B2_BASE) +# define SN32_CT16B3 ((sn32_ct16b3_290_t *)SN_CT16B3_BASE) +# define SN32_CT16B4 ((sn32_ct16b3_290_t *)SN_CT16B4_BASE) +# define SN32_CT16B5 ((sn32_ct16b5_290_t *)SN_CT16B5_BASE) #else -#error "CT not supported in the selected device" +# error "CT not supported in the selected device" #endif + /** @} */ /*===========================================================================*/ @@ -66,55 +140,308 @@ * @note This is the most general known form, not all timers have * necessarily all registers and bits. */ -typedef struct { /*!< (@ 0x40002000) SN_CT16Bn Structure */ - volatile uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ - volatile uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ - volatile uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ - volatile uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ - volatile uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ - volatile uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ - volatile uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ - volatile uint32_t MCTRL3; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn Match Control Register 3 */ - volatile uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ - volatile uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ - volatile uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ - volatile uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ - volatile uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ - volatile uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ - volatile uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ - volatile uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ - volatile uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ - volatile uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ - volatile uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ - volatile uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ - volatile uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ - volatile uint32_t MR13; /*!< (@ 0x00000054) Offset:0x54 CT16Bn MR13 Register */ - volatile uint32_t MR14; /*!< (@ 0x00000058) Offset:0x58 CT16Bn MR14 Register */ - volatile uint32_t MR15; /*!< (@ 0x0000005C) Offset:0x5C CT16Bn MR15 Register */ - volatile uint32_t MR16; /*!< (@ 0x00000060) Offset:0x60 CT16Bn MR16 Register */ - volatile uint32_t MR17; /*!< (@ 0x00000064) Offset:0x64 CT16Bn MR17 Register */ - volatile uint32_t MR18; /*!< (@ 0x00000068) Offset:0x68 CT16Bn MR18 Register */ - volatile uint32_t MR19; /*!< (@ 0x0000006C) Offset:0x6C CT16Bn MR19 Register */ - volatile uint32_t MR20; /*!< (@ 0x00000070) Offset:0x70 CT16Bn MR20 Register */ - volatile uint32_t MR21; /*!< (@ 0x00000074) Offset:0x74 CT16Bn MR21 Register */ - volatile uint32_t MR22; /*!< (@ 0x00000078) Offset:0x78 CT16Bn MR22 Register */ - volatile uint32_t MR23; /*!< (@ 0x0000007C) Offset:0x7C CT16Bn MR23 Register */ - volatile uint32_t MR24; /*!< (@ 0x00000080) Offset:0x80 CT16Bn MR24 Register */ - volatile uint32_t CAP0; /*!< (@ 0x00000084) Offset:0x84 CT16Bn CAP0 Register */ - volatile uint32_t EM; /*!< (@ 0x00000088) Offset:0x88 CT16Bn External Match Register */ - volatile uint32_t EMC; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Control register */ - volatile uint32_t EMC2; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register 2 */ - volatile uint32_t PWMCTRL; /*!< (@ 0x00000094) Offset:0x94 CT16Bn PWM Control Register */ - volatile uint32_t PWMCTRL2; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register 2 */ - volatile uint32_t PWMENB; /*!< (@ 0x0000009C) Offset:0x9C CT16Bn PWM Enable register */ - volatile uint32_t PWMIOENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM IO Enable register */ - volatile uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ - volatile uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ -} sn32_ct_t; /*!< Size = 172 (0xac) */ +// Configuration registers block +typedef struct { + volatile uint32_t TMRCTRL; + volatile uint32_t TC; + volatile uint32_t PRE; + volatile uint32_t PC; + volatile uint32_t CNTCTRL; +} sn32_ct_config_t; + +// Match control block +typedef struct { + volatile uint32_t MCTRL; +#if !defined(SN32F240) + volatile uint32_t MCTRL2; + volatile uint32_t MCTRL3; +#endif +} sn32_ct_match_t; + +// Capture control block +typedef struct { + volatile uint32_t CAPCTRL; + volatile uint32_t CAP0; +} sn32_ct_capture_t; + +// External match control block +typedef struct { + volatile uint32_t EM; +#if !defined(SN32F240) + volatile uint32_t EMC; + volatile uint32_t EMC2; +#endif +} sn32_ct_em_t; +// PWM control block +typedef struct { + volatile uint32_t PWMCTRL; +#if !defined(SN32F240) + volatile uint32_t PWMCTRL2; + volatile uint32_t PWMENB; + volatile uint32_t PWMIOENB; +#endif +} sn32_ct_pwm_t; + +// IRQ control block +typedef struct { + volatile uint32_t RIS; + volatile uint32_t IC; +} sn32_ct_irq_t; + +#if defined(SN32F240) +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B0_CHANNELS]; + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct16b0_240_t; +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT32_MAX_CHANNELS]; + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct32_t; +#endif +#if (defined(SN32F240B) || defined(SN32F240C) || defined(SN32F260) || defined(SN32F280) || defined(SN32F290)) +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B0_CHANNELS]; +#if (SN32_CT16B0_CHANNELS != SN32_CT16B0_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B0_MAX_CHANNELS - SN32_CT16B0_CHANNELS]; +#endif + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct16b0_240b_t; +#endif +#if (defined(SN32F280) || defined(SN32F290)) +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B0_CHANNELS]; +#if (SN32_CT16B0_CHANNELS != SN32_CT16B0_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B0_MAX_CHANNELS - SN32_CT16B0_CHANNELS]; +#endif + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers + volatile uint32_t PWMmNIOCTRL; + volatile uint32_t PWMnNDB[SN32_CT16B0_PWMN_CHANNELS]; +} sn32_ct16b0_290_t; +#endif +#if (defined(SN32F240B) || defined(SN32F240C) || defined(SN32F260)) +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B1_CHANNELS]; +#if (SN32_CT16B1_CHANNELS != SN32_CT16B1_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B1_MAX_CHANNELS - SN32_CT16B1_CHANNELS]; +#endif + volatile const uint32_t RESERVED1; + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct16b1_240b_t; +#endif +#if (defined(SN32F280) || defined(SN32F290)) +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B1_CHANNELS]; +#if (SN32_CT16B1_CHANNELS != SN32_CT16B1_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B1_MAX_CHANNELS - SN32_CT16B1_CHANNELS]; +#endif + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct16b1_290_t; + +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B0_CHANNELS]; +#if (SN32_CT16B3_CHANNELS != SN32_CT16B3_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B3_MAX_CHANNELS - SN32_CT16B3_CHANNELS]; +#endif + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers + volatile uint32_t PWMmNIOCTRL; + volatile uint32_t PWMnNDB[SN32_CT16B3_PWMN_CHANNELS]; +} sn32_ct16b3_290_t; + +typedef struct { + sn32_ct_config_t config; // Configuration registers + sn32_ct_match_t match; // Match control registers + volatile uint32_t MR[SN32_CT16B5_CHANNELS]; +#if (SN32_CT16B5_CHANNELS != SN32_CT16B5_MAX_CHANNELS) + volatile const uint32_t RESERVED[SN32_CT16B5_MAX_CHANNELS - SN32_CT16B5_CHANNELS]; +#endif + sn32_ct_capture_t cap; // Capture registers + sn32_ct_em_t em; // External match control + sn32_ct_pwm_t pwm; // PWM control registers + sn32_ct_irq_t irq; // IRQ control registers +} sn32_ct16b5_290_t; +#endif /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ +/* CT16Bn Timer Control register (0x00) */ +#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit +#define CT16_CEN_EN 1 +#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0) +#define mskCT16_CEN_EN (CT16_CEN_EN<<0) + +#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit +#define mskCT16_CRST (CT16_CRST<<1) + +#define CT16_CLKSEL_HCLK 0 //[2:2] CT16Bn PCLK source +#define CT16_CLKSEL_PLL_VCO 1 +#define CT16_CLKSEL_ILRC 2 +#define mskCT16_CLKSEL_HCLK (CT16_CLKSEL_HCLK << 2) +#define mskCT16_CLKSEL_PLL_VCO (CT16_CLKSEL_PLL_VCO << 2) +#define mskCT16_CLKSEL_ILRC (CT16_CLKSEL_ILRC << 2) + +#define CT16_PWM_KEY (0x5A << 24) +#define CT16_PWM_UNLOCK(value) ((CT16_PWM_KEY) | ((value) & 0x00FFFFFF)) + +//[6:4] CT16Bn counting mode selection +#define CT16_CM_EDGE_UP 0 // Edge-aligned Up-counting mode +#define CT16_CM_EDGE_DOWN 1 // Edge-aligned Down-counting mode +#define CT16_CM_CENTER_UP 2 // Center-aligned mode 1. Match interrupt is set during up-counting period +#define CT16_CM_CENTER_DOWN 4 // Center-aligned mode 2. Match interrupt is set during down-counting period +#define CT16_CM_CENTER_BOTH 6 // Center-aligned mode 3. Match interrupt is set during both up and down period. +#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4) +#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4) +#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4) +#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4) +#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4) + +/* CT16Bn Count Control register (0x10) */ +//[1:0] Count/Timer Mode selection. +#define CT16_CTM_TIMER 0 // Timer mode: Every rising PCLK edge. +#define CT16_CTM_CNTER_RISING 1 // Counter mode: TC increments on rising edge of CAP input. +#define CT16_CTM_CNTER_FALLING 2 // Counter mode: TC increments on falling edge of CAP input. +#define CT16_CTM_CNTER_BOTH 3 // Counter mode: TC increments on both edge of CAP input. +#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0) +#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0) +#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0) +#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0) + +#define CT16_CIS 0 //[3:2] Count Input Select +#define mskCT16_CIS (CT16_CIS<<2) + +/* CT16Bn Match Control register (0x14) */ +#define CT16_MRnIE_EN 1 // Enable MRn match interrupt +#define CT16_MRnIE_DIS 0 +#define mskCT16_MRnIE_EN(n) (CT16_MRnIE_EN<<((n % 10) *3)) +#define mskCT16_MRnIE_DIS(n) (CT16_MRnIE_DIS<<((n % 10) *3)) + +#define CT16_MRnRST_EN 1 // Enable reset TC when MRn matches TC. +#define CT16_MRnRST_DIS 0 +#define mskCT16_MRnRST_EN(n) (CT16_MRnRST_EN<<(((n % 10) *3) +1)) +#define mskCT16_MRnRST_DIS(n) (CT16_MRnRST_DIS<<(((n % 10) *3) +1)) + +#define CT16_MRnSTOP_EN 1 // Enable stop TC and clear CEN when MRn matches TC. +#define CT16_MRnSTOP_DIS 0 +#define mskCT16_MRnSTOP_EN(n) (CT16_MRnSTOP_EN<<(((n % 10) *3) +2)) +#define mskCT16_MRnSTOP_DIS(n) (CT16_MRnSTOP_DIS<<(((n % 10) *3) +2)) + +/* CT16Bn Capture Control register (0x80) */ +#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. +#define CT16_CAP0RE_DIS 0 +#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0) +#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0) + +#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. +#define CT16_CAP0FE_DIS 0 +#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1) +#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1) + +#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. +#define CT16_CAP0IE_DIS 0 +#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2) +#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2) + +#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function. +#define CT16_CAP0EN_DIS 0 +#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3) +#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3) + +/* CT16Bn External Match register (0x88) */ +#define CT16_EMn 1 // CT16Bn PWMn drive state +#define mskCT16_EM(n) (CT16_EMn< (0x94) */ +#define CT16_PWMnMODE_1 0 // PWM mode 1. +#define CT16_PWMnMODE_2 1 // PWM mode 2. +#define CT16_PWMnMODE_FORCE_0 2 // Force 0. +#define CT16_PWMnMODE_FORCE_1 3 // Force 1. +#define mskCT16_PWMnMODE_1(n) (CT16_PWMnMODE_1<<((n % 16) *2)) +#define mskCT16_PWMnMODE_2(n) (CT16_PWMnMODE_2<<((n % 16) *2)) +#define mskCT16_PWMnMODE_FORCE_0(n) (CT16_PWMnMODE_FORCE_0<<((n % 16) *2)) +#define mskCT16_PWMnMODE_FORCE_1(n) (CT16_PWMnMODE_FORCE_1<<((n % 16) *2)) +/* CT16Bn PWM Enable register (0x9C) */ +#define CT16_PWMnEN_EN 1 // CT16Bn PWMn is enabled for PWM mode. +#define CT16_PWMnEN_EMn 0 // CT16Bn PWMn is controlled by EMn. +#define mskCT16_PWMnEN_EN(n) (CT16_PWMnEN_EN< (0xA0) */ +#define CT16_PWMnIOEN_EN 1 // PWMn pin acts as match output. +#define CT16_PWMnIOEN_DIS 0 // PWMn pin acts as GPIO. +#define mskCT16_PWMnIOEN_EN(n) (CT16_PWMnIOEN_EN< (0x8C) */ +#define CT16_EMCn_DO_NOTHING 0 //Do nothing. +#define CT16_EMCn_LOW 1 //CT16Bn PWM0 pin is low. +#define CT16_EMCn_HIGH 2 //CT16Bn PWM0 pin is high. +#define CT16_EMCn_TOGGLE 3 //Toggle CT16Bn PWM0 pin. +#define mskCT16_EMCn_DO_NOTHING(n) (CT16_EMCn_LOW<<((n % 16) *2)) +#define mskCT16_EMCn_LOW(n) (CT16_EMCn_LOW<<((n % 16) *2)) +#define mskCT16_EMCn_HIGH(n) (CT16_EMCn_HIGH<<((n % 16) *2)) +#define mskCT16_EMCn_TOGGLE(n) (CT16_EMCn_TOGGLE<<((n % 16) *2)) +/* CT16Bn Timer Raw Interrupt Status register (0xA4) */ +/* CT16Bn Timer Interrupt Clear register (0xA8) */ +/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/ +#define mskCT16_MRnIF(n) (0x1<config.TMRCTRL = (mskCT16_CRST); \ + while (timer->config.TMRCTRL & mskCT16_CRST); \ + } while (0) + +#if defined(SN32_HAS_CT16B0) +# define CT16B0_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B0) +#endif +#if defined(SN32_HAS_CT16B1) +# define CT16B1_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B1) +#endif +#if defined(SN32_HAS_CT16B2) +# define CT16B2_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B2) +#endif +#if defined(SN32_HAS_CT16B3) +# define CT16B3_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B3) +#endif +#if defined(SN32_HAS_CT16B4) +# define CT16B4_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B4) +#endif +#if defined(SN32_HAS_CT16B5) +# define CT16B5_ResetTimer() SN32_CT_ResetTimer(SN32_CT16B5) +#endif /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c index 0a0d87f7d4..242c6d7b77 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c @@ -29,6 +29,29 @@ /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ +uint32_t get_gpio_width(ioportid_t gpiop) { +#if SN32_HAS_GPIOA + if (gpiop == GPIOA) { + return GPIOA_WIDTH; + } +#endif +#if SN32_HAS_GPIOB + if (gpiop == GPIOB) { + return GPIOB_WIDTH; + } +#endif +#if SN32_HAS_GPIOC + if (gpiop == GPIOC) { + return GPIOC_WIDTH; + } +#endif +#if SN32_HAS_GPIOD + if (gpiop == GPIOD) { + return GPIOD_WIDTH; + } +#endif + return 0U; // Default case +} /*===========================================================================*/ /* Driver exported variables. */ @@ -50,6 +73,11 @@ static void initgpio(ioportid_t gpiop, const sn32_gpio_setup_t *config) { gpiop->DATA = config->data; gpiop->MODE = config->mode; gpiop->CFG = config->cfg; +#if (PAL_IOPORTS_WIDTH > 16U) + if (get_gpio_width(gpiop) >16U) { + gpiop->CFG1 = config->cfg1; + } +#endif } #if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) @@ -60,7 +88,7 @@ static void irq_handler(ioportid_t port, uint32_t offset) { chSysUnlockFromISR(); /* invoke callbacks for pending interrupts */ - for (iopadid_t pad = 0; pad < PAL_IOPORTS_WIDTH; pad++) { + for (iopadid_t pad = 0; pad < GET_PORT_WIDTH(port); pad++) { if (ris & (1 << pad)) { _pal_isr_code(offset + pad); } @@ -83,21 +111,21 @@ OSAL_IRQ_HANDLER(SN32_GPIOA_HANDLER) { #if SN32_HAS_GPIOB OSAL_IRQ_HANDLER(SN32_GPIOB_HANDLER) { OSAL_IRQ_PROLOGUE(); - irq_handler(GPIOB, PAL_IOPORTS_WIDTH); + irq_handler(GPIOB, get_gpio_width(GPIOA)); OSAL_IRQ_EPILOGUE(); } #endif #if SN32_HAS_GPIOC OSAL_IRQ_HANDLER(SN32_GPIOC_HANDLER) { OSAL_IRQ_PROLOGUE(); - irq_handler(GPIOC, PAL_IOPORTS_WIDTH * 2); + irq_handler(GPIOC, (get_gpio_width(GPIOA)+get_gpio_width(GPIOB))); OSAL_IRQ_EPILOGUE(); } #endif #if SN32_HAS_GPIOD OSAL_IRQ_HANDLER(SN32_GPIOD_HANDLER) { OSAL_IRQ_PROLOGUE(); - irq_handler(GPIOD, PAL_IOPORTS_WIDTH * 3); + irq_handler(GPIOD, (get_gpio_width(GPIOA)+get_gpio_width(GPIOB)+get_gpio_width(GPIOC))); OSAL_IRQ_EPILOGUE(); } #endif @@ -135,7 +163,7 @@ void _pal_lld_init(const PALConfig *config) { nvicEnableVector(SN32_GPIOD_NUMBER, SN32_GPIOD_IRQ_PRIORITY); #endif - for (uint8_t i = 0; i < TOTAL_PORTS * PAL_IOPORTS_WIDTH; i++) { + for (uint8_t i = 0; i < (get_gpio_width(GPIOA)+get_gpio_width(GPIOB)+get_gpio_width(GPIOC)+get_gpio_width(GPIOD)); i++) { _pal_init_event(i); } #endif @@ -174,6 +202,15 @@ void _pal_lld_init(const PALConfig *config) { void _pal_lld_setpadmode(ioportid_t port, iopadid_t pad, iomode_t mode) { +#if (PAL_IOPORTS_WIDTH > 16U) + volatile uint32_t *cfg_registers[] = {&(port->CFG), &(port->CFG1)}; + volatile uint32_t *cfg_register = cfg_registers[(pad > 15) ? 1 : 0]; + uint32_t bit_offset = (pad % 16) * 2; +#else + volatile uint32_t *cfg_register = &(port->CFG); + uint32_t bit_offset = pad * 2; +#endif + switch (mode) { @@ -183,7 +220,8 @@ void _pal_lld_setpadmode(ioportid_t port, // disable pull up resistor // disable Schmitt trigger // keep DATA low - port->CFG |= (3 << (pad * 2)); + *cfg_register &= ~(3 << bit_offset); + *cfg_register |= (3 << bit_offset); break; case PAL_MODE_INPUT: @@ -191,14 +229,15 @@ void _pal_lld_setpadmode(ioportid_t port, port->MODE &= ~(1 << pad); // disable pull up resistor // enable Schmitt trigger - port->CFG |= (2 << (pad * 2)); + *cfg_register &= ~(3 << bit_offset); + *cfg_register |= (2 << bit_offset); break; case PAL_MODE_INPUT_PULLUP: //set MODE as INPUT port->MODE &= ~(1 << pad); //enable pull up resistor - port->CFG &= ~(3 << (pad * 2)); + *cfg_register &= ~(3 << bit_offset); break; case PAL_MODE_OUTPUT_PUSHPULL: @@ -225,11 +264,11 @@ palevent_t* _pal_lld_get_pad_event(ioportid_t port, if (port == GPIOA) { return _pal_events + pad; } else if (port == GPIOB) { - return _pal_events + PAL_IOPORTS_WIDTH + pad; + return _pal_events + get_gpio_width(GPIOA) + pad; } else if (port == GPIOC) { - return _pal_events + PAL_IOPORTS_WIDTH * 2 + pad; + return _pal_events + (get_gpio_width(GPIOA)+get_gpio_width(GPIOB)) + pad; } else if (port == GPIOD) { - return _pal_events + PAL_IOPORTS_WIDTH * 3 + pad; + return _pal_events + (get_gpio_width(GPIOA)+get_gpio_width(GPIOB)+get_gpio_width(GPIOC))+ pad; } return NULL; } @@ -289,11 +328,11 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { if (port == GPIOA) { _pal_clear_event(pad); } else if (port == GPIOB) { - _pal_clear_event(PAL_IOPORTS_WIDTH + pad); + _pal_clear_event(get_gpio_width(GPIOA) + pad); } else if (port == GPIOC) { - _pal_clear_event(PAL_IOPORTS_WIDTH * 2 + pad); + _pal_clear_event((get_gpio_width(GPIOA)+get_gpio_width(GPIOB)) + pad); } else if (port == GPIOD) { - _pal_clear_event(PAL_IOPORTS_WIDTH * 3 + pad); + _pal_clear_event((get_gpio_width(GPIOA)+get_gpio_width(GPIOB)+get_gpio_width(GPIOC)) + pad); } } diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h index 32c3ea5865..b70a4c276c 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h @@ -15,7 +15,7 @@ */ /** - * @file GPIOv3/hal_pal_lld.h + * @file GPIO/hal_pal_lld.h * @brief SN32 PAL low level driver header. * * @addtogroup PAL @@ -31,21 +31,6 @@ /* Unsupported modes and specific modes */ /*===========================================================================*/ -// /* Specifies palInit() without parameter, required until all platforms will -// be updated to the new style.*/ -// // #define PAL_NEW_INIT - - -/* Discarded definitions from the ST headers, the PAL driver uses its own - definitions in order to have an unified handling for all devices. - Unfortunately the ST headers have no uniform definitions for the same - objects across the various sub-families.*/ -#undef GPIOA -#undef GPIOB -#undef GPIOC -#undef GPIOD - - /*===========================================================================*/ /* I/O Ports Types and constants. */ /*===========================================================================*/ @@ -54,10 +39,10 @@ * @name GPIO ports definitions * @{ */ -#define GPIOA ((SN_GPIO0_Type *)SN_GPIO0_BASE)// SN_GPIO0// -#define GPIOB ((SN_GPIO0_Type *)SN_GPIO1_BASE)// SN_GPIO1// -#define GPIOC ((SN_GPIO0_Type *)SN_GPIO2_BASE)// SN_GPIO2// -#define GPIOD ((SN_GPIO0_Type *)SN_GPIO3_BASE)// SN_GPIO3// +#define GPIOA ((ioportid_t)SN_GPIO0_BASE)// SN_GPIO0// +#define GPIOB ((ioportid_t)SN_GPIO1_BASE)// SN_GPIO1// +#define GPIOC ((ioportid_t)SN_GPIO2_BASE)// SN_GPIO2// +#define GPIOD ((ioportid_t)SN_GPIO3_BASE)// SN_GPIO3// /** @} */ @@ -66,16 +51,17 @@ * @{ */ #define TOTAL_PORTS 4U -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16U /** * @brief Whole port mask. * @details This macro specifies all the valid bits into a port. */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) +#if (PAL_IOPORTS_WIDTH > 16U) + #define PAL_WHOLE_PORT ((ioportmask_t)UINT32_MAX) +#else + #define PAL_WHOLE_PORT ((ioportmask_t)UINT16_MAX) +#endif + /** @} */ /** @@ -99,27 +85,35 @@ * @name Line handling macros * @{ */ +#define GET_PORT_WIDTH(portid) \ + (((uint32_t)(portid) == (uint32_t)GPIOA) ? GPIOA_WIDTH : \ + ((uint32_t)(portid) == (uint32_t)GPIOB) ? GPIOB_WIDTH : \ + ((uint32_t)(portid) == (uint32_t)GPIOC) ? GPIOC_WIDTH : \ + ((uint32_t)(portid) == (uint32_t)GPIOD) ? GPIOD_WIDTH : 0U) + +#define PAL_PAD_MASK (iopadid_t)((1U <<(PAL_IOPORTS_WIDTH / TOTAL_PORTS)) - 1) + /** * @brief Forms a line identifier. * @details A port/pad pair are encoded into an @p ioline_t type. The encoding * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of + * @note In this driver the pad number is encoded in the lower PAL_PAD_MASK bits of * the GPIO address which are guaranteed to be zero. */ #define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + ((ioline_t)((ioportmask_t)(port)) | ((iopadid_t)(pad))) /** * @brief Decodes a port identifier from a line identifier. */ #define PAL_PORT(line) \ - ((SN_GPIO0_Type *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + ((ioportid_t)((ioline_t)(line) & ~PAL_PAD_MASK)) /** * @brief Decodes a pad identifier from a line identifier. */ #define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + ((iopadid_t)((ioline_t)(line) & PAL_PAD_MASK)) /** * @brief Value identifying an invalid line. @@ -153,6 +147,10 @@ typedef struct { uint32_t bset; /** Initial value for BCLR register.*/ uint32_t bclr; +#if (PAL_IOPORTS_WIDTH > 16U) + /** Initial value for CFG1 register.*/ + uint32_t cfg1; +#endif } sn32_gpio_setup_t; /** @@ -202,8 +200,11 @@ typedef uint32_t ioline_t; * any assumption about it, use the provided macros when populating * variables of this type. */ -typedef SN_GPIO0_Type * ioportid_t; - +#if (defined(SN32F240) || defined(SN32F240B)|| defined(SN32F240C)|| defined(SN32F260)) + typedef SN_GPIO0_Type * ioportid_t; +#elif (defined(SN32F280)|| defined(SN32F290)) + typedef SN_GPIO1_Type * ioportid_t; +#endif /** * @brief Type of an pad identifier. */ @@ -313,7 +314,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (uint16_t)(bits)) +#define pal_lld_writeport(port, bits) ((port)->DATA = (uint32_t)(bits)) /** * @brief Sets a bits mask on a I/O port. @@ -326,7 +327,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->BSET = (uint16_t)(bits)) +#define pal_lld_setport(port, bits) ((port)->BSET = (uint32_t)(bits)) /** * @brief Clears a bits mask on a I/O port. @@ -339,7 +340,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint16_t)(bits)) +#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint32_t)(bits)) /** * @brief Writes a group of bits. @@ -355,7 +356,7 @@ typedef uint32_t iopadid_t; * @notapi */ #define pal_lld_writegroup(port, mask, offset, bits) { \ - uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (GET_PORT_WIDTH(port) + (offset))) | \ ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ (port)->DATA = w; \ } diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.c index 3dffe6d5b9..2c5640b0f9 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.c @@ -86,100 +86,121 @@ static inline void i2c_lld_configure(I2CDriver *i2cp) { dp->SCLHT = (uint32_t)(tval -1); dp->SCLLT = (uint32_t)(tval -1); - + if(i2cp->config->timeout > 0) { // Convert timeout in milliseconds to system ticks sysinterval_t timeout_ticks = TIME_MS2I(i2cp->config->timeout); uint32_t timeout_cycles = (uint32_t)(timeout_ticks * 32 * I2C_CLK / CH_CFG_ST_FREQUENCY); osalDbgCheck(timeout_cycles <= 0xFFFF); - dp->TOCTRL = timeout_cycles; + dp->TOCTRL = (uint16_t)timeout_cycles; + } +} + +static inline void i2c_lld_handle_error(I2CDriver *i2cp, uint32_t error_flag) { + i2cp->errors |= error_flag; + _i2c_wakeup_error_isr(i2cp); + i2cp->i2c->STAT_b.I2CIF = true; +} + +static inline void i2c_lld_handle_success(I2CDriver *i2cp) { + _i2c_wakeup_isr(i2cp); + i2cp->i2c->STAT_b.I2CIF = true; } static inline void i2c_lld_irq_handler(I2CDriver * i2cp) { I2C_TypeDef *dp = i2cp->i2c; + uint32_t status = dp->STAT; + bool master = (status & mskI2C_MASTER_STATUS); - if (dp-> STAT_b.TIMEOUT) { - i2cp -> errors |= I2C_TIMEOUT; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_error_isr(i2cp); + if (status & mskI2C_I2C_TIMEOUT) { + i2c_lld_handle_error(i2cp, I2C_TIMEOUT); return; } - if (dp-> STAT_b.LOST_ARB) { - i2cp -> errors |= I2C_ARBITRATION_LOST; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_error_isr(i2cp); + if (status & mskI2C_LOST_ARB) { + i2c_lld_handle_error(i2cp, I2C_ARBITRATION_LOST); return; } - if((dp-> STAT_b.STOP_DN)){ + if (status & mskI2C_STOP_DONE) { // stop received - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_isr(i2cp); + i2c_lld_handle_success(i2cp); return; } - if((dp-> STAT_b.MST) && (dp-> STAT_b.START_DN)) { + if (master && (status & mskI2C_START_DONE)) { // set slave address. dp->TXDATA = i2cp->addr; - dp-> STAT_b.I2CIF |= true; + dp->STAT_b.I2CIF |= true; return; } // TX if (i2cp->state == I2C_ACTIVE_TX) { - if ((dp-> STAT_b.ACK_STAT) | (dp-> STAT_b.SLV_TX_HIT)) { - if (i2cp -> tx_buffer && i2cp -> count < i2cp -> tx_len) { - // ack received, clear to transmit - dp-> TXDATA = i2cp -> tx_buffer[i2cp -> count++]; - } else if (dp-> STAT_b.MST) { - // transmission completed - dp-> CTRL_b.STO |= true; - } - dp-> STAT_b.I2CIF = true; - return; - } else if (dp-> STAT_b.NACK_STAT) { - if (dp-> STAT_b.MST == false) { - dp-> CTRL_b.ACK |= true; - dp-> STAT_b.I2CIF |= true; - return; - } - else if (i2cp -> count == i2cp -> tx_len) { - dp-> CTRL_b.STO |= true; - _i2c_wakeup_isr(i2cp); - } else { - i2cp -> errors |= I2C_ACK_FAILURE; - } - dp-> STAT_b.I2CIF |= true; + if (status & (mskI2C_ACK_DONE | mskI2C_SLAVE_TX_MATCH)) { + if (i2cp->tx_buffer && i2cp->count < i2cp->tx_len) { + dp->TXDATA = i2cp->tx_buffer[i2cp->count++]; + dp->STAT_b.I2CIF |= true; + } + + else if (i2cp->count == i2cp->tx_len) { + // All data sent — end transaction + dp->CTRL_b.STO = true; + i2c_lld_handle_success(i2cp); + } + + } else if (status & mskI2C_NACK_DONE) { + if (!master) { + // Slave was NACKed — treat as completed + dp->CTRL_b.ACK = true; + i2c_lld_handle_success(i2cp); + } else if (i2cp->count == i2cp->tx_len) { + dp->CTRL_b.STO = true; + i2c_lld_handle_success(i2cp); } else { - i2cp -> errors |= I2C_BUS_ERROR; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_error_isr(i2cp); + dp->CTRL_b.STO = true; + i2c_lld_handle_error(i2cp, I2C_ACK_FAILURE); } + + } else { + dp->CTRL_b.STO = true; + i2c_lld_handle_error(i2cp, I2C_BUS_ERROR); + } } // RX - if (i2cp->state == I2C_ACTIVE_RX) { - if ((dp-> STAT_b.MST) | (dp-> STAT_b.ACK_STAT) || (dp-> STAT_b.SLV_RX_HIT)) { - dp-> CTRL_b.ACK |= true; - dp-> STAT_b.I2CIF |= true; - return; - } else if((dp-> STAT_b.MST) | (dp-> STAT_b.RX_DN)) { - if (i2cp -> rx_buffer && i2cp -> count < i2cp -> rx_len) { - // rx done received, clear to receive - i2cp -> rx_buffer[i2cp -> count++] = dp-> RXDATA; - dp-> STAT_b.I2CIF |= true; - } else if (i2cp -> count == i2cp -> rx_len) { - // transmission completed - dp-> CTRL_b.STO = true; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_isr(i2cp); + else if (i2cp->state == I2C_ACTIVE_RX) { + if ((status & mskI2C_ACK_DONE) || (status & mskI2C_SLAVE_RX_MATCH)) { + // ACK to continue reception + if (i2cp->count < i2cp->rx_len) { + dp->CTRL_b.ACK = true; } else { - i2cp -> errors |= I2C_OVERRUN; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_error_isr(i2cp); + i2c_lld_handle_error(i2cp, I2C_OVERRUN); + return; + } + dp->STAT_b.I2CIF = true; + return; + } + + if (status & mskI2C_RX_DONE) { + if (!i2cp->rx_buffer || i2cp->count >= i2cp->rx_len) { + // Buffer full or invalid + i2c_lld_handle_error(i2cp, I2C_OVERRUN); + return; } + + // Receive byte + i2cp->rx_buffer[i2cp->count++] = dp->RXDATA; + + if (i2cp->count == i2cp->rx_len) { + if (master) dp->CTRL_b.STO = true; + i2c_lld_handle_success(i2cp); + } else dp->STAT_b.I2CIF = true; } else { - i2cp -> errors |= I2C_BUS_ERROR; - dp-> STAT_b.I2CIF |= true; - _i2c_wakeup_error_isr(i2cp); + dp->CTRL_b.STO = true; + i2c_lld_handle_error(i2cp, I2C_BUS_ERROR); } } + // UNINIT, STOP, READY, LOCKED + else { + dp->CTRL_b.STO = true; + i2c_lld_handle_error(i2cp, I2C_BUS_ERROR); + } } /*===========================================================================*/ /* Driver interrupt handlers. */ @@ -259,7 +280,7 @@ void i2c_lld_start(I2CDriver *i2cp) { #if SN32_I2C_USE_I2C1 == TRUE if (&I2CD1 == i2cp) { - sys1EnableI2C0(); + sys1EnableI2C1(); nvicClearPending(SN32_I2C1_GLOBAL_NUMBER); nvicEnableVector(SN32_I2C1_GLOBAL_NUMBER, SN32_I2C_I2C1_IRQ_PRIORITY); } @@ -429,10 +450,10 @@ msg_t i2c_lld_match_address(I2CDriver *i2cp, i2caddr_t addr) { I2C_TypeDef *dp = i2cp->i2c; uint16_t i2cadr = addr << 1; - uint16_t ownAdr = dp->SLVADRR0 & (0x7f<<1); + uint16_t ownAdr = dp->SLVADDR0 & (0x7f<<1); if (ownAdr == 0 || ownAdr == i2cadr) - dp->SLVADRR0 = i2cadr; + dp->SLVADDR0 = i2cadr; else /* cannot add this address to set of those matched */ return MSG_RESET; diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.h index 3e77bd4965..7fe33408c9 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.h @@ -228,6 +228,10 @@ struct hal_i2c_driver { extern I2CDriver I2CD0; #endif +#if (SN32_I2C_USE_I2C1 == TRUE) && !defined(__DOXYGEN__) +extern I2CDriver I2CD1; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/sn32_i2c.h b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/sn32_i2c.h index 9301d77bbd..5a86f046be 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/sn32_i2c.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/sn32_i2c.h @@ -1,6 +1,6 @@ /* Copyright (C) 2023 1Conan - Copyright (C) 2023 Dimitris Mantzouranis + Copyright (C) 2025 Dimitris Mantzouranis Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,70 +16,83 @@ */ #ifndef SN32_I2C_H -#define SN32_I2C_H +# define SN32_I2C_H typedef struct { union { - uint32_t CTRL; + volatile uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ struct { uint32_t : 1; - uint32_t NACK : 1; - uint32_t ACK : 1; + volatile uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + volatile uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ uint32_t : 1; - uint32_t STO : 1; - uint32_t STA : 1; + volatile uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + volatile uint32_t STA : 1; /*!< [5..5] START assert flag */ uint32_t : 1; - uint32_t MODE : 1; - uint32_t I2CEN : 1; + volatile uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + volatile uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ uint32_t : 23; } CTRL_b; }; union { - uint32_t STAT; + volatile uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ struct { - uint32_t RX_DN : 1; - uint32_t ACK_STAT : 1; - uint32_t NACK_STAT : 1; - uint32_t STOP_DN : 1; - uint32_t START_DN : 1; - uint32_t MST : 1; - uint32_t SLV_RX_HIT : 1; - uint32_t SLV_TX_HIT : 1; - uint32_t LOST_ARB : 1; - uint32_t TIMEOUT : 1; + volatile const uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + volatile const uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + volatile const uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + volatile const uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + volatile const uint32_t START_DN : 1; /*!< [4..4] START done status */ + volatile const uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + volatile const uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + volatile const uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + volatile const uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + volatile const uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ uint32_t : 5; - uint32_t I2CIF : 1; + volatile uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ uint32_t : 16; } STAT_b; }; - uint32_t TXDATA; - uint32_t RXDATA; + volatile uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + volatile const uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ union { - uint32_t SLVADRR0; + volatile uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ struct { - uint32_t ADDR : 10; + volatile uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ uint32_t : 20; - uint32_t GCEN : 1; - uint32_t ADD_MODE : 1; - + volatile uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + volatile uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ } SLVADDR0_b; }; - uint32_t SLVADDR1; - uint32_t SLVADDR2; - uint32_t SLVADDR3; - uint32_t SCLHT; - uint32_t SCLLT; - uint32_t SCLCT; - uint32_t TOCTRL; + volatile uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + volatile uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + volatile uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + volatile uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + volatile uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + volatile uint32_t SCLCT; /*!< (@ 0x00000028) Offset:0x28 I2C SCL Check Time register */ + volatile uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ } sn32_i2c_t; + +/* I2C n Status register (0x04) */ +#define mskI2C_RX_DONE (1 << 0) +#define mskI2C_ACK_DONE (1 << 1) +#define mskI2C_NACK_DONE (1 << 2) +#define mskI2C_STOP_DONE (1 << 3) +#define mskI2C_START_DONE (1 << 4) +#define mskI2C_MASTER_STATUS (1 << 5) +#define mskI2C_SLAVE_RX_MATCH (1 << 6) +#define mskI2C_SLAVE_TX_MATCH (1 << 7) +#define mskI2C_LOST_ARB (1 << 8) +#define mskI2C_I2C_TIMEOUT (1 << 9) +#define mskI2C_I2CIF_PENDING (1 << 15) + #endif /* SN32_I2C_H */ /** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c deleted file mode 100644 index 82b0fb149f..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c +++ /dev/null @@ -1,51 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: PMU related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 1. First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/*************************************************************************************************** -* Function : PMU_Setting -* Description : Setting and enter specified Low power mode -* Input : mode - specified Low power mode (PMU_SLEEP, PMU_DEEP_SLEEP, PMU_DEEP_PWR_DOWN) -* Output : None -* Return : None -* Note : None -****************************************************************************************************/ -void PMU_Setting(uint16_t mode) -{ - - SN_PMU->CTRL = mode; - - __WFI(); - - SN_PMU->CTRL = 0x0; -} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h deleted file mode 100644 index 988c69093c..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __SN32F2XX_PMU_H -#define __SN32F2XX_PMU_H - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define PMU_SLEEP 4 -#define PMU_DEEP_SLEEP 2 - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void PMU_Setting(uint16_t mode_sel); - -#endif /*__SN32F2XX_PMU_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/RTC/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/driver.mk new file mode 100644 index 0000000000..c102cc6d09 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/RTC diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.c new file mode 100644 index 0000000000..7095346833 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.c @@ -0,0 +1,274 @@ +/* + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTC/hal_rtc_lld.c + * @brief SN32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Converts time from timespec to seconds counter. + * + * @param[in] timespec pointer to a @p RTCDateTime structure + * @return the TR register encoding. + * + * @notapi + */ +static time_t rtc_encode(const RTCDateTime *timespec) { + struct tm tim; + + rtcConvertDateTimeToStructTm(timespec, &tim, NULL); + return mktime(&tim); +} + +/** + * @brief Converts time from seconds/milliseconds to timespec. + * + * @param[in] tv_sec seconds value + * @param[in] tv_msec milliseconds value + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +static void rtc_decode(uint32_t tv_sec, + uint32_t tv_msec, + RTCDateTime *timespec) { + struct tm tim; + struct tm *t; + const time_t time = (const time_t)tv_sec; /* Could be 64 bits.*/ + + /* If the conversion is successful the function returns a pointer + to the object the result was written into.*/ +#if defined(__GNUC__) || defined(__CC_ARM) + t = localtime_r(&time, &tim); + osalDbgAssert(t != NULL, "conversion failed"); +#else + t = localtime(&time); + memcpy(&tim, t, sizeof(struct tm)); +#endif + + rtcConvertStructTmToDateTime(&tim, tv_msec, timespec); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_RTC_HANDLER) { + uint32_t flags; + + OSAL_IRQ_PROLOGUE(); + + flags = RTCD1.rtc->RIS; + RTCD1.rtc->IC = flags; + + if (flags & mskRTC_SECIF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initialize RTC. + * + * @notapi + */ +void rtc_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + + /* RTC pointer initialization.*/ + RTCD1.rtc = SN_RTC; + + /* Clock activation.*/ + sys1EnableRTC(); + + /* All interrupts initially disabled.*/ + RTCD1.rtc->IE = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(SN32_RTC_NUMBER, SN32_RTC_IRQ_PRIORITY); + + RTCD1.rtc->CTRL |= mskRTC_RTCEN_ENABLE; +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on SN32F1xx platform. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { + time_t tv_sec = rtc_encode(timespec); + + rtcSN32SetSec(rtcp, tv_sec); +} + +/** + * @brief Get current time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { + uint32_t tv_sec; + + rtcSN32GetSec(rtcp, &tv_sec); + rtc_decode(tv_sec, 0, timespec); +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + + rtcp->rtc->IC = mskRTC_SECIC; + rtcp->rtc->IE = mskRTC_SECIE; + } + else { + rtcp->rtc->IE = 0; + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get seconds from RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] tv_sec pointer to seconds value + * + * @api + */ +void rtcSN32GetSec(RTCDriver *rtcp, uint32_t *tv_sec) { + uint32_t time_frac; + syssts_t sts; + + osalDbgCheck((NULL != tv_sec) && (NULL != rtcp)); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + *tv_sec = rtcp->rtc->SECCNT; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Set seconds in RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] tv_sec seconds value + * + * @api + */ +void rtcSN32SetSec(RTCDriver *rtcp, uint32_t tv_sec) { + syssts_t sts; + + osalDbgCheck(NULL != rtcp); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + uint32_t reg_value = rtcp->rtc->SECCNTV; // Read current value + reg_value &= ~0xFFFFF; // Clear the lower 20 bits + reg_value |= ((tv_sec >> 16) & 0xFFFFF); // Set the new 20-bit value + rtcp->rtc->SECCNTV = reg_value; // Write back the updated value + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.h new file mode 100644 index 0000000000..9b088636e4 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/RTC/hal_rtc_lld.h @@ -0,0 +1,138 @@ +/* + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RTC/hal_rtc_lld.h + * @brief SN32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + */ +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief No alarm comparator available. + */ +#define RTC_ALARMS 0 + +/** + * @brief Presence of a local persistent storage. + */ +#define RTC_HAS_STORAGE FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#define SN32_RTC_IRQ_PRIORITY 3 +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !SN32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0 /** Triggered every second. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct hal_rtc_alarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +} RTCAlarm; + +/** + * @brief Implementation-specific @p RTCDriver fields. + */ +#define rtc_lld_driver_fields \ + /* Pointer to the RTC registers block.*/ \ + RTC_TypeDef *rtc; \ + /* Callback pointer.*/ \ + rtccb_t callback + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + #define mskRTC_RTCEN_ENABLE 1 + #define mskRTC_SECIF (0x1 << 0) //Interrupt flag for Second + #define mskRTC_SECIC mskRTC_SECIF + #define mskRTC_SECIE mskRTC_SECIF +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + void rtcSN32GetSec(RTCDriver *rtcp, uint32_t *tv_sec); + void rtcSN32SetSec(RTCDriver *rtcp, uint32_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.c index 38dc6d98af..38aa7d7c06 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.c @@ -58,16 +58,13 @@ SPIDriver SPID1; static void spi_lld_configure(SPIDriver *spip) { spip->spi->CTRL0 = spip->config->ctrl0; - spip->spi->CTRL1 = spip->config->ctrl1; - spip->spi->CLKDIV = spip->config->clkdiv; - - spip->spi->CTRL0 |= (spip->config->slave << 3); + spip->spi->CTRL0_b.SELDIS = SPI_SELECT_MODE != SPI_SELECT_MODE_LLD; + spip->spi->CTRL0_b.MS = spip->config->slave; spip->spi->CTRL0_b.SDODIS = false; -#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD - // Use hardware Auto-SEL - spip->spi->CTRL0_b.SELDIS = false; -#endif + spip->spi->CTRL1 = (uint32_t)spip->config->ctrl1; + + spip->spi->CLKDIV = (uint32_t)spip->config->clkdiv; uint32_t sn32_spi_clock = (SN32_HCLK / ((2 * spip->config->clkdiv) + 2)); if (sn32_spi_clock > 6000000) { diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.h index 0a6ed33a91..27c75f7051 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/hal_spi_v2_lld.h @@ -163,8 +163,8 @@ */ #define spi_lld_config_fields \ uint32_t ctrl0; \ - uint32_t ctrl1; \ - uint32_t clkdiv; + uint8_t ctrl1; \ + uint8_t clkdiv; /*===========================================================================*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/sn32_spi.h b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/sn32_spi.h index 4395c40b9d..8832ced252 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/sn32_spi.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/sn32_spi.h @@ -19,79 +19,80 @@ typedef struct { union { - uint32_t CTRL0; + volatile uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPIn Control Register 0 */ + struct { - uint32_t SPIEN : 1; - uint32_t LOOPBACK : 1; - uint32_t SDODIS : 1; - uint32_t MS : 1; - uint32_t FORMAT : 1; - uint32_t : 1; - uint32_t FRESET : 2; - uint32_t DL : 4; - uint32_t TXFIFOTH : 3; - uint32_t RXFIFOTH : 3; - uint32_t SELDIS : 1; - uint32_t : 13; + volatile uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + volatile uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + volatile uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + volatile uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + volatile uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + volatile uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + volatile uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + volatile uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + volatile uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + volatile uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; } CTRL0_b; }; - uint32_t CTRL1; - uint32_t CLKDIV; + volatile uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPIn Control Register 1 */ + volatile uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPIn Clock Divider Register */ union { - uint32_t STAT; + volatile const uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPIn Status Register */ struct { - uint32_t TX_EMPTY : 1; - uint32_t TX_FULL : 1; - uint32_t RX_EMPTY : 1; - uint32_t RX_FULL : 1; - uint32_t BUSY : 1; - uint32_t TXFIFOTHF : 1; - uint32_t RXFIFOTHF : 1; - uint32_t : 25; + volatile const uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + volatile const uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + volatile const uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + volatile const uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + volatile const uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + volatile const uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + volatile const uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; } STAT_b; }; union { - uint32_t IE; + volatile uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPIn Interrupt Enable Register */ struct { - uint32_t RXOVFIE : 1; - uint32_t RXTOIE : 1; - uint32_t RXFIFOTHIE : 1; - uint32_t TXFIFOTHIE : 1; - uint32_t : 28; + volatile uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + volatile uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + volatile uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + volatile uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; } IE_b; }; union { - uint32_t RIS; + volatile const uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPIn Raw Interrupt Status Register */ struct { - uint32_t RXOVFIF : 1; - uint32_t RXTOIF : 1; - uint32_t RXFIFOTHIF : 1; - uint32_t TXFIFOTHIF : 1; - uint32_t : 28; + volatile const uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + volatile const uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + volatile const uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + volatile const uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; } RIS_b; }; union { - uint32_t IC; + volatile uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPIn Interrupt Clear Register */ struct { - uint32_t RXOVFIC : 1; - uint32_t RXTOIC : 1; - uint32_t RXFIFOTHIC : 1; - uint32_t TXFIFOTHIC : 1; - uint32_t : 28; + volatile uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + volatile uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + volatile uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + volatile uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; } IC_b; }; - uint32_t DATA; - uint32_t DFDLY; + volatile uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPIn Data Register */ + volatile uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPIn Data Fetch Register */ } sn32_spi_t; #endif /* SN32_SPI_H */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c deleted file mode 100644 index e754c43084..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c +++ /dev/null @@ -1,71 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: SysTick related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include "SysTick.h" - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ -/***************************************************************************** -* Function : SysTick_Init -* Description : Initialization of SysTick timer -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void SysTick_Init (void) -{ - SystemCoreClockUpdate(); - - __SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1 - - __SYSTICK_CLEAR_COUNTER_AND_FLAG; - -#if SYSTICK_IRQ == INTERRUPT_METHOD - SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt -#else - SysTick->CTRL = 0x5; //Enable SysTick timer ONLY -#endif -} - - -/***************************************************************************** -* Function : SysTick_Handler -* Description : ISR of SysTick interrupt -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void SysTick_Handler(void) -{ - __SYSTICK_CLEAR_COUNTER_AND_FLAG; -} - - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h deleted file mode 100644 index 7a6379a7ba..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __SN32F2XX_SYSTICK_H -#define __SN32F2XX_SYSTICK_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include - - -/*_____ D E F I N I T I O N S ______________________________________________*/ -#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt - //POLLING_METHOD: Enable SysTick timer ONLY - -/*_____ M A C R O S ________________________________________________________*/ -#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1 -#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF - - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -void SysTick_Init(void); - -#endif /*__SN32F2XX_SYSTICK_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c index bf863d2368..b062477b91 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c @@ -37,7 +37,7 @@ #error "Tickless mode on SN32 supports only 16bit timers" #endif -#if SN32_ST_USE_TIMER == CT16B0 +#if SN32_ST_USE_TIMER == SN32_TIM_CT16B0 #if !SN32_HAS_CT16B0 #error "CT16B0 not present in the selected device" @@ -46,7 +46,7 @@ #define ST_ENABLE_CLOCK() sys1EnableCT16B0() #define ST_INIT_CLOCK() CT16B0_ResetTimer() -#elif SN32_ST_USE_TIMER == CT16B1 +#elif SN32_ST_USE_TIMER == SN32_TIM_CT16B1 #if !SN32_HAS_CT16B1 #error "CT16B1 not present in the selected device" @@ -65,7 +65,7 @@ #error "the selected ST frequency is not obtainable because integer rounding" #endif -#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFF +#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > UINT8_MAX #error "the selected ST frequency is not obtainable because CT16 timer prescaler limits" #endif @@ -130,8 +130,10 @@ void st_lld_init(void) { ST_ENABLE_CLOCK(); ST_INIT_CLOCK(); /* Initializing the counter in free running mode.*/ - SN32_ST_TIM->PRE = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; - SN32_ST_TIM->TMRCTRL |= mskCT16_CEN_EN; + SN32_ST_TIM->config.PRE = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; + // safeguarding, CT16B1 has always more channels + SN32_ST_TIM->irq.IC &= mskCT_IC_Clear(SN32_CT16B1_MAX_CHANNELS); + SN32_ST_TIM->config.TMRCTRL |= mskCT16_CEN_EN; /* Reset the SysTick timer. */ SysTick->LOAD = 0; diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h index 887425cb62..3c003eb793 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h @@ -30,6 +30,8 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ +#define SN32_TIM_CT16B0 0 +#define SN32_TIM_CT16B1 1 /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -53,7 +55,7 @@ * @note Timers CT16B0 and CT16B1 are supported. */ #if !defined(SN32_ST_USE_TIMER) || defined(__DOXYGEN__) -#define SN32_ST_USE_TIMER CT16B0 +#define SN32_ST_USE_TIMER SN32_TIM_CT16B0 #endif /** @} */ /*===========================================================================*/ @@ -68,7 +70,7 @@ #endif #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING -#if SN32_ST_USE_TIMER == CT16B0 +#if SN32_ST_USE_TIMER == SN32_TIM_CT16B0 #if defined(SN32_CT16B0_IS_USED) #error "ST requires CT16B0 but the timer is already used" @@ -79,7 +81,7 @@ #define SN32_ST_TIM SN32_CT16B0 #define ST_LLD_NUM_ALARMS 1 -#elif SN32_ST_USE_TIMER == CT16B1 +#elif SN32_ST_USE_TIMER == SN32_TIM_CT16B1 #if defined(SN32_CT16B1_IS_USED) #error "ST requires CT16B1 but the timer is already used" @@ -131,7 +133,7 @@ extern "C" { * @notapi */ static inline systime_t st_lld_get_counter(void) { - return (systime_t)(SN32_ST_TIM->TC & 0x0000FFFF); + return (systime_t)(SN32_ST_TIM->config.TC & UINT16_MAX); } /** @@ -147,20 +149,23 @@ static inline void st_lld_start_alarm(systime_t abstime) { /* The requested delay in OSAL_ST_FREQUENCY ticks, decreased by 1 to bring it * into the 0...0xFFFF range instead of 1...0x10000. */ - uint32_t delay = ((uint32_t)abstime - SN32_ST_TIM->TC - 1U) & 0xFFFF; + uint32_t delay = ((uint32_t)abstime - SN32_ST_TIM->config.TC - 1U) & SN32_CT16_TC_LIMIT; /* The conversion factor between the SN32_ST_TIM and SysTick clock * frequencies (SN32_HCLK / OSAL_ST_FREQUENCY). * TODO: Actually use (SN32_HCLK / OSAL_ST_FREQUENCY) instead of reading the * value from a hardware register (this requires making SN32_HCLK a compile * time constant). */ - uint32_t prescale = (SN32_ST_TIM->PRE & 0xFF) + 1; + uint32_t prescale = (SN32_ST_TIM->config.PRE & UINT8_MAX) + 1; /* The requested delay in the SysTick clock ticks. The maximum possible * value with prescale=256 is 0xFFFFFF, which just fits into the 24-bit * SysTick timer registers. */ uint32_t systick_delay = delay * prescale + (prescale - 1); + if (systick_delay > 0xFFFFFF) { + systick_delay = 0xFFFFFF; + } /* Start SysTick to generate an interrupt after systick_delay. */ SysTick->LOAD = systick_delay; SysTick->VAL = 0; @@ -170,7 +175,11 @@ static inline void st_lld_start_alarm(systime_t abstime) { /* Save the alarm time in a timer register. This is needed only to make * st_lld_get_alarm() work. */ - SN32_ST_TIM->MR0 = (uint32_t)abstime; +#if ((defined(SN32F280) || defined(SN32F290)) && SN32_ST_USE_TIMER == SN32_TIM_CT16B0) + SN32_ST_TIM->MR[0] = CT16_PWM_UNLOCK(((uint32_t)abstime & SN32_CT16_TC_LIMIT)); +#else + SN32_ST_TIM->MR[0] = ((uint32_t)abstime & SN32_CT16_TC_LIMIT); +#endif } /** @@ -203,7 +212,7 @@ static inline void st_lld_set_alarm(systime_t abstime) { * @notapi */ static inline systime_t st_lld_get_alarm(void) { - return (systime_t)(SN32_ST_TIM->MR0 & 0x0000FFFF); + return (systime_t)(SN32_ST_TIM->MR[0] & SN32_CT16_TC_LIMIT); } /** diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c index 16a22a933c..b3c36d6dbe 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c @@ -51,6 +51,11 @@ SerialDriver SD1; SerialDriver SD2; #endif +/** @brief UART3 serial driver identifier.*/ +#if SN32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -362,6 +367,15 @@ static void notify2(io_queue_t *qp) { load(&SD2); } #endif + +#if SN32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify3(io_queue_t *qp) { + + (void)qp; + load(&SD3); +} +#endif + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -423,6 +437,25 @@ OSAL_IRQ_HANDLER(SN32_UART2_HANDLER) { } #endif +#if SN32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +#if !defined(SN32_UART3_HANDLER) +#error "SN32_UART3_HANDLER not defined" +#endif +/** + * @brief UART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&SD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -448,6 +481,11 @@ void sd_lld_init(void) { sdObjectInit(&SD2, NULL, notify2); SD2.uart = SN32_UART2; #endif + +#if SN32_SERIAL_USE_UART3 + sdObjectInit(&SD3, NULL, notify3); + SD3.uart = SN32_UART3; +#endif } /** @@ -489,6 +527,14 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { uart_init(sdp, config); nvicEnableVector(SN32_UART2_NUMBER, SN32_SERIAL_UART2_PRIORITY); } +#endif +#if SN32_SERIAL_USE_UART3 + if (&SD3 == sdp) { + /* UART3 clock enable.*/ + sys1EnableUART3(); + uart_init(sdp, config); + nvicEnableVector(SN32_UART3_NUMBER, SN32_SERIAL_UART3_PRIORITY); + } #endif } } @@ -529,6 +575,14 @@ void sd_lld_stop(SerialDriver *sdp) { nvicDisableVector(SN32_UART2_NUMBER); return; } +#endif +#if SN32_SERIAL_USE_UART3 + if (&SD3 == sdp) { + /* UART3 DeInit.*/ + sys1DisableUART3(); + nvicDisableVector(SN32_UART3_NUMBER); + return; + } #endif } } diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h index ec37948f2f..b52a3421fc 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h @@ -68,6 +68,15 @@ #define SN32_SERIAL_USE_UART2 FALSE #endif +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define SN32_SERIAL_USE_UART3 FALSE +#endif + /** * @brief UART0 interrupt priority level setting. */ @@ -89,6 +98,13 @@ #define SN32_SERIAL_UART2_PRIORITY 3 #endif +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(SN32_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) +#define SN32_SERIAL_UART3_PRIORITY 3 +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -105,8 +121,12 @@ #error "UART2 not present in the selected device" #endif +#if SN32_SERIAL_USE_UART3 && !SN32_HAS_UART3 +#error "UART3 not present in the selected device" +#endif + #if !SN32_SERIAL_USE_UART0 && !SN32_SERIAL_USE_UART1 && \ - !SN32_SERIAL_USE_UART2 + !SN32_SERIAL_USE_UART2 && !SN32_SERIAL_USE_UART3 #error "SERIAL driver activated but no UART/UART peripheral assigned" #endif @@ -125,6 +145,11 @@ #error "Invalid IRQ priority assigned to UART2" #endif +#if SN32_SERIAL_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_SERIAL_UART3_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -144,6 +169,11 @@ #define SN32_UART2 ((sn32_uart_t *)SN_UART2_BASE) #endif +#if SN32_HAS_UART3 +#define SN32_UART3_BASE SN_UART3_BASE +#define SN32_UART3 ((sn32_uart_t *)SN_UART3_BASE) +#endif + /** * @brief SN32 Serial Driver configuration structure. * @details An instance of this structure must be passed to @p sdStart() @@ -227,6 +257,9 @@ extern SerialDriver SD1; #if SN32_SERIAL_USE_UART2 && !defined(__DOXYGEN__) extern SerialDriver SD2; #endif +#if SN32_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c index 1a9caea3af..e98574f4f6 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c @@ -49,6 +49,11 @@ UARTDriver UARTD1; UARTDriver UARTD2; #endif +/** @brief UART3 UART driver identifier.*/ +#if SN32_UART_USE_UART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -363,6 +368,25 @@ OSAL_IRQ_HANDLER(SN32_UART2_HANDLER) { } #endif /* SN32_UART_USE_UART2 */ +#if SN32_UART_USE_UART3 || defined(__DOXYGEN__) +#if !defined(SN32_UART3_HANDLER) +#error "SN32_UART3_HANDLER not defined" +#endif +/** + * @brief UART3 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_uart_irq(&UARTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* SN32_UART_USE_UART3 */ + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -388,6 +412,11 @@ void uart_lld_init(void) { uartObjectInit(&UARTD2); UARTD2.uart = SN32_UART2; #endif + +#if SN32_UART_USE_UART3 + uartObjectInit(&UARTD3); + UARTD3.uart = SN32_UART3; +#endif } /** @@ -426,6 +455,15 @@ void uart_lld_start(UARTDriver *uartp) { nvicEnableVector(SN32_UART2_NUMBER, SN32_UART_UART2_IRQ_PRIORITY); } #endif + +#if SN32_UART_USE_UART3 + if (&UARTD3 == uartp) { + /* UART3 clock enable.*/ + sys1EnableUART3(); + nvicClearPending(SN32_UART3_NUMBER); + nvicEnableVector(SN32_UART3_NUMBER, SN32_UART_UART3_IRQ_PRIORITY); + } +#endif } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; @@ -473,6 +511,14 @@ void uart_lld_stop(UARTDriver *uartp) { return; } #endif + +#if SN32_UART_USE_UART3 + if (&UARTD3 == uartp) { + nvicDisableVector(SN32_UART3_NUMBER); + sys1DisableUART3(); + return; + } +#endif } } diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h index 608515fa65..ad6bb1ea0b 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h @@ -68,6 +68,15 @@ #define SN32_UART_USE_UART2 FALSE #endif +/** + * @brief UART driver on UART3 enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_UART_USE_UART3) || defined(__DOXYGEN__) +#define SN32_UART_USE_UART3 FALSE +#endif + /** * @brief UART0 interrupt priority level setting. */ @@ -89,6 +98,13 @@ #define SN32_UART_UART2_IRQ_PRIORITY 3 #endif +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(SN32_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_UART_UART3_IRQ_PRIORITY 3 +#endif + /** @} */ /*===========================================================================*/ @@ -107,8 +123,12 @@ #error "UART2 not present in the selected device" #endif +#if SN32_UART_USE_UART3 && !SN32_HAS_UART3 +#error "UART3 not present in the selected device" +#endif + #if !SN32_UART_USE_UART0 && !SN32_UART_USE_UART1 && \ - !SN32_UART_USE_UART2 + !SN32_UART_USE_UART2 && !SN32_UART_USE_UART3 #error "UART driver activated but no UART/UART peripheral assigned" #endif @@ -127,6 +147,11 @@ #error "Invalid IRQ priority assigned to UART2" #endif +#if SN32_UART_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_UART_UART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -146,6 +171,11 @@ #define SN32_UART2 ((sn32_uart_t *)SN_UART2_BASE) #endif +#if SN32_HAS_UART3 +#define SN32_UART3_BASE SN_UART3_BASE +#define SN32_UART3 ((sn32_uart_t *)SN_UART3_BASE) +#endif + /** * @brief UART driver condition flags type. */ @@ -332,6 +362,10 @@ extern UARTDriver UARTD1; extern UARTDriver UARTD2; #endif +#if SN32_UART_USE_UART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h index ab3c75af16..fb7bc4aed5 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h @@ -18,166 +18,154 @@ # define SN32_UART_H typedef struct { - union { - union { - __IM uint32_t RB; - - struct { - __IM uint32_t RB : 8; - } RB_b; - }; - - union { - __OM uint32_t TH; - - struct { - __OM uint32_t TH : 8; - } TH_b; - }; - - union { - __IOM uint32_t DLL; - - struct { - __IOM uint32_t DLL : 8; - } DLL_b; - }; - }; - - union { - union { - __IOM uint32_t DLM; - - struct { - __IOM uint32_t DLM : 8; - } DLM_b; - }; - - union { - __IOM uint32_t IE; - - struct { - __IOM uint32_t RDAIE : 1; - __IOM uint32_t THREIE : 1; - __IOM uint32_t RLSIE : 1; - __IM uint32_t : 1; - __IOM uint32_t TEMTIE : 1; - __IM uint32_t : 3; - __IOM uint32_t ABEOIE : 1; - __IOM uint32_t ABTOIE : 1; - } IE_b; - }; - }; - - union { - union { - __IM uint32_t II; - - struct { - __IM uint32_t INTSTATUS : 1; - __IM uint32_t INTID : 3; - __IM uint32_t : 2; - __IM uint32_t FIFOEN : 2; - __IM uint32_t ABEOIF : 1; - __IM uint32_t ABTOIF : 1; - } II_b; - }; - - union { - __OM uint32_t FIFOCTRL; - - struct { - __OM uint32_t FIFOEN : 1; - __IM uint32_t : 5; - __OM uint32_t RXTL : 2; - } FIFOCTRL_b; - }; - }; - - union { - __IOM uint32_t LC; - - struct { - __IOM uint32_t WLS : 2; - __IOM uint32_t SBS : 1; - __IOM uint32_t PE : 1; - __IOM uint32_t PS : 2; - __IOM uint32_t BC : 1; - __IOM uint32_t DLAB : 1; - } LC_b; - }; - __IM uint32_t RESERVED; - - union { - __IM uint32_t LS; - - struct { - __IM uint32_t RDR : 1; - __IM uint32_t OE : 1; - __IM uint32_t PE : 1; - __IM uint32_t FE : 1; - __IM uint32_t BI : 1; - __IM uint32_t THRE : 1; - __IM uint32_t TEMT : 1; - __IM uint32_t RXFE : 1; - } LS_b; - }; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t SP; - - struct { - __IOM uint32_t PAD : 8; - } SP_b; - }; - - union { - __IOM uint32_t ABCTRL; - - struct { - __IOM uint32_t START : 1; - __IOM uint32_t MODE : 1; - __IOM uint32_t AUTORESTART : 1; - __IM uint32_t : 5; - __OM uint32_t ABEOIFC : 1; - __OM uint32_t ABTOIFC : 1; - } ABCTRL_b; - }; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t FD; - - struct { - __IOM uint32_t DIVADDVAL : 4; - __IOM uint32_t MULVAL : 4; - __IOM uint32_t OVER8 : 1; - } FD_b; - }; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t CTRL; - - struct { - __IOM uint32_t UARTEN : 1; - __IOM uint32_t MODE : 3; - __IM uint32_t : 2; - __IOM uint32_t RXEN : 1; - __IOM uint32_t TXEN : 1; - } CTRL_b; - }; - - union { - __IOM uint32_t HDEN; - - struct { - __IOM uint32_t HDEN : 1; - } HDEN_b; - }; + union { + union { + volatile const uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + struct { + volatile const uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + }; + union { + volatile uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + struct { + volatile uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter is available */ + uint32_t : 24; + } TH_b; + }; + union { + volatile uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + struct { + volatile uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + }; + }; + union { + union { + volatile uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + struct { + volatile uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + }; + union { + volatile uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + struct { + volatile uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + volatile uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + volatile uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + volatile uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + volatile uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + volatile uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + }; + }; + union { + union { + volatile const uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + struct { + volatile const uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + volatile const uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + volatile const uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + volatile const uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + volatile const uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + }; + union { + volatile uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + struct { + volatile uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + volatile uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + }; + }; + union { + volatile uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + struct { + volatile uint32_t WLS : 2; /*!< [1..0] Word length selection */ + volatile uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + volatile uint32_t PE : 1; /*!< [3..3] Parity enable */ + volatile uint32_t PS : 2; /*!< [5..4] Parity selection */ + volatile uint32_t BC : 1; /*!< [6..6] Break control */ + volatile uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + }; + volatile const uint32_t RESERVED; + union { + volatile const uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + struct { + volatile const uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + volatile const uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + volatile const uint32_t PE : 1; /*!< [2..2] Parity error flag */ + volatile const uint32_t FE : 1; /*!< [3..3] Framing error flag */ + volatile const uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + volatile const uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + volatile const uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + volatile const uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + }; + volatile const uint32_t RESERVED1; + union { + volatile uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + struct { + volatile uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + }; + union { + volatile uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + struct { + volatile uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + volatile uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + volatile uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + volatile uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + volatile uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + }; + volatile const uint32_t RESERVED2; + union { + volatile uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + struct { + volatile uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + volatile uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + volatile uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + }; + volatile const uint32_t RESERVED3; + union { + volatile uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + struct { + volatile uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + volatile uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + volatile uint32_t RXEN : 1; /*!< [6..6] RX enable */ + volatile uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + }; + union { + volatile uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + struct { + volatile uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + }; } sn32_uart_t; + /** @defgroup UART_Exported_Constants * @{ */ diff --git a/os/hal/ports/SN32/SN32F240/hal_efl_lld.c b/os/hal/ports/SN32/SN32F240/hal_efl_lld.c index b6ef39fe50..44e8ed7afa 100644 --- a/os/hal/ports/SN32/SN32F240/hal_efl_lld.c +++ b/os/hal/ports/SN32/SN32F240/hal_efl_lld.c @@ -78,7 +78,7 @@ static inline void sn32_flash_start_pgm(EFlashDriver *eflp) { static inline void sn32_flash_clear_status(EFlashDriver *eflp) { /* Clearing error conditions.*/ - eflp->flash->STATUS_b.ERR = 0; + eflp->flash->STATUS_b.PGERR = 0; } static inline void sn32_flash_wait_busy(EFlashDriver *eflp) { @@ -89,10 +89,10 @@ static inline void sn32_flash_wait_busy(EFlashDriver *eflp) { } static inline flash_error_t sn32_flash_check_errors(EFlashDriver *eflp) { - uint32_t error = eflp->flash->STATUS_b.ERR; + uint32_t error = eflp->flash->STATUS_b.PGERR; /* Clearing error conditions.*/ - eflp->flash->STATUS_b.ERR = 0; + eflp->flash->STATUS_b.PGERR = 0; /* Decoding relevant errors.*/ if ((error) != 0U) { @@ -198,7 +198,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, sn32_flash_clear_status(devp); /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); + memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); /* Ready state again.*/ devp->state = FLASH_READY; diff --git a/os/hal/ports/SN32/SN32F240/hal_lld.h b/os/hal/ports/SN32/SN32F240/hal_lld.h index 5ac220e040..62d8ee9938 100644 --- a/os/hal/ports/SN32/SN32F240/hal_lld.h +++ b/os/hal/ports/SN32/SN32F240/hal_lld.h @@ -74,6 +74,7 @@ /* Various helpers.*/ #include "nvic.h" +#include "sn32_sys1.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/SN32/SN32F240/platform.mk b/os/hal/ports/SN32/SN32F240/platform.mk index 58b75cbd19..ded6d29853 100644 --- a/os/hal/ports/SN32/SN32F240/platform.mk +++ b/os/hal/ports/SN32/SN32F240/platform.mk @@ -5,7 +5,7 @@ PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ # Required include directories. PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx \ $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240 ifeq ($(USE_SMART_BUILD),yes) @@ -20,9 +20,10 @@ HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community endif # Drivers compatible with the platform. -include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/SN32/SN32F240/sn32_sys1.h b/os/hal/ports/SN32/SN32F240/sn32_sys1.h new file mode 100644 index 0000000000..5bd78ea72e --- /dev/null +++ b/os/hal/ports/SN32/SN32F240/sn32_sys1.h @@ -0,0 +1,850 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240/sn32_sys1.h + * @brief SYS1 helper driver header. + * @note This file requires definitions from the SN32 header file + * @p SN32F240.h. + * + * @addtogroup SN32F24x_SYS1 + * @{ + */ + +#ifndef SN32_SYS1_H +#define SN32_SYS1_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic AHB operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1EnableAHB(mask) { \ + SN_SYS1->AHBCLKEN |= (mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1DisableAHB(mask) { \ + SN_SYS1->AHBCLKEN &= ~(mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Resets one or more peripheral. + * + * @param[in] mask Reset peripherals mask + * + * @api + */ +#define sys1Reset(mask) { \ + SN_SYS1->PRST |= (mask); \ + SN_SYS1->PRST &= ~(mask); \ + (void)SN_SYS1->PRST; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB0 bus. + * + * @param[in] mask APB0 peripherals mask + * + * @api + */ +#define sys1SelectAPB0(mask) { \ + SN_SYS1->APBCP0 |= (mask); \ + (void)SN_SYS1->APBCP0; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define sys1SelectAPB1(mask) { \ + SN_SYS1->APBCP1 |= (mask); \ + (void)SN_SYS1->APBCP1; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define sys1SelectAPB2(mask) { \ + SN_SYS1->APBCP2 |= (mask); \ + (void)SN_SYS1->APBCP2; \ +} +/** @} */ + +/** + * @name GPIO peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the GPIO peripheral clock. + * + * @api + */ +#define sys1EnableGPIO() sys1EnableAHB(0x1<<0) + +/** + * @brief Disables the GPIO peripheral clock. + * + * @api + */ +#define sys1DisableGPIO() sys1DisableAHB(0x1<<0) + +/** + * @brief Resets the GPIOP0 peripheral. + * + * @api + */ +#define sys1ResetGPIOP0() sys1Reset(0x1<<0) + +/** + * @brief Resets the GPIOP1 peripheral. + * + * @api + */ +#define sys1ResetGPIOP1() sys1Reset(0x1<<1) + +/** + * @brief Resets the GPIOP2 peripheral. + * + * @api + */ +#define sys1ResetGPIOP2() sys1Reset(0x1<<2) + +/** + * @brief Resets the GPIOP3 peripheral. + * + * @api + */ +#define sys1ResetGPIOP3() sys1Reset(0x1<<3) + +/** + * @name USB peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @api + */ +#define sys1EnableUSB() sys1EnableAHB(0x1<<1) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define sys1DisableUSB() sys1DisableAHB(0x1<<1) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define sys1ResetUSB() sys1Reset(0x1<<25) + +/** + * @name LCD peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the LCD peripheral clock. + * + * @api + */ +#define sys1EnableLCD() sys1EnableAHB(0x1<<2) + +/** + * @brief Disables the LCD peripheral clock. + * + * @api + */ +#define sys1DisableLCD() sys1DisableAHB(0x1<<2) + +/** + * @brief Resets the LCD peripheral. + * + * @api + */ +#define sys1ResetLCD() sys1Reset(0x1<<15) + +/** + * @name CT16B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B0() sys1EnableAHB(0x1<<5) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B0() sys1DisableAHB(0x1<<5) + +/** + * @brief Resets the CT16B0 peripheral. + * + * @api + */ +#define sys1ResetCT16B0() sys1Reset(0x1<<5) + +/** + * @brief Configures the CT16B0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT16B0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<0) \ +} + +/** + * @name CT16B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B1() sys1EnableAHB(0x1<<6) + +/** + * @brief Disables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B1() sys1DisableAHB(0x1<<6) + +/** + * @brief Resets the CT16B1 peripheral. + * + * @api + */ +#define sys1ResetCT16B1() sys1Reset(0x1<<6) + +/** + * @brief Configures the CT16B1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT16B1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<4) \ +} + +/** + * @name CT16B2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B2 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B2() sys1EnableAHB(0x1<<7) + +/** + * @brief Disables the CT16B2 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B2() sys1DisableAHB(0x1<<7) + +/** + * @brief Resets the CT16B2 peripheral. + * + * @api + */ +#define sys1ResetCT16B2() sys1Reset(0x1<<7) + +/** + * @brief Configures the CT16B2 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT16B2PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<28) \ +} + +/** + * @name CT32B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT32B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT32B0() sys1EnableAHB(0x1<<8) + +/** + * @brief Disables the CT32B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT32B0() sys1DisableAHB(0x1<<8) + +/** + * @brief Resets the CT32B0 peripheral. + * + * @api + */ +#define sys1ResetCT32B0() sys1Reset(0x1<<8) + +/** + * @brief Configures the CT32B0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT32B0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<8) \ +} + +/** + * @name CT32B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT32B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT32B1() sys1EnableAHB(0x1<<9) + +/** + * @brief Disables the CT32B1 peripheral clock. + * + * @api + */ +#define sys1DisableCT32B1() sys1DisableAHB(0x1<<9) + +/** + * @brief Resets the CT32B1 peripheral. + * + * @api + */ +#define sys1ResetCT32B1() sys1Reset(0x1<<9) + +/** + * @brief Configures the CT32B1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT32B1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<12) \ +} + +/** + * @name CT32B2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT32B2 peripheral clock. + * + * @api + */ +#define sys1EnableCT32B2() sys1EnableAHB(0x1<<10) + +/** + * @brief Disables the CT32B2 peripheral clock. + * + * @api + */ +#define sys1DisableCT32B2() sys1DisableAHB(0x1<<10) + +/** + * @brief Resets the CT32B2 peripheral. + * + * @api + */ +#define sys1ResetCT32B2() sys1Reset(0x1<<10) + +/** + * @brief Configures the CT32B2 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCT32B2PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<28) \ +} + +/** + * @name ADC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @api + */ +#define sys1EnableADC() sys1EnableAHB(0x1<<11) + +/** + * @brief Disables the ADC peripheral clock. + * + * @api + */ +#define sys1DisableADC() sys1DisableAHB(0x1<<11) + +/** + * @brief Resets the ADC peripheral. + * + * @api + */ +#define sys1ResetADC() sys1Reset(0x1<<11) + +/** + * @brief Configures the ADC peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectADCPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<16) \ +} + +/** + * @name SPI0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI0 peripheral clock. + * + * @api + */ +#define sys1EnableSPI0() sys1EnableAHB(0x1<<12) + +/** + * @brief Disables the SPI0 peripheral clock. + * + * @api + */ +#define sys1DisableSPI0() sys1DisableAHB(0x1<<12) + +/** + * @brief Resets the SPI0 peripheral. + * + * @api + */ +#define sys1ResetSPI0() sys1Reset(0x1<<12) + +/** + * @brief Configures the SPI0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectSPI0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<20) \ +} + +/** + * @name SPI1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @api + */ +#define sys1EnableSPI1() sys1EnableAHB(0x1<<13) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define sys1DisableSPI1() sys1DisableAHB(0x1<<13) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define sys1ResetSPI1() sys1Reset(0x1<<13) + +/** + * @brief Configures the SPI1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectSPI1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<24) \ +} + +/** + * @name USART0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USART0 peripheral clock. + * + * @api + */ +#define sys1EnableUSART0() sys1EnableAHB(0x1<<16) + +/** + * @brief Disables the USART0 peripheral clock. + * + * @api + */ +#define sys1DisableUSART0() sys1DisableAHB(0x1<<16) + +/** + * @brief Resets the USART0 peripheral. + * + * @api + */ +#define sys1ResetUSART0() sys1Reset(0x1<<16) + +/** + * @brief Configures the USART0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectUSART0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<0) \ +} + +/** + * @name USART1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @api + */ +#define sys1EnableUSART1() sys1EnableAHB(0x1<<17) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @api + */ +#define sys1DisableUSART1() sys1DisableAHB(0x1<<17) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define sys1ResetUSART1() sys1Reset(0x1<<17) + +/** + * @brief Configures the USART1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectUSART1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<4) \ +} + +/** + * @name I2C1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @api + */ +#define sys1EnableI2C1() sys1EnableAHB(0x1<<20) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define sys1DisableI2C1() sys1DisableAHB(0x1<<20) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define sys1ResetI2C1() sys1Reset(0x1<<20) + +/** + * @brief Configures the I2C1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<24) \ +} + +/** + * @name I2C0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C0 peripheral clock. + * + * @api + */ +#define sys1EnableI2C0() sys1EnableAHB(0x1<<21) + +/** + * @brief Disables the I2C0 peripheral clock. + * + * @api + */ +#define sys1DisableI2C0() sys1DisableAHB(0x1<<21) + +/** + * @brief Resets the I2C0 peripheral. + * + * @api + */ +#define sys1ResetI2C0() sys1Reset(0x1<<21) + +/** + * @brief Configures the I2C0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<8) \ +} + +/** + * @name I2S peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2S peripheral clock. + * + * @api + */ +#define sys1EnableI2S() sys1EnableAHB(0x1<<22) + +/** + * @brief Disables the I2S peripheral clock. + * + * @api + */ +#define sys1DisableI2S() sys1DisableAHB(0x1<<22) + +/** + * @brief Resets the I2S peripheral. + * + * @api + */ +#define sys1ResetI2S() sys1Reset(0x1<<22) + +/** + * @brief Configures the I2S peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2SPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<12) \ +} + +/** + * @name RTC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the RTC peripheral clock. + * + * @api + */ +#define sys1EnableRTC() sys1EnableAHB(0x1<<23) + +/** + * @brief Disables the RTC peripheral clock. + * + * @api + */ +#define sys1DisableRTC() sys1DisableAHB(0x1<<23) + +/** + * @brief Resets the RTC peripheral. + * + * @api + */ +#define sys1ResetRTC() sys1Reset(0x1<<23) + +/** + * @name WDT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the WDT peripheral clock. + * + * @api + */ +#define sys1EnableWDT() sys1EnableAHB(0x1<<24) + +/** + * @brief Disables the WDT peripheral clock. + * + * @api + */ +#define sys1DisableWDT() sys1DisableAHB(0x1<<24) + +/** + * @brief Resets the WDT peripheral. + * + * @api + */ +#define sys1ResetWDT() sys1Reset(0x1<<24) + +/** + * @brief Configures the WDT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectWDTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<20) \ +} + +/** + * @name CLKOUT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CLKOUT peripheral clock. + * + * @param[in] clkval clock output source + * * @api + */ +#define sys1EnableCLKOUT(clkval) { \ + if(clkval > 0) \ + sys1EnableAHB(clkval<<28) \ +} + +/** + * @brief Disables the CLKOUT peripheral clock. + * + * @api + */ +#define sys1DisableCLKOUT() { \ + SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Configures the CLKOUT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCLKOUTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB2(pre<<0) \ +} + +/** + * @brief Configures the SYSTICK peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectSYSTICKPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<16) \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* SN32_SYS1_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/hal_efl_lld.c b/os/hal/ports/SN32/SN32F240B/hal_efl_lld.c index b6ef39fe50..21fc3ca074 100644 --- a/os/hal/ports/SN32/SN32F240B/hal_efl_lld.c +++ b/os/hal/ports/SN32/SN32F240B/hal_efl_lld.c @@ -198,7 +198,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, sn32_flash_clear_status(devp); /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); + memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); /* Ready state again.*/ devp->state = FLASH_READY; diff --git a/os/hal/ports/SN32/SN32F240B/hal_lld.h b/os/hal/ports/SN32/SN32F240B/hal_lld.h index 77d8d08fa7..013805b509 100644 --- a/os/hal/ports/SN32/SN32F240B/hal_lld.h +++ b/os/hal/ports/SN32/SN32F240B/hal_lld.h @@ -80,6 +80,7 @@ /* Various helpers.*/ #include "nvic.h" #include "sn32_ct.h" +#include "sn32_sys1.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/SN32/SN32F240B/platform.mk b/os/hal/ports/SN32/SN32F240B/platform.mk index 62710aa7e4..5f3f40fe92 100644 --- a/os/hal/ports/SN32/SN32F240B/platform.mk +++ b/os/hal/ports/SN32/SN32F240B/platform.mk @@ -28,6 +28,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/SN32/SN32F240C/hal_efl_lld.c b/os/hal/ports/SN32/SN32F240C/hal_efl_lld.c new file mode 100644 index 0000000000..b7ad21bc0a --- /dev/null +++ b/os/hal/ports/SN32/SN32F240C/hal_efl_lld.c @@ -0,0 +1,486 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief SN32F24xC Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SN32_FLASH_LINE_MASK (SN32_FLASH_LINE_SIZE - 1U) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const flash_descriptor_t efl_lld_descriptor = { + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = SN32_FLASH_LINE_SIZE, + .sectors_count = SN32_FLASH_NUMBER_OF_BANKS * + SN32_FLASH_SECTORS_PER_BANK, + .sectors = NULL, + .sectors_size = SN32_FLASH_SECTOR_SIZE, + .address = (uint8_t *)SN32_FLASH_BASE, + .size = SN32_FLASH_NUMBER_OF_BANKS * + SN32_FLASH_SECTORS_PER_BANK * + SN32_FLASH_SECTOR_SIZE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void sn32_flash_enable_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL = SN32_FLASH_CTRL_PG; +} + +static inline void sn32_flash_start_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL |= SN32_FLASH_CTRL_START; +} + +static inline void sn32_flash_clear_status(EFlashDriver *eflp) { + + /* Clearing error conditions.*/ + eflp->flash->STATUS_b.ERR = 0; +} + +static inline void sn32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while ((eflp->flash->STATUS & SN32_FLASH_STATUS_BUSY) != 0U) { + } +} + +static inline flash_error_t sn32_flash_check_errors(EFlashDriver *eflp) { + uint32_t error = eflp->flash->STATUS_b.ERR; + + /* Clearing error conditions.*/ + eflp->flash->STATUS_b.ERR = 0; + + /* Decoding relevant errors.*/ + if ((error) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = SN_FLASH; +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + eflp->flash->CTRL = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * @retval Pointer to single bank if DBM not enabled. + * @retval Pointer to bank1 if DBM enabled. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + + (void)instance; + + return &efl_lld_descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + sn32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Program operation. + * @note The device supports ECC, it is only possible to write erased + * pages once except when writing all zeroes. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ + +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + volatile uint32_t *flash_base = (volatile uint32_t *)efl_lld_descriptor.address; + uint32_t erased_val = (efl_lld_descriptor.attributes & FLASH_ATTR_ERASED_IS_ONE) ? + UINT32_MAX : 0U; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + // Align size to SN32_FLASH_LINE_SIZE (8 bytes) + size_t aligned_size = (n + SN32_FLASH_LINE_MASK) & ~SN32_FLASH_LINE_MASK; + devp->state = FLASH_PGM; + + // Clear previous error flags and enable programming + sn32_flash_clear_status(devp); + sn32_flash_enable_pgm(devp); + + for (size_t i = 0; i < aligned_size; i += SN32_FLASH_LINE_SIZE) { + size_t abs_offset = offset + i; + volatile uint32_t *addr = flash_base + (abs_offset / sizeof(uint32_t)); + + // Read current contents of flash + uint32_t existing_word0 = addr[0]; + uint32_t existing_word1 = addr[1]; + + // Load new data (0-padded if beyond n) + uint32_t word0 = erased_val; + uint32_t word1 = erased_val; + size_t remaining = n - i; + + if (remaining >= (SN32_FLASH_LINE_SIZE / 2)) { + memcpy(&word0, pp + i, (SN32_FLASH_LINE_SIZE / 2)); + if (remaining >= SN32_FLASH_LINE_SIZE) { + memcpy(&word1, pp + i + (SN32_FLASH_LINE_SIZE / 2), (SN32_FLASH_LINE_SIZE / 2)); + } else { + memcpy(&word1, pp + i + (SN32_FLASH_LINE_SIZE / 2), remaining - (SN32_FLASH_LINE_SIZE / 2)); + } + } else { + memcpy(&word0, pp + i, remaining); + } + + // Skip if both words already match erased state + if ((existing_word0 != erased_val) || (existing_word1 != erased_val)) { + flash_sector_t sector = (abs_offset) / efl_lld_descriptor.sectors_size; + err = efl_lld_start_erase_sector(instance, sector); + devp->state = FLASH_READY; + if (err != FLASH_NO_ERROR) return err; + + // Restore programming mode and address + devp->state = FLASH_PGM; + sn32_flash_clear_status(devp); + sn32_flash_enable_pgm(devp); + } + + // Set address + devp->flash->ADDR = (uint32_t)(flash_base + (abs_offset / sizeof(uint32_t))); + + // Write two words (8 bytes) + devp->flash->DATA = word0; + devp->flash->DATA = word1; + + // Trigger programming + sn32_flash_start_pgm(devp); + sn32_flash_wait_busy(devp); + + if (devp->flash->STATUS & SN32_FLASH_STATUS_ERROR) { + sn32_flash_clear_status(devp); + devp->state = FLASH_READY; + return FLASH_ERROR_PROGRAM; + } + + // Re-enable programming for next chunk if any + if (i + SN32_FLASH_LINE_SIZE < aligned_size) { + sn32_flash_enable_pgm(devp); + } + } + + devp->state = FLASH_READY; + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function only erases bank 2 if it is present. Bank 1 is not + * allowed since it is normally where the primary program is located. + * Pages on bank 1 can be individually erased. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + (void) instance; + + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * this is an index within the total sectors + * in a flash bank + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + sn32_flash_clear_status(devp); + + /* Enable page erase.*/ + devp->flash->CTRL = SN32_FLASH_CTRL_PER; + + /* Set the page.*/ + devp->flash->ADDR = (uint32_t)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + sn32_flash_wait_busy(devp); + + /* Start the erase.*/ + sn32_flash_start_pgm(devp); + sn32_flash_wait_busy(devp); + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[out] msec recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if ((devp->flash->STATUS & SN32_FLASH_STATUS_BUSY) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CTRL &= ~(SN32_FLASH_CTRL_PER | SN32_FLASH_CTRL_MER); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + } + else { + /* Recommended time before polling again. This is a simplified + implementation.*/ + if (msec != NULL) { + *msec = (uint32_t)SN32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector.*/ + address = (uint32_t *)(SN32_FLASH_BASE + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + uint32_t erased_val = (efl_lld_descriptor.attributes & FLASH_ATTR_ERASED_IS_ONE) ? + UINT32_MAX : 0U; + uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); + for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { + if (*address != erased_val) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240C/hal_efl_lld.h b/os/hal/ports/SN32/SN32F240C/hal_efl_lld.h new file mode 100644 index 0000000000..062bfc3ba2 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240C/hal_efl_lld.h @@ -0,0 +1,129 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief SN32F24xC Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define SN32_FLASH_CTRL_PG 0x00000001 +#define SN32_FLASH_CTRL_PER 0x00000002 +#define SN32_FLASH_CTRL_MER 0x00000004 +#define SN32_FLASH_CTRL_START 0x00000040 +#define SN32_FLASH_CTRL_CHK 0x00000080 + +#define SN32_FLASH_STATUS_BUSY 0x00000001 +#define SN32_FLASH_STATUS_ERROR 0x00000004 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SN32F24xB configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(SN32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define SN32_FLASH_WAIT_TIME_MS 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(SN32_FLASH_SECTOR_SIZE) +#error "SN32_FLASH_SECTOR_SIZE not defined in registry" +#endif + +#if !defined(SN32_FLASH_NUMBER_OF_BANKS) +#error "SN32_FLASH_NUMBER_OF_BANKS not defined in registry" +#endif + +#if !defined(SN32_FLASH_SECTORS_PER_BANK) +#error "SN32_FLASH_SECTORS_PER_BANK not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + SN_FLASH_Type *flash + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c b/os/hal/ports/SN32/SN32F240C/hal_lld.c similarity index 61% rename from os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c rename to os/hal/ports/SN32/SN32F240C/hal_lld.c index a031d53492..a61568a9b6 100644 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c +++ b/os/hal/ports/SN32/SN32F240C/hal_lld.c @@ -15,42 +15,24 @@ */ /** - * @file hal_st_lld.c - * @brief PLATFORM ST subsystem low level driver source. + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. * - * @addtogroup ST + * @addtogroup HAL * @{ */ #include "hal.h" -#include "CT16.h" -#include "CT16B0.h" -#include "CT16B1.h" -#include "CT16B2.h" -#include "CT32.h" -#include "CT32B0.h" -#include "CT32B1.h" -#include "CT32B2.h" -#include "SN32F240.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) +#include /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ -#define IHRC_CLOCK 12000000 -#define ILRC_CLOCK 32000 -#define ELS_XTAL_CLOCK 32768 - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -63,39 +45,30 @@ /* Driver interrupt handlers. */ /*===========================================================================*/ -OSAL_IRQ_HANDLER(SysTick_Handler) { - - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ /** - * @brief Low level ST driver initialization. + * @brief SN32F24xC clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. * - * @notapi + * @special */ -void st_lld_init(void) { - /* Periodic systick mode, the Cortex-Mx internal systick timer is used - in this mode.*/ - SysTick->LOAD = ((IHRC_CLOCK >> SN_SYS0->AHBCP) / OSAL_ST_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* IRQ enabled.*/ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, 8); +void sn32_clock_init(void) { + SystemCoreClockUpdate(); + FlashClockUpdate(); } -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + SystemInit(); + sn32_clock_init(); +} /** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h b/os/hal/ports/SN32/SN32F240C/hal_lld.h similarity index 53% rename from os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h rename to os/hal/ports/SN32/SN32F240C/hal_lld.h index 612388e07c..fce4f5c1f6 100644 --- a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h +++ b/os/hal/ports/SN32/SN32F240C/hal_lld.h @@ -15,37 +15,56 @@ */ /** - * @file hal_st_lld.h - * @brief PLATFORM ST subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. * - * @addtogroup ST + * @addtogroup HAL * @{ */ -#ifndef HAL_ST_LLD_H -#define HAL_ST_LLD_H - -#include "CT16B0.h" -#include "CT16B1.h" -#include "CT16B2.h" -#include "CT32B0.h" -#include "CT32B1.h" -#include "CT32B2.h" +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ +#include "sn32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SN32F24xC" +/** @} */ + +/** + * @brief Requires use of SPIv2 driver model. + */ +#define HAL_LLD_SELECT_SPI_V2 TRUE + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name PLATFORM configuration options + * @{ + */ +#define SN32_HCLK SystemCoreClock +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -58,90 +77,20 @@ /* External declarations. */ /*===========================================================================*/ +/* Various helpers.*/ +#include "nvic.h" +#include "sn32_ct.h" +#include "sn32_sys1.h" + #ifdef __cplusplus extern "C" { #endif - void st_lld_init(void); + void hal_lld_init(void); + void sn32_clock_init(void); #ifdef __cplusplus } #endif -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) { - return (systime_t)0; -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] abstime the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) { - -} - -/** - * @brief Sets the alarm time. - * - * @param[in] abstime the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) { - - return (systime_t)0; -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) { - - return false; -} - -#endif /* HAL_ST_LLD_H */ +#endif /* _HAL_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/SN32/SN32F240C/platform.mk b/os/hal/ports/SN32/SN32F240C/platform.mk new file mode 100644 index 0000000000..07bafce22d --- /dev/null +++ b/os/hal/ports/SN32/SN32F240C/platform.mk @@ -0,0 +1,35 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240C/hal_lld.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240C/hal_efl_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240C + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif + +# Drivers compatible with the platform. +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) \ No newline at end of file diff --git a/os/hal/ports/SN32/SN32F240C/sn32_registry.h b/os/hal/ports/SN32/SN32F240C/sn32_registry.h new file mode 100644 index 0000000000..e94f790853 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240C/sn32_registry.h @@ -0,0 +1,177 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240C/sn32_registry.h + * @brief SN32F24xC capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef SN32_REGISTRY_H +#define SN32_REGISTRY_H + +/* Common identifier of all SN32F2xx devices.*/ +#if !defined(SN32F2xx) || defined(__DOXYGEN__) +#define SN32F2xx +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SN32F24xC capabilities + * @{ + */ + +/* Common identifier of all SN32F24xC devices.*/ +#if !defined(SN32F240C) || defined(__DOXYGEN__) +#define SN32F240C +#endif + +/* + * ST unit + */ +#define SN32_ST_HANDLER Vector3C +#define SN32_ST_NUMBER SysTick_IRQn + +/* + * NDT unit. + */ +#define SN32_NDT_HANDLER Vector40 +#define SN32_NDT_NUMBER NDT_IRQn + +/* + * USB unit. + */ +#define SN32_USB_HANDLER Vector44 +#define SN32_USB_NUMBER USB_IRQn +#define SN32_HAS_USB TRUE + +#define USBD_INTSTS_EPEVT_Pos USBD_INTSTS_EPEVT0_Pos +#define USBD_INTSTS_EPEVT_Msk (0xFFul << USBD_INTSTS_EPEVT_Pos) + +/* + * SPI unit. + */ +#define SN32_SPI0_HANDLER Vector58 +#define SN32_SPI1_HANDLER Vector5C + +#define SN32_SPI0_NUMBER SPI0_IRQn +#define SN32_SPI1_NUMBER SPI1_IRQn + +#define SN32_HAS_SPI0 TRUE +#define SN32_HAS_SPI1 TRUE + +/* + * I2C unit. + */ +#define SN32_I2C0_GLOBAL_HANDLER Vector68 +#define SN32_I2C1_GLOBAL_HANDLER Vector6C + +#define SN32_I2C0_GLOBAL_NUMBER I2C0_IRQn +#define SN32_I2C1_GLOBAL_NUMBER I2C1_IRQn + +#define SN32_HAS_I2C0 TRUE +#define SN32_HAS_I2C1 TRUE + +/* + * UART units. + */ +#define SN32_UART0_HANDLER Vector70 +#define SN32_UART1_HANDLER Vector74 +#define SN32_UART2_HANDLER Vector78 + +#define SN32_UART0_NUMBER UART0_IRQn +#define SN32_UART1_NUMBER UART1_IRQn +#define SN32_UART2_NUMBER UART2_IRQn + +#define SN32_HAS_UART0 TRUE +#define SN32_HAS_UART1 TRUE +#define SN32_HAS_UART2 TRUE + +/* + * CT16 units. + */ +#define SN32_CT16B0_HANDLER Vector7C +#define SN32_CT16B1_HANDLER Vector80 + +#define SN32_CT16B0_NUMBER CT16B0_IRQn +#define SN32_CT16B1_NUMBER CT16B1_IRQn + +#define SN32_HAS_CT16B0 TRUE +#define SN32_HAS_CT16B1 TRUE + +/* + * ADC unit. + */ +#define SN32_ADC_HANDLER VectorA0 +#define SN32_ADC_NUMBER ADC_IRQn +#define SN32_HAS_ADC TRUE + +/* + * WDT unit. + */ +#define SN32_WDT_HANDLER VectorA4 +#define SN32_WDT_NUMBER WDT_IRQn + +/* + * LVD unit. + */ +#define SN32_LVD_HANDLER VectorA8 +#define SN32_LVD_NUMBER LVD_IRQn + +/* + * GPIO units. + */ +#define SN32_GPIOD_HANDLER VectorB0 +#define SN32_GPIOC_HANDLER VectorB4 +#define SN32_GPIOB_HANDLER VectorB8 +#define SN32_GPIOA_HANDLER VectorBC + +#define SN32_GPIOD_NUMBER P3_IRQn +#define SN32_GPIOC_NUMBER P2_IRQn +#define SN32_GPIOB_NUMBER P1_IRQn +#define SN32_GPIOA_NUMBER P0_IRQn + +#define SN32_HAS_GPIOD TRUE +#define SN32_HAS_GPIOC TRUE +#define SN32_HAS_GPIOB TRUE +#define SN32_HAS_GPIOA TRUE + +/* + * FLASH units. + */ +#define SN32_JUMPLOADER_SIZE 0x200 +#define SN32_FLASH_LINE_SIZE 8U +#define SN32_FLASH_NUMBER_OF_BANKS 1 +#define SN32_FLASH_SECTORS_PER_BANK 128U +#define SN32_FLASH_SECTOR_SIZE 1024U +#define SN32_FLASH_BASE 0x00000000UL +#define FLASH_SIZE (SN32_FLASH_NUMBER_OF_BANKS * SN32_FLASH_SECTORS_PER_BANK * SN32_FLASH_SECTOR_SIZE) +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + + + +/** @} */ + +#endif /* SN32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240C/sn32_sys1.h b/os/hal/ports/SN32/SN32F240C/sn32_sys1.h new file mode 100644 index 0000000000..4dc5e56220 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240C/sn32_sys1.h @@ -0,0 +1,453 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240C/sn32_sys1.h + * @brief SYS1 helper driver header. + * @note This file requires definitions from the SN32 header file + * @p SN32F240C.h. + * + * @addtogroup SN32F24xC_SYS1 + * @{ + */ + +#ifndef SN32_SYS1_H +#define SN32_SYS1_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic AHB operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1EnableAHB(mask) { \ + SN_SYS1->AHBCLKEN |= (mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1DisableAHB(mask) { \ + SN_SYS1->AHBCLKEN &= ~(mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB0 bus. + * + * @param[in] mask APB0 peripherals mask + * + * @api + */ +#define sys1SelectAPB0(mask) { \ + SN_SYS1->APBCP0 |= (mask); \ + (void)SN_SYS1->APBCP0; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define sys1SelectAPB1(mask) { \ + SN_SYS1->APBCP1 |= (mask); \ + (void)SN_SYS1->APBCP1; \ +} + +/** @} */ +/** + * @name Dummy GPIO peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the GPIO peripherals clock. + * + * @api + */ +#define sys1EnableP0() +#define sys1EnableP1() +#define sys1EnableP2() +#define sys1EnableP3() +/** + * @brief Disables the GPIO peripherals clock. + * + * @api + */ +#define sys1DisableP0() +#define sys1DisableP1() +#define sys1DisableP2() +#define sys1DisableP3() + +/** + * @name USB peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @api + */ +#define sys1EnableUSB() sys1EnableAHB(0x1<<4) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define sys1DisableUSB() sys1DisableAHB(0x1<<4) + +/** + * @name CT16B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B0() sys1EnableAHB(0x1<<6) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B0() sys1DisableAHB(0x1<<6) + +/** + * @name CT16B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B1() sys1EnableAHB(0x1<<7) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B1() sys1DisableAHB(0x1<<7) + +/** + * @name ADC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @api + */ +#define sys1EnableADC() sys1EnableAHB(0x1<<11) + +/** + * @brief Disables the ADC peripheral clock. + * + * @api + */ +#define sys1DisableADC() sys1DisableAHB(0x1<<11) + +/** + * @name SPI0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI0 peripheral clock. + * + * @api + */ +#define sys1EnableSPI0() sys1EnableAHB(0x1<<12) + +/** + * @brief Disables the SPI0 peripheral clock. + * + * @api + */ +#define sys1DisableSPI0() sys1DisableAHB(0x1<<12) + +/** + * @name SPI1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @api + */ +#define sys1EnableSPI1() sys1EnableAHB(0x1<<13) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define sys1DisableSPI1() sys1DisableAHB(0x1<<13) +/** + * @name UART0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART0 peripheral clock. + * + * @api + */ +#define sys1EnableUART0() sys1EnableAHB(0x1<<16) + +/** + * @brief Disables the UART0 peripheral clock. + * + * @api + */ +#define sys1DisableUART0() sys1DisableAHB(0x1<<16) + +/** + * @name UART1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART1 peripheral clock. + * + * @api + */ +#define sys1EnableUART1() sys1EnableAHB(0x1<<17) + +/** + * @brief Disables the UART1 peripheral clock. + * + * @api + */ +#define sys1DisableUART1() sys1DisableAHB(0x1<<17) + +/** + * @name UART2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART2 peripheral clock. + * + * @api + */ +#define sys1EnableUART2() sys1EnableAHB(0x1<<18) + +/** + * @brief Disables the UART2 peripheral clock. + * + * @api + */ +#define sys1DisableUART2() sys1DisableAHB(0x1<<18) + +/** + * @name I2C0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C0 peripheral clock. + * + * @api + */ +#define sys1EnableI2C0() sys1EnableAHB(0x1<<21) + +/** + * @brief Disables the I2C0 peripheral clock. + * + * @api + */ +#define sys1DisableI2C0() sys1DisableAHB(0x1<<21) + +/** + * @name I2C1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @api + */ +#define sys1EnableI2C1() sys1EnableAHB(0x1<<20) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define sys1DisableI2C1() sys1DisableAHB(0x1<<20) + +/** + * @name WDT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the WDT peripheral clock. + * + * @api + */ +#define sys1EnableWDT() sys1EnableAHB(0x1<<24) + +/** + * @brief Disables the WDT peripheral clock. + * + * @api + */ +#define sys1DisableWDT() sys1DisableAHB(0x1<<24) + +/** + * @name CRC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CRC peripheral clock. + * + * @api + */ +#define sys1EnableCRC() sys1EnableAHB(0x1<<27) + +/** + * @brief Disables the CRC peripheral clock. + * + * @api + */ +#define sys1DisableCRC() sys1DisableAHB(0x1<<27) + +/** + * @name CLKOUT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CLKOUT peripheral clock. + * + * @param[in] clkval clock output source + * * @api + */ +#define sys1EnableCLKOUT(clkval) { \ + if(clkval > 0) \ + sys1EnableAHB(clkval<<28) \ +} + +/** + * @brief Disables the CLKOUT peripheral clock. + * + * @api + */ +#define sys1DisableCLKOUT() { \ + SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Configures the ADC peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectADCPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<16) \ +} + +/** + * @brief Configures the I2C0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<8) \ +} + +/** + * @brief Configures the WDT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectWDTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<20) \ +} + +/** + * @brief Configures the I2C1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<24) \ +} + +/** + * @brief Configures the CLKOUT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCLKOUTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<28) \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* SN32_SYS1_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F260/hal_efl_lld.c b/os/hal/ports/SN32/SN32F260/hal_efl_lld.c index b6ef39fe50..21fc3ca074 100644 --- a/os/hal/ports/SN32/SN32F260/hal_efl_lld.c +++ b/os/hal/ports/SN32/SN32F260/hal_efl_lld.c @@ -198,7 +198,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, sn32_flash_clear_status(devp); /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); + memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); /* Ready state again.*/ devp->state = FLASH_READY; diff --git a/os/hal/ports/SN32/SN32F260/hal_lld.h b/os/hal/ports/SN32/SN32F260/hal_lld.h index 74f6fe477f..f313e3bda3 100644 --- a/os/hal/ports/SN32/SN32F260/hal_lld.h +++ b/os/hal/ports/SN32/SN32F260/hal_lld.h @@ -80,6 +80,7 @@ /* Various helpers.*/ #include "nvic.h" #include "sn32_ct.h" +#include "sn32_sys1.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/SN32/SN32F290/hal_efl_lld.c b/os/hal/ports/SN32/SN32F290/hal_efl_lld.c new file mode 100644 index 0000000000..cd257b325f --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/hal_efl_lld.c @@ -0,0 +1,486 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief SN32F29x Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SN32_FLASH_LINE_MASK (SN32_FLASH_LINE_SIZE - 1U) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const flash_descriptor_t efl_lld_descriptor = { + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = SN32_FLASH_LINE_SIZE, + .sectors_count = SN32_FLASH_NUMBER_OF_BANKS * + SN32_FLASH_SECTORS_PER_BANK, + .sectors = NULL, + .sectors_size = SN32_FLASH_SECTOR_SIZE, + .address = (uint8_t *)SN32_FLASH_BASE, + .size = SN32_FLASH_NUMBER_OF_BANKS * + SN32_FLASH_SECTORS_PER_BANK * + SN32_FLASH_SECTOR_SIZE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void sn32_flash_enable_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL = SN32_FLASH_CTRL_PG; +} + +static inline void sn32_flash_start_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL |= SN32_FLASH_CTRL_START; +} + +static inline void sn32_flash_clear_status(EFlashDriver *eflp) { + + /* Clearing error conditions.*/ + eflp->flash->STATUS_b.ERR = 0; +} + +static inline void sn32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while ((eflp->flash->STATUS & SN32_FLASH_STATUS_BUSY) != 0U) { + } +} + +static inline flash_error_t sn32_flash_check_errors(EFlashDriver *eflp) { + uint32_t error = eflp->flash->STATUS_b.ERR; + + /* Clearing error conditions.*/ + eflp->flash->STATUS_b.ERR = 0; + + /* Decoding relevant errors.*/ + if ((error) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = SN_FLASH; +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + eflp->flash->CTRL = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * @retval Pointer to single bank if DBM not enabled. + * @retval Pointer to bank1 if DBM enabled. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + + (void)instance; + + return &efl_lld_descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + sn32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Program operation. + * @note The device supports ECC, it is only possible to write erased + * pages once except when writing all zeroes. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ + +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + volatile uint32_t *flash_base = (volatile uint32_t *)efl_lld_descriptor.address; + uint32_t erased_val = (efl_lld_descriptor.attributes & FLASH_ATTR_ERASED_IS_ONE) ? + UINT32_MAX : 0U; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + // Align size to SN32_FLASH_LINE_SIZE (8 bytes) + size_t aligned_size = (n + SN32_FLASH_LINE_MASK) & ~SN32_FLASH_LINE_MASK; + devp->state = FLASH_PGM; + + // Clear previous error flags and enable programming + sn32_flash_clear_status(devp); + sn32_flash_enable_pgm(devp); + + for (size_t i = 0; i < aligned_size; i += SN32_FLASH_LINE_SIZE) { + size_t abs_offset = offset + i; + volatile uint32_t *addr = flash_base + (abs_offset / sizeof(uint32_t)); + + // Read current contents of flash + uint32_t existing_word0 = addr[0]; + uint32_t existing_word1 = addr[1]; + + // Load new data (0-padded if beyond n) + uint32_t word0 = erased_val; + uint32_t word1 = erased_val; + size_t remaining = n - i; + + if (remaining >= (SN32_FLASH_LINE_SIZE / 2)) { + memcpy(&word0, pp + i, (SN32_FLASH_LINE_SIZE / 2)); + if (remaining >= SN32_FLASH_LINE_SIZE) { + memcpy(&word1, pp + i + (SN32_FLASH_LINE_SIZE / 2), (SN32_FLASH_LINE_SIZE / 2)); + } else { + memcpy(&word1, pp + i + (SN32_FLASH_LINE_SIZE / 2), remaining - (SN32_FLASH_LINE_SIZE / 2)); + } + } else { + memcpy(&word0, pp + i, remaining); + } + + // Skip if both words already match erased state + if ((existing_word0 != erased_val) || (existing_word1 != erased_val)) { + flash_sector_t sector = (abs_offset) / efl_lld_descriptor.sectors_size; + err = efl_lld_start_erase_sector(instance, sector); + devp->state = FLASH_READY; + if (err != FLASH_NO_ERROR) return err; + + // Restore programming mode and address + devp->state = FLASH_PGM; + sn32_flash_clear_status(devp); + sn32_flash_enable_pgm(devp); + } + + // Set address + devp->flash->ADDR = (uint32_t)(flash_base + (abs_offset / sizeof(uint32_t))); + + // Write two words (8 bytes) + devp->flash->DATA = word0; + devp->flash->DATA = word1; + + // Trigger programming + sn32_flash_start_pgm(devp); + sn32_flash_wait_busy(devp); + + if (devp->flash->STATUS & SN32_FLASH_STATUS_ERROR) { + sn32_flash_clear_status(devp); + devp->state = FLASH_READY; + return FLASH_ERROR_PROGRAM; + } + + // Re-enable programming for next chunk if any + if (i + SN32_FLASH_LINE_SIZE < aligned_size) { + sn32_flash_enable_pgm(devp); + } + } + + devp->state = FLASH_READY; + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function only erases bank 2 if it is present. Bank 1 is not + * allowed since it is normally where the primary program is located. + * Pages on bank 1 can be individually erased. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + (void) instance; + + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * this is an index within the total sectors + * in a flash bank + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + sn32_flash_clear_status(devp); + + /* Enable page erase.*/ + devp->flash->CTRL = SN32_FLASH_CTRL_PER; + + /* Set the page.*/ + devp->flash->ADDR = (uint32_t)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + sn32_flash_wait_busy(devp); + + /* Start the erase.*/ + sn32_flash_start_pgm(devp); + sn32_flash_wait_busy(devp); + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[out] msec recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if ((devp->flash->STATUS & SN32_FLASH_STATUS_BUSY) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CTRL &= ~(SN32_FLASH_CTRL_PER | SN32_FLASH_CTRL_MER); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + } + else { + /* Recommended time before polling again. This is a simplified + implementation.*/ + if (msec != NULL) { + *msec = (uint32_t)SN32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector.*/ + address = (uint32_t *)(SN32_FLASH_BASE + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + uint32_t erased_val = (efl_lld_descriptor.attributes & FLASH_ATTR_ERASED_IS_ONE) ? + UINT32_MAX : 0U; + uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); + for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { + if (*address != erased_val) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F290/hal_efl_lld.h b/os/hal/ports/SN32/SN32F290/hal_efl_lld.h new file mode 100644 index 0000000000..b298ff68e6 --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/hal_efl_lld.h @@ -0,0 +1,129 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + Copyright (C) 2025 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief SN32F29x Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define SN32_FLASH_CTRL_PG 0x00000001 +#define SN32_FLASH_CTRL_PER 0x00000002 +#define SN32_FLASH_CTRL_MER 0x00000004 +#define SN32_FLASH_CTRL_START 0x00000040 +#define SN32_FLASH_CTRL_CHK 0x00000080 + +#define SN32_FLASH_STATUS_BUSY 0x00000001 +#define SN32_FLASH_STATUS_ERROR 0x00000004 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SN32F24xB configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(SN32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define SN32_FLASH_WAIT_TIME_MS 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(SN32_FLASH_SECTOR_SIZE) +#error "SN32_FLASH_SECTOR_SIZE not defined in registry" +#endif + +#if !defined(SN32_FLASH_NUMBER_OF_BANKS) +#error "SN32_FLASH_NUMBER_OF_BANKS not defined in registry" +#endif + +#if !defined(SN32_FLASH_SECTORS_PER_BANK) +#error "SN32_FLASH_SECTORS_PER_BANK not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + SN_FLASH_Type *flash + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c b/os/hal/ports/SN32/SN32F290/hal_lld.c similarity index 50% rename from os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c rename to os/hal/ports/SN32/SN32F290/hal_lld.c index 5935e92ddb..a74371be64 100644 --- a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c +++ b/os/hal/ports/SN32/SN32F290/hal_lld.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2024 Dimitris Mantzouranis Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,16 +15,15 @@ */ /** - * @file GPIOv3/hal_pal_lld.c - * @brief SN32 PAL low level driver code. + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. * - * @addtogroup PAL + * @addtogroup HAL * @{ */ #include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) +#include /*===========================================================================*/ /* Driver local definitions. */ @@ -42,13 +41,6 @@ /* Driver local functions. */ /*===========================================================================*/ -static void initgpio(SN_GPIO0_Type *gpiop, const sn32_gpio_setup_t *config) { - - gpiop->DATA = config->data; - gpiop->MODE = config->mode; - gpiop->CFG = config->cfg; -} - /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -58,90 +50,25 @@ static void initgpio(SN_GPIO0_Type *gpiop, const sn32_gpio_setup_t *config) { /*===========================================================================*/ /** - * @brief SN32 I/O ports configuration. - * @details Ports A-D clocks enabled. - * - * @param[in] config the SN32 ports configuration + * @brief SN32F29x clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. * - * @notapi + * @special */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Initial GPIO setup. - */ - -#if SN32_HAS_GPIOA - initgpio(GPIOA, &config->PAData); -#endif -#if SN32_HAS_GPIOB - initgpio(GPIOB, &config->PBData); -#endif -#if SN32_HAS_GPIOC - initgpio(GPIOC, &config->PCData); -#endif -#if SN32_HAS_GPIOD - initgpio(GPIOD, &config->PDData); -#endif - +void sn32_clock_init(void) { + SystemCoreClockUpdate(); + FlashClockUpdate(); } /** - * @brief Pad mode setup. - * @details This function programs a pad - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum - * speed. - * - * @param[in] port the port identifier - * @param[in] pad the pad number - * @param[in] mode the mode + * @brief Low level HAL driver initialization. * * @notapi */ -void _pal_lld_setpadmode(ioportid_t port, - uint32_t pad, - iomode_t mode) { - - switch (mode) - { - - case PAL_MODE_UNCONNECTED: - break; - - case PAL_MODE_INPUT: - port->MODE &= ~(1 << pad); - break; - - case PAL_MODE_INPUT_PULLUP: - port->MODE &= ~(1 << pad); - port->CFG &= ~(3 << (pad * 2)); - // port->BSET = (1 << pad); // High 1 - break; - - case PAL_MODE_INPUT_PULLDOWN: - port->MODE &= ~(1 << pad); - port->CFG &= ~(3 << (pad * 2)); - // port->BCLR = (1 << pad); // Low 0 - break; - - case PAL_MODE_INPUT_ANALOG: - port->MODE &= ~(1 << pad); - port->CFG &= ~(3 << (pad * 2)); - break; - - case PAL_MODE_OUTPUT_PUSHPULL: - port->MODE |= (1 << pad); - break; - - case 7: - break; - - default: - break; - } +void hal_lld_init(void) { + SystemInit(); + sn32_clock_init(); } -#endif /* HAL_USE_PAL */ - /** @} */ diff --git a/os/hal/ports/SN32/SN32F290/hal_lld.h b/os/hal/ports/SN32/SN32F290/hal_lld.h new file mode 100644 index 0000000000..8dc4634f3a --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/hal_lld.h @@ -0,0 +1,96 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "sn32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SN32F29x" +/** @} */ + +/** + * @brief Requires use of SPIv2 driver model. + */ +#define HAL_LLD_SELECT_SPI_V2 TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +#define SN32_HCLK SystemCoreClock +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "sn32_ct.h" +#include "sn32_sys1.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void sn32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F290/platform.mk b/os/hal/ports/SN32/SN32F290/platform.mk new file mode 100644 index 0000000000..5c86ada8f1 --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/platform.mk @@ -0,0 +1,35 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F290/hal_lld.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F290/hal_efl_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F290 + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif + +# Drivers compatible with the platform. +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/ADC/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) \ No newline at end of file diff --git a/os/hal/ports/SN32/SN32F290/sn32_registry.h b/os/hal/ports/SN32/SN32F290/sn32_registry.h new file mode 100644 index 0000000000..c68bc151bd --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/sn32_registry.h @@ -0,0 +1,233 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F290/sn32_registry.h + * @brief SN32F29x capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef SN32_REGISTRY_H +#define SN32_REGISTRY_H + +/* Common identifier of all SN32F2xx devices.*/ +#if !defined(SN32F2xx) || defined(__DOXYGEN__) +#define SN32F2xx +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SN32F29x capabilities + * @{ + */ + +/* Common identifier of all SN32F24xB devices.*/ +#if !defined(SN32F290) || defined(__DOXYGEN__) +#define SN32F290 +#endif + +/* + * ST unit + */ +#define SN32_ST_HANDLER Vector3C +#define SN32_ST_NUMBER SysTick_IRQn + +/* + * NDT unit. + */ +#define SN32_NDT_HANDLER Vector40 +#define SN32_NDT_NUMBER NDT_IRQn + +/* + * USB unit. + */ +#define SN32_USB_HANDLER Vector44 +#define SN32_USB_NUMBER USB_IRQn +#define SN32_HAS_USB TRUE + +#define USBD_INTSTS_EPEVT_Pos USBD_INTSTS_EPEVT0_Pos +#define USBD_INTSTS_EPEVT_Msk (0xFFul << USBD_INTSTS_EPEVT_Pos) + +/* + * LCD unit. + */ +#define SN32_LCD_HANDLER Vector48 +#define SN32_LCD_NUMBER LCD_IRQn + +/* + * I2S units. + */ +#define SN32_I2S0_HANDLER Vector4C +#define SN32_I2S1_HANDLER Vector50 + +#define SN32_I2S0_NUMBER I2S0_IRQn +#define SN32_I2S1_NUMBER I2S1_IRQn + +/* + * CMP units. + */ +#define SN32_CMP0_HANDLER VectorAC +#define SN32_CMP1_HANDLER Vector88 +#define SN32_CMP2_HANDLER Vector70 +#define SN32_CMP3_HANDLER Vector54 + +#define SN32_CMP0_NUMBER CMP0_IRQn +#define SN32_CMP1_NUMBER CMP1_IRQn +#define SN32_CMP2_NUMBER CMP2_IRQn +#define SN32_CMP3_NUMBER CMP3_IRQn + +/* + * SPI units. + */ +#define SN32_SPI0_HANDLER Vector58 +#define SN32_SPI1_HANDLER Vector5C + +#define SN32_SPI0_NUMBER SPI0_IRQn +#define SN32_SPI1_NUMBER SPI1_IRQn + +#define SN32_HAS_SPI0 TRUE +#define SN32_HAS_SPI1 TRUE + +/* + * UART units. + */ +#define SN32_UART0_HANDLER Vector74 +#define SN32_UART1_HANDLER Vector78 +#define SN32_UART2_HANDLER Vector60 +#define SN32_UART3_HANDLER Vector64 + +#define SN32_UART0_NUMBER UART0_IRQn +#define SN32_UART1_NUMBER UART1_IRQn +#define SN32_UART2_NUMBER UART2_IRQn +#define SN32_UART3_NUMBER UART3_IRQn + +#define SN32_HAS_UART0 TRUE +#define SN32_HAS_UART1 TRUE +#define SN32_HAS_UART2 TRUE +#define SN32_HAS_UART3 TRUE + + +/* + * I2C units. + */ +#define SN32_I2C0_GLOBAL_HANDLER Vector68 +#define SN32_I2C1_GLOBAL_HANDLER Vector6C + +#define SN32_I2C0_GLOBAL_NUMBER I2C0_IRQn +#define SN32_I2C1_GLOBAL_NUMBER I2C0_IRQn + +#define SN32_HAS_I2C0 TRUE +#define SN32_HAS_I2C1 TRUE + +/* + * CT16 units. + */ +#define SN32_CT16B0_HANDLER Vector7C +#define SN32_CT16B1_HANDLER Vector80 +#define SN32_CT16B2_HANDLER Vector84 +#define SN32_CT16B3_HANDLER Vector8C +#define SN32_CT16B4_HANDLER Vector90 +#define SN32_CT16B5_HANDLER Vector94 + +#define SN32_CT16B0_NUMBER CT16B0_IRQn +#define SN32_CT16B1_NUMBER CT16B1_IRQn +#define SN32_CT16B2_NUMBER CT16B2_IRQn +#define SN32_CT16B3_NUMBER CT16B3_IRQn +#define SN32_CT16B4_NUMBER CT16B4_IRQn +#define SN32_CT16B5_NUMBER CT16B5_IRQn + +#define SN32_HAS_CT16B0 TRUE +#define SN32_HAS_CT16B1 TRUE +#define SN32_HAS_CT16B2 TRUE +#define SN32_HAS_CT16B3 TRUE +#define SN32_HAS_CT16B4 TRUE +#define SN32_HAS_CT16B5 TRUE + +/* + * EBI unit. + */ +#define SN32_EBI_HANDLER Vector98 +#define SN32_EBI_NUMBER EBI_IRQn + +/* + * RTC unit. + */ +#define SN32_RTC_HANDLER Vector9C +#define SN32_RTC_NUMBER RTC_IRQn +#define SN32_HAS_RTC TRUE +/* + * ADC unit. + */ +#define SN32_ADC_HANDLER VectorA0 +#define SN32_ADC_NUMBER ADC_IRQn +#define SN32_HAS_ADC TRUE + +/* + * WDT unit. + */ +#define SN32_WDT_HANDLER VectorA4 +#define SN32_WDT_NUMBER WDT_IRQn + +/* + * LVD unit. + */ +#define SN32_LVD_HANDLER VectorA8 +#define SN32_LVD_NUMBER LVD_IRQn + +/* + * GPIO units. + */ +#define SN32_GPIOD_HANDLER VectorB0 +#define SN32_GPIOC_HANDLER VectorB4 +#define SN32_GPIOB_HANDLER VectorB8 +#define SN32_GPIOA_HANDLER VectorBC + +#define SN32_GPIOD_NUMBER P3_IRQn +#define SN32_GPIOC_NUMBER P2_IRQn +#define SN32_GPIOB_NUMBER P1_IRQn +#define SN32_GPIOA_NUMBER P0_IRQn + +#define SN32_HAS_GPIOD TRUE +#define SN32_HAS_GPIOC TRUE +#define SN32_HAS_GPIOB TRUE +#define SN32_HAS_GPIOA TRUE + +/* + * FLASH units. + */ +#define SN32_JUMPLOADER_SIZE 0x200 +#define SN32_FLASH_LINE_SIZE 8U +#define SN32_FLASH_NUMBER_OF_BANKS 1 +#define SN32_FLASH_SECTORS_PER_BANK 256U +#define SN32_FLASH_SECTOR_SIZE 1024U +#define SN32_FLASH_BASE 0x00000000UL +#define FLASH_SIZE (SN32_FLASH_NUMBER_OF_BANKS * SN32_FLASH_SECTORS_PER_BANK * SN32_FLASH_SECTOR_SIZE) +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + + + +/** @} */ + +#endif /* SN32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F290/sn32_sys1.h b/os/hal/ports/SN32/SN32F290/sn32_sys1.h new file mode 100644 index 0000000000..239fbc0fee --- /dev/null +++ b/os/hal/ports/SN32/SN32F290/sn32_sys1.h @@ -0,0 +1,696 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F290/sn32_sys1.h + * @brief SYS1 helper driver header. + * @note This file requires definitions from the SN32 header file + * @p SN32F290.h. + * + * @addtogroup SN32F29x_SYS1 + * @{ + */ + +#ifndef SN32_SYS1_H +#define SN32_SYS1_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic AHB operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1EnableAHB(mask) { \ + SN_SYS1->AHBCLKEN |= (mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1DisableAHB(mask) { \ + SN_SYS1->AHBCLKEN &= ~(mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB0 bus. + * + * @param[in] mask APB peripherals mask + * + * @api + */ +#define sys1SelectAPB0(mask) { \ + SN_SYS1->APBCP0 |= (mask); \ + (void)SN_SYS1->APBCP0; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB peripherals mask + * + * @api + */ +#define sys1SelectAPB1(mask) { \ + SN_SYS1->APBCP1 |= (mask); \ + (void)SN_SYS1->APBCP1; \ +} + +/** @} */ +/** + * @name Dummy GPIO peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the GPIO peripherals clock. + * + * @api + */ +#define sys1EnableP0() +#define sys1EnableP1() +#define sys1EnableP2() +#define sys1EnableP3() +/** + * @brief Disables the GPIO peripherals clock. + * + * @api + */ +#define sys1DisableP0() +#define sys1DisableP1() +#define sys1DisableP2() +#define sys1DisableP3() + +/** @} */ + +/** + * @name OPA peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the OPA peripheral clock. + * + + * + * @api + */ +#define sys1EnableOPA() sys1EnableAHB(0x1<<3) + +/** + * @brief Disables the OPA peripheral clock. + * + * @api + */ +#define sys1DisableOPA() sys1DisableAHB(0x1<<3) + +/** + * @name USB peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @api + */ +#define sys1EnableUSB() sys1EnableAHB(0x1<<4) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define sys1DisableUSB() sys1DisableAHB(0x1<<4) + +/** + * @name CT16B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B0() sys1EnableAHB(0x1<<5) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B0() sys1DisableAHB(0x1<<5) + +/** + * @name CT16B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B1() sys1EnableAHB(0x1<<6) + +/** + * @brief Disables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B1() sys1DisableAHB(0x1<<6) + +/** + * @name CT16B2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B2 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B2() sys1EnableAHB(0x1<<7) + +/** + * @brief Disables the CT16B2 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B2() sys1DisableAHB(0x1<<7) + +/** + * @name CT16B3 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B3 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B3() sys1EnableAHB(0x1<<8) + +/** + * @brief Disables the CT16B3 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B3() sys1DisableAHB(0x1<<8) + +/** + * @name CT16B4 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B4 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B4() sys1EnableAHB(0x1<<9) + +/** + * @brief Disables the CT16B4 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B4() sys1DisableAHB(0x1<<9) + +/** + * @name CT16B5 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B5 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B5() sys1EnableAHB(0x1<<10) + +/** + * @brief Disables the CT16B5 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B5() sys1DisableAHB(0x1<<10) + +/** + * @name ADC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @api + */ +#define sys1EnableADC() sys1EnableAHB(0x1<<11) + +/** + * @brief Disables the ADC peripheral clock. + * + * @api + */ +#define sys1DisableADC() sys1DisableAHB(0x1<<11) + +/** + * @name SPI0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI0 peripheral clock. + * + * @api + */ +#define sys1EnableSPI0() sys1EnableAHB(0x1<<12) + +/** + * @brief Disables the SPI0 peripheral clock. + * + * @api + */ +#define sys1DisableSPI0() sys1DisableAHB(0x1<<12) + +/** + * @name SPI1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @api + */ +#define sys1EnableSPI1() sys1EnableAHB(0x1<<13) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define sys1DisableSPI1() sys1DisableAHB(0x1<<13) + +/** + * @name CMP peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CMP peripheral clock. + * + * @api + */ +#define sys1EnableCMP() sys1EnableAHB(0x1<<14) + +/** + * @brief Disables the CMP peripheral clock. + * + * @api + */ +#define sys1DisableCMP() sys1DisableAHB(0x1<<14) + +/** + * @name EBI peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the EBI peripheral clock. + * + * @api + */ +#define sys1EnableEBI() sys1EnableAHB(0x1<<15) + +/** + * @brief Disables the EBI peripheral clock. + * + * @api + */ +#define sys1DisableEBI() sys1DisableAHB(0x1<<15) + +/** + * @name UART0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART0 peripheral clock. + * + * @api + */ +#define sys1EnableUART0() sys1EnableAHB(0x1<<16) + +/** + * @brief Disables the UART0 peripheral clock. + * + * @api + */ +#define sys1DisableUART0() sys1DisableAHB(0x1<<16) + +/** + * @name UART1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART1 peripheral clock. + * + * @api + */ +#define sys1EnableUART1() sys1EnableAHB(0x1<<17) + +/** + * @brief Disables the UART1 peripheral clock. + * + * @api + */ +#define sys1DisableUART1() sys1DisableAHB(0x1<<17) + +/** + * @name UART2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART2 peripheral clock. + * + * @api + */ +#define sys1EnableUART2() sys1EnableAHB(0x1<<18) + +/** + * @brief Disables the UART2 peripheral clock. + * + * @api + */ +#define sys1DisableUART2() sys1DisableAHB(0x1<<18) + +/** + * @name UART3 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART3 peripheral clock. + * + * @api + */ +#define sys1EnableUART3() sys1EnableAHB(0x1<<19) + +/** + * @brief Disables the UART3 peripheral clock. + * + * @api + */ +#define sys1DisableUART3() sys1DisableAHB(0x1<<19) + +/** + * @name I2C0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C0 peripheral clock. + * + * @api + */ +#define sys1EnableI2C0() sys1EnableAHB(0x1<<21) + +/** + * @brief Disables the I2C0 peripheral clock. + * + * @api + */ +#define sys1DisableI2C0() sys1DisableAHB(0x1<<21) + +/** + * @name I2C1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @api + */ +#define sys1EnableI2C1() sys1EnableAHB(0x1<<20) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define sys1DisableI2C1() sys1DisableAHB(0x1<<20) + +/** + * @name I2S0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2S0 peripheral clock. + * + * @api + */ +#define sys1EnableI2S0() sys1EnableAHB(0x1<<22) + +/** + * @brief Disables the I2S0 peripheral clock. + * + * @api + */ +#define sys1DisableI2S0() sys1DisableAHB(0x1<<22) + +/** + * @name RTC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the RTC peripheral clock. + * + * @api + */ +#define sys1EnableRTC() sys1EnableAHB(0x1<<23) + +/** + * @brief Disables the RTC peripheral clock. + * + * @api + */ +#define sys1DisableRTC() sys1DisableAHB(0x1<<23) + +/** + * @name WDT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the WDT peripheral clock. + * + * @api + */ +#define sys1EnableWDT() sys1EnableAHB(0x1<<24) + +/** + * @brief Disables the WDT peripheral clock. + * + * @api + */ +#define sys1DisableWDT() sys1DisableAHB(0x1<<24) + +/** + * @name I2S1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2S1 peripheral clock. + * + * @api + */ +#define sys1EnableI2S1() sys1EnableAHB(0x1<<25) + +/** + * @brief Disables the I2S1 peripheral clock. + * + * @api + */ +#define sys1DisableI2S1() sys1DisableAHB(0x1<<25) + +/** + * @name LCD peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the LCD peripheral clock. + * + * @api + */ +#define sys1EnableLCD() sys1EnableAHB(0x1<<26) + +/** + * @brief Disables the LCD peripheral clock. + * + * @api + */ +#define sys1DisableLCD() sys1DisableAHB(0x1<<26) + +/** + * @name CRC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CRC peripheral clock. + * + * @api + */ +#define sys1EnableCRC() sys1EnableAHB(0x1<<27) + +/** + * @brief Disables the CRC peripheral clock. + * + * @api + */ +#define sys1DisableCRC() sys1DisableAHB(0x1<<27) + +/** + * @name CLKOUT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CLKOUT peripheral clock. + * + * @param[in] clkval clock output source + * * @api + */ +#define sys1EnableCLKOUT(clkval) { \ + if(clkval > 0) \ + sys1EnableAHB(clkval<<28) \ +} + +/** + * @brief Disables the CLKOUT peripheral clock. + * + * @api + */ +#define sys1DisableCLKOUT() { \ + SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Configures the I2C0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<8) \ +} + +/** + * @brief Configures the I2S0 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2S0PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<12) \ +} + +/** + * @brief Configures the I2S1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2S1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<15) \ +} + +/** + * @brief Configures the WDT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectWDTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<20) \ +} + +/** + * @brief Configures the I2C1 peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectI2C1PRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<24) \ +} + +/** + * @brief Configures the CLKOUT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCLKOUTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB1(pre<<28) \ +} + +/** + * @brief Configures the ADC peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectADCPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB0(pre<<16) \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* SN32_SYS1_H */ + +/** @} */