diff --git a/adder.t.v b/adder.t.v
index 76109ed..e5c9fed 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,28 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    // behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+    $dumpfile("adderTest.vcd");
+    $dumpvars(0,testFullAdder);
+    $display("a b carryin | sum carryout  | Expected Output");
+	a=0;b=0;carryin=0;	#1000
+	$display("%b %b    %b    |  %b      %b     | 0 0", a, b, carryin, sum, carryout);
+	a=0;b=0;carryin=1;	#1000
+	$display("%b %b    %b    |  %b      %b     | 1 0", a, b, carryin, sum, carryout);
+	a=1;b=0;carryin=0;	#1000
+	$display("%b %b    %b    |  %b      %b     | 1 0", a, b, carryin, sum, carryout);
+	a=1;b=0;carryin=1;	#1000
+	$display("%b %b    %b    |  %b      %b     | 0 1", a, b, carryin, sum, carryout);
+	a=0;b=1;carryin=0;	#1000
+	$display("%b %b    %b    |  %b      %b     | 1 0", a, b, carryin, sum, carryout);
+	a=0;b=1;carryin=1;	#1000
+	$display("%b %b    %b    |  %b      %b     | 0 1", a, b, carryin, sum, carryout);
+	a=1;b=1;carryin=0;	#1000
+	$display("%b %b    %b    |  %b      %b     | 0 1", a, b, carryin, sum, carryout);
+	a=1;b=1;carryin=1;	#1000
+	$display("%b %b    %b    |  %b      %b     | 1 1", a, b, carryin, sum, carryout);
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..9a55fe8 100644
--- a/adder.v
+++ b/adder.v
@@ -20,5 +20,26 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire ab;
+    wire acarryin;
+    wire bcarryin;
+    wire orpairintermediate;
+    wire orsingleintermediate;
+    wire orall;
+    wire andsumintermediate;
+    wire andsingleintermediate;
+    wire andall;
+    wire invcarryout;
+    and #(50) andab(ab, a, b);
+    and #(50) andacarryin(acarryin, a, carryin);
+    and #(50) andbcarryin(bcarryin, b, carryin);
+    or #(50) orpair(orpairintermediate, ab, acarryin);
+    or #(50) orcarryout(carryout, orpairintermediate, bcarryin);
+    or #(50) orintermediate(orsingleintermediate, a, b);
+    or #(50) orallinputs(orall, orsingleintermediate, carryin);
+    not #(50) inv(invcarryout, carryout);
+    and #(50) sumintermediate(andsumintermediate, invcarryout, orall);
+    and #(50) andintermediate(andsingleintermediate, a, b);
+    and #(50) andallinputs(andall, andsingleintermediate, carryin);
+    or #(50) adder(sum, andsumintermediate, andall);
 endmodule
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..216085e 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    // behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoderTest.vcd");
+    $dumpvars(0,testDecoder);
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
diff --git a/decoder.v b/decoder.v
index 17836e0..89d6560 100644
--- a/decoder.v
+++ b/decoder.v
@@ -17,6 +17,21 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+    wire naddress0;
+    wire naddress1;
+    wire pos0;
+    wire pos1;
+    wire pos2;
+    wire pos3;
+    not invaddress0(naddress0, address0);
+    not invaddress1(naddress1, address1);
+    and #50 (pos0, naddress0, naddress1);
+    and #50 (pos1, address0, naddress1);
+    and #50 (pos2, naddress0, address1);
+    and #50 (pos3, address0, address1);
+    and #50 (out0, pos0, enable);
+    and #50 (out1, pos1, enable);
+    and #50 (out2, pos2, enable);
+    and #50 (out3, pos3, enable);
 endmodule
 
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..a956e68 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,26 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  reg address0, address1;
+  reg  in0, in1, in2, in3;
+  wire out;
+
+  // behavioralMultiplexer mux (out, address0, address1, in0, in1, in2, in3);
+  structuralMultiplexer mux (out, address0, address1, in0, in1, in2, in3);
+
+  initial begin
+  $dumpfile("multiplexerTest.vcd");
+  $dumpvars(0,testMultiplexer);
+  $display("A0 A1 i0 i1 i2 i3| out | Expected Output");
+	address0=0;address1=0;in0=0;in1=0;in2=0;in3=0; #1000
+	$display("%b  %b  %b  %b  %b  %b |  %b  | False", address0, address1, in0, in1, in2, in3, out);
+	address0=0;address1=0;in0=1;in1=0;in2=0;in3=0; #1000
+	$display("%b  %b  %b  %b  %b  %b |  %b  | True", address0, address1, in0, in1, in2, in3, out);
+	address0=1;address1=0;in0=0;in1=1;in2=0;in3=0; #1000
+	$display("%b  %b  %b  %b  %b  %b |  %b  | True", address0, address1, in0, in1, in2, in3, out);
+	address0=0;address1=1;in0=0;in1=0;in2=1;in3=0; #1000
+	$display("%b  %b  %b  %b  %b  %b |  %b  | True", address0, address1, in0, in1, in2, in3, out);
+	address0=1;address1=1;in0=0;in1=0;in2=0;in3=1; #1000
+	$display("%b  %b  %b  %b  %b  %b |  %b  | True", address0, address1, in0, in1, in2, in3, out);
+  end
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..45d06dd 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -19,6 +19,26 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire in0nadd0;
+    wire in1add0;
+    wire in2nadd0;
+    wire in3add0;
+    wire or0;
+    wire or1;
+    wire int0nadd1;
+    wire int1add1;
+    wire naddress0;
+    wire naddress1;
+    not #(50) invaddress0(naddress0, address0);
+    not #(50) invaddress1(naddress1, address1);
+    and #(50) andin0nadd0(in0nadd0, in0, naddress0);
+    and #(50) andin1add0(in1add0, in1, address0);
+    and #(50) andin2nadd0(in2nadd0, in2, naddress0);
+    and #(50) andin3add0(in3add0, in3, address0);
+    or #(50) ornadd1(or0, in0nadd0, in1add0);
+    or #(50) oradd1(or1, in2nadd0, in3add0);
+    and #(50) andint0nadd1(int0nadd1, or0, naddress1);
+    and #(50) andint1add1(int1add1, or1, address1);
+    or #(50) ans(out, int0nadd1, int1add1);
 endmodule
 
diff --git a/tests_waves.pdf b/tests_waves.pdf
new file mode 100644
index 0000000..968fa7d
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