diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..f47cb20
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.out
diff --git a/README.md b/README.md
index b650dc1..11adbac 100644
--- a/README.md
+++ b/README.md
@@ -1,84 +1,20 @@
 # HW 0b010: Verilog Building Blocks
 
-Due: September 23rd
+Jonah Spear
 
-This homework prepares some of the gate level primitives you will use in the design of your processor.  You will reuse these modules in several future designs.  Therefore, the structure and test will be in separate modules.
+The purpose of the homework was to build several digital circucit building-blocks in verilog. All of the code was tested using icarus verilog. 
 
-This homework is to be done individually.
+## Multiplexer
 
-## The Devices
+![Multiplexer Truth Table](/resources/mux_table.png?raw=true)
+![Multiplexer Signal Trace](/resources/mux_test.png?raw=true)
 
-This homework is based on the following three devices:
+## Decoder
 
-1. 2-bit decoder with enable (2+1 inputs, 4 outputs)
-1. 4:1 (four input multiplexer)
-1. 1-bit full adder
+![Decoder Truth Table](/resources/decoder_table.png?raw=true)
+![Decoder Signal Trace](/resources/decoder_test.png?raw=true)
 
-For each of these three devices, you will do the following:
-
-1. Write a test bench to test the functionality of the device.
-1. Test your test bench against my version of the device.
-1. Write your own version of the device.
-1. Test your device against your test bench.
-
-## The Test Benches
-For each device, first write a test bench that verifies the appropriate behavior of your device.  We have already completed this for you for the 2 bit decoder as an example, so you will only have to write the other two.
-
-The test bench should:
-
-1. Instantiate a copy of the device it is testing (Device Under Test = DUT)
-1. Show what the truth table should be
-1. Show what the truth table is
-
-## The Behavioral Devices
-We've provided versions of each of the three devices in a language subset called "Behavioral Verilog".  Use these versions to test your test benches.  Connect the test bench to the device definition provided and verify that your test bench passes with the given behavioral device.
-
-## The Structural Devices
-Create the three devices in Structural Verilog, using only the gate primitives we have already gone over:
-```verilog
-NOT AND NAND OR NOR XOR
-```
-
-Do not use behavioral constructs such as `assign` or `case`.
-
-Give all of your gates a delay of 50 units of time.
-
-## The Write Up
-Create a PDF or Markdown file demonstrating your circuits working correctly. It should contain pictures of your test bench results and your waveforms that clearly show the gate propagation delays.  
-
-## Submission
-Please submit:
-
-1. Your 3 Verilog files
-2. Your writeup as a PDF or Markdown file
-3. The scripts you used to run the tests
-
-Push the work to your repo, then submit a pull request to the course repo (CompArchFA17/HW2) for us to respond to with feedback.
-
-## Hints / Tricks
-
-### Gate delays
-In order to model some sort of delay for our gates, simply put these statements at the top of your Verilog source:
-
-```verilog
-// define gates with delays
-`define AND and #50
-`define OR or #50
-`define NOT not #50
-```
-
-Then, when you go to instantiate an AND, for instance, instead of using just `and`, use `` `AND``. That is, back-tick followed by the define you specified. Think of the back-tick as a macro definition.
-
-That means that the gate, `` `AND``, has a delay of 50 units. Then, in your simulation, you should wait between transitions of the input long enough to allow the signals to propagate to the output of your circuit.
-
-### Signal Declaration
-You need to declare all your inputs and outputs and all the intermediate signals you use in your designs.   Thus, if you have the statement:
-```verilog
-and myandgate(out, in1, in2)
-```
-
-You need to have previously declared `out`, `in1`, and `in2`, to be some sort of physical entity (`wire`, `reg`).
-
-### Tutorials
-There are some Verilog resources listed on the [course website](http://sites.google.com/site/ca17fall/resources/verilog)
+## Adder
 
+![Adder Truth Table](/resources/adder_table.png?raw=true)
+![Adder Signal Trace](/resources/adder_test.png?raw=true)
diff --git a/adder.t.v b/adder.t.v
deleted file mode 100644
index 76109ed..0000000
--- a/adder.t.v
+++ /dev/null
@@ -1,14 +0,0 @@
-// Adder testbench
-`timescale 1 ns / 1 ps
-`include "adder.v"
-
-module testFullAdder();
-    reg a, b, carryin;
-    wire sum, carryout;
-
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
-
-    initial begin
-        // Your test code here
-    end
-endmodule
diff --git a/adder.v b/adder.v
deleted file mode 100644
index d21f7e4..0000000
--- a/adder.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// Adder circuit
-
-module behavioralFullAdder
-(
-    output sum, 
-    output carryout,
-    input a, 
-    input b, 
-    input carryin
-);
-    // Uses concatenation operator and built-in '+'
-    assign {carryout, sum}=a+b+carryin;
-endmodule
-
-module structuralFullAdder
-(
-    output sum, 
-    output carryout,
-    input a, 
-    input b, 
-    input carryin
-);
-    // Your adder code here
-endmodule
diff --git a/decoder.t.v b/decoder.t.v
deleted file mode 100644
index e0e925f..0000000
--- a/decoder.t.v
+++ /dev/null
@@ -1,33 +0,0 @@
-// Decoder testbench
-`timescale 1 ns / 1 ps
-`include "decoder.v"
-
-module testDecoder (); 
-    reg addr0, addr1;
-    reg enable;
-    wire out0,out1,out2,out3;
-
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
-
-    initial begin
-    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=0; #1000
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    end
-
-endmodule
diff --git a/decoder.v b/decoder.v
deleted file mode 100644
index 17836e0..0000000
--- a/decoder.v
+++ /dev/null
@@ -1,22 +0,0 @@
-// Decoder circuit
-
-module behavioralDecoder
-(
-    output out0, out1, out2, out3,
-    input address0, address1,
-    input enable
-);
-    // Uses concatenation and shift operators
-    assign {out3,out2,out1,out0}=enable<<{address1,address0};
-endmodule
-
-
-module structuralDecoder
-(
-    output out0, out1, out2, out3,
-    input address0, address1,
-    input enable
-);
-    // Your decoder code here
-endmodule
-
diff --git a/multiplexer.t.v b/multiplexer.t.v
deleted file mode 100644
index fd475c4..0000000
--- a/multiplexer.t.v
+++ /dev/null
@@ -1,7 +0,0 @@
-// Multiplexer testbench
-`timescale 1 ns / 1 ps
-`include "multiplexer.v"
-
-module testMultiplexer ();
-  // Your test code here
-endmodule
diff --git a/multiplexer.v b/multiplexer.v
deleted file mode 100644
index b05820f..0000000
--- a/multiplexer.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// Multiplexer circuit
-
-module behavioralMultiplexer
-(
-    output out,
-    input address0, address1,
-    input in0, in1, in2, in3
-);
-    // Join single-bit inputs into a bus, use address as index
-    wire[3:0] inputs = {in3, in2, in1, in0};
-    wire[1:0] address = {address1, address0};
-    assign out = inputs[address];
-endmodule
-
-
-module structuralMultiplexer
-(
-    output out,
-    input address0, address1,
-    input in0, in1, in2, in3
-);
-    // Your multiplexer code here
-endmodule
-
diff --git a/resources/adder.vcd b/resources/adder.vcd
new file mode 100644
index 0000000..35c3592
--- /dev/null
+++ b/resources/adder.vcd
@@ -0,0 +1,125 @@
+$date
+	Sun Sep 17 21:41:41 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testFullAdder $end
+$var wire 1 ! carryout $end
+$var wire 1 " sum $end
+$var reg 1 # a $end
+$var reg 1 $ b $end
+$var reg 1 % carryin $end
+$scope module adder $end
+$var wire 1 & _carryin $end
+$var wire 1 ' a $end
+$var wire 1 ( aandb $end
+$var wire 1 ) aorb $end
+$var wire 1 * b $end
+$var wire 1 + carryin $end
+$var wire 1 ! carryout $end
+$var wire 1 , outputIfCarryin $end
+$var wire 1 - outputIf_Carryin $end
+$var wire 1 . s $end
+$var wire 1 " sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z.
+z-
+x,
+0+
+0*
+z)
+z(
+0'
+z&
+0%
+0$
+0#
+x"
+x!
+$end
+#50000
+0-
+0)
+0(
+0.
+1&
+#100000
+0"
+0,
+#150000
+0!
+#1000000
+1#
+1'
+#1050000
+1.
+1)
+#1100000
+1"
+#2000000
+1$
+1*
+0#
+0'
+#3000000
+1#
+1'
+#3050000
+0.
+1(
+#3100000
+0"
+1,
+#3150000
+1!
+#4000000
+1%
+1+
+0$
+0*
+0#
+0'
+#4050000
+1"
+0&
+1-
+0(
+0)
+#4100000
+0,
+0-
+#4150000
+0!
+#5000000
+1#
+1'
+#5050000
+1.
+1)
+#5100000
+0"
+1-
+#5150000
+1!
+#6000000
+1$
+1*
+0#
+0'
+#7000000
+1#
+1'
+#7050000
+0.
+1(
+#7100000
+1"
+#8000000
diff --git a/resources/adder_table.png b/resources/adder_table.png
new file mode 100644
index 0000000..5ded78c
Binary files /dev/null and b/resources/adder_table.png differ
diff --git a/resources/adder_test.png b/resources/adder_test.png
new file mode 100644
index 0000000..826a0de
Binary files /dev/null and b/resources/adder_test.png differ
diff --git a/resources/decoder.vcd b/resources/decoder.vcd
new file mode 100644
index 0000000..2f0efa8
--- /dev/null
+++ b/resources/decoder.vcd
@@ -0,0 +1,146 @@
+$date
+	Sun Sep 17 21:14:19 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testDecoder $end
+$var wire 1 ! out0 $end
+$var wire 1 " out1 $end
+$var wire 1 # out2 $end
+$var wire 1 $ out3 $end
+$var reg 1 % addr0 $end
+$var reg 1 & addr1 $end
+$var reg 1 ' enable $end
+$scope module decoder $end
+$var wire 1 ( _a0 $end
+$var wire 1 ) _a1 $end
+$var wire 1 * a0 $end
+$var wire 1 + a1 $end
+$var wire 1 , enable $end
+$var wire 1 ! o0 $end
+$var wire 1 " o1 $end
+$var wire 1 # o2 $end
+$var wire 1 $ o3 $end
+$var wire 1 - p0 $end
+$var wire 1 . p1 $end
+$var wire 1 / p2 $end
+$var wire 1 0 p3 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z0
+z/
+z.
+x-
+0,
+0+
+0*
+z)
+z(
+0'
+0&
+0%
+z$
+z#
+z"
+z!
+$end
+#50000
+0$
+0#
+0"
+0!
+00
+0/
+0.
+1(
+1)
+#100000
+1-
+#1000000
+1%
+1*
+#1050000
+0(
+1.
+#1100000
+0-
+#2000000
+1&
+1+
+0%
+0*
+#2050000
+0)
+1(
+0.
+#2100000
+1/
+#3000000
+1%
+1*
+#3050000
+0(
+10
+#3100000
+0/
+#4000000
+0&
+0+
+0%
+0*
+1'
+1,
+#4050000
+1)
+1(
+00
+1$
+#4100000
+1-
+0$
+#4150000
+1!
+#5000000
+1%
+1*
+#5050000
+0(
+1.
+#5100000
+0-
+1"
+#5150000
+0!
+#6000000
+1&
+1+
+0%
+0*
+#6050000
+0)
+1(
+0.
+#6100000
+1/
+0"
+#6150000
+1#
+#7000000
+1%
+1*
+#7050000
+0(
+10
+#7100000
+0/
+1$
+#7150000
+0#
+#8000000
diff --git a/resources/decoder_table.png b/resources/decoder_table.png
new file mode 100644
index 0000000..c42a85c
Binary files /dev/null and b/resources/decoder_table.png differ
diff --git a/resources/decoder_test.png b/resources/decoder_test.png
new file mode 100644
index 0000000..367c14e
Binary files /dev/null and b/resources/decoder_test.png differ
diff --git a/resources/mux.vcd b/resources/mux.vcd
new file mode 100644
index 0000000..91f1d17
--- /dev/null
+++ b/resources/mux.vcd
@@ -0,0 +1,194 @@
+$date
+	Sun Sep 17 21:08:56 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testMultiplexer $end
+$var wire 1 ! out $end
+$var reg 1 " addr0 $end
+$var reg 1 # addr1 $end
+$var reg 1 $ in0 $end
+$var reg 1 % in1 $end
+$var reg 1 & in2 $end
+$var reg 1 ' in3 $end
+$scope module multiplexer $end
+$var wire 1 ( a0 $end
+$var wire 1 ) a1 $end
+$var wire 1 * b0 $end
+$var wire 1 + b1 $end
+$var wire 1 , b2 $end
+$var wire 1 - b3 $end
+$var wire 1 . in0 $end
+$var wire 1 / in1 $end
+$var wire 1 0 in2 $end
+$var wire 1 1 in3 $end
+$var wire 1 2 m0 $end
+$var wire 1 3 m1 $end
+$var wire 1 4 m2 $end
+$var wire 1 5 m3 $end
+$var wire 1 6 n0 $end
+$var wire 1 7 n1 $end
+$var wire 1 ! out $end
+$scope module decoder $end
+$var wire 1 8 _a0 $end
+$var wire 1 9 _a1 $end
+$var wire 1 ( a0 $end
+$var wire 1 ) a1 $end
+$var wire 1 : enable $end
+$var wire 1 * o0 $end
+$var wire 1 + o1 $end
+$var wire 1 , o2 $end
+$var wire 1 - o3 $end
+$var wire 1 ; p0 $end
+$var wire 1 < p1 $end
+$var wire 1 = p2 $end
+$var wire 1 > p3 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z>
+z=
+z<
+x;
+1:
+z9
+z8
+x7
+x6
+z5
+z4
+z3
+z2
+01
+00
+0/
+0.
+x-
+x,
+x+
+x*
+0)
+0(
+0'
+0&
+0%
+0$
+0#
+0"
+x!
+$end
+#50000
+0>
+0=
+0<
+05
+04
+03
+02
+18
+19
+#100000
+0-
+0,
+0+
+07
+06
+1;
+#150000
+0!
+1*
+#1000000
+1$
+1.
+#1050000
+12
+#1100000
+16
+#1150000
+1!
+#2000000
+0$
+0.
+1"
+1(
+#2050000
+02
+08
+1<
+#2100000
+06
+0;
+1+
+#2150000
+0!
+0*
+#3000000
+1%
+1/
+#3050000
+13
+#3100000
+16
+#3150000
+1!
+#4000000
+0%
+0/
+1#
+1)
+0"
+0(
+#4050000
+03
+09
+18
+0<
+#4100000
+06
+1=
+0+
+#4150000
+0!
+1,
+#5000000
+1&
+10
+#5050000
+14
+#5100000
+17
+#5150000
+1!
+#6000000
+0&
+00
+1"
+1(
+#6050000
+04
+08
+1>
+#6100000
+07
+0=
+1-
+#6150000
+0!
+0,
+#7000000
+1'
+11
+#7050000
+15
+#7100000
+17
+#7150000
+1!
+#8000000
diff --git a/resources/mux_table.png b/resources/mux_table.png
new file mode 100644
index 0000000..2c0ae5f
Binary files /dev/null and b/resources/mux_table.png differ
diff --git a/resources/mux_test.png b/resources/mux_test.png
new file mode 100644
index 0000000..8589c42
Binary files /dev/null and b/resources/mux_test.png differ
diff --git a/src/adder.t.v b/src/adder.t.v
new file mode 100644
index 0000000..6e2376f
--- /dev/null
+++ b/src/adder.t.v
@@ -0,0 +1,33 @@
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+module testFullAdder();
+    reg a, b, carryin;
+    wire sum, carryout;
+
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
+
+    initial begin
+      $dumpfile("../resources/adder.vcd");
+      $dumpvars;
+
+      $display("A B Cin | Cout Sum ");
+      a=0;b=0;carryin=0; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=1;b=0;carryin=0; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=0;b=1;carryin=0; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=1;b=1;carryin=0; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=0;b=0;carryin=1; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=1;b=0;carryin=1; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=0;b=1;carryin=1; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+      a=1;b=1;carryin=1; #1000;
+      $display("%b %b  %b  |  %b   %b", a, b, carryin, carryout, sum);
+    end
+endmodule
diff --git a/src/adder.v b/src/adder.v
new file mode 100644
index 0000000..557d4c8
--- /dev/null
+++ b/src/adder.v
@@ -0,0 +1,28 @@
+// Adder circuit
+
+// define gates with delays
+`define XOR xor #50
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
+module structuralFullAdder
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire aandb, aorb;
+    wire s, _carryin;
+    wire outputIfCarryin, outputIf_Carryin;
+    `XOR(s, a, b);
+    `XOR(sum, s, carryin);
+    `AND(aandb, a, b);
+    `OR(aorb, a, b);
+    `NOT(_carryin, carryin);
+    `AND(outputIfCarryin, aandb, _carryin);
+    `AND(outputIf_Carryin, aorb, carryin);
+    `OR(carryout, outputIfCarryin, outputIf_Carryin);
+endmodule
diff --git a/src/decoder.t.v b/src/decoder.t.v
new file mode 100644
index 0000000..e7cecb9
--- /dev/null
+++ b/src/decoder.t.v
@@ -0,0 +1,34 @@
+// Decoder testbench
+`timescale 1 ns / 1 ps
+`include "decoder.v"
+
+module testDecoder ();
+    reg addr0, addr1;
+    reg enable;
+    wire out0,out1,out2,out3;
+
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+
+    initial begin
+        $dumpfile("../resources/decoder.vcd");
+        $dumpvars;
+        $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
+        enable=0;addr0=0;addr1=0; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=1;addr1=0; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=0;addr1=1; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=1;addr1=1; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=0;addr1=0; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=1;addr1=0; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=0;addr1=1; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=1;addr1=1; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+    end
+
+endmodule
diff --git a/src/decoder.v b/src/decoder.v
new file mode 100644
index 0000000..93283d1
--- /dev/null
+++ b/src/decoder.v
@@ -0,0 +1,27 @@
+// Decoder circuit
+
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
+module structuralDecoder
+(
+    output o0, o1, o2, o3,
+    input a0, a1,
+    input enable
+);
+    wire _a0, _a1;
+    wire p0, p1, p2, p3;
+    `NOT(_a0, a0);
+    `NOT(_a1, a1);
+    `AND(p0, _a0, _a1);
+    `AND(p1, a0, _a1);
+    `AND(p2, _a0, a1);
+    `AND(p3, a0, a1);
+    `AND(o0, p0, enable);
+    `AND(o1, p1, enable);
+    `AND(o2, p2, enable);
+    `AND(o3, p3, enable);
+
+endmodule
diff --git a/src/multiplexer.t.v b/src/multiplexer.t.v
new file mode 100644
index 0000000..04f23d7
--- /dev/null
+++ b/src/multiplexer.t.v
@@ -0,0 +1,33 @@
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "multiplexer.v"
+
+module testMultiplexer ();
+  wire out;
+  reg addr0, addr1;
+  reg in0, in1, in2, in3;
+
+  structuralMultiplexer multiplexer (out,addr0,addr1,in0,in1,in2,in3);
+  initial begin
+    $dumpfile("../resources/mux.vcd");
+    $dumpvars;
+
+    $display("A0 A1 | I0 I1 I2 I3 | Out | Expected Behaviour");
+    addr0=0;addr1=0;in0=0;in1=0;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I0 Only (low)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=0;in0=1;in1=0;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I0 Only (high)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in0=0;in1=0;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I1 Only (low)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in0=0;in1=1;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I1 Only (high)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in0=0;in1=0;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I2 Only (low)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in0=0;in1=0;in2=1;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I2 Only (high)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in0=0;in1=0;in2=0;in3=0; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I3 Only (low)", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in0=0;in1=0;in2=0;in3=1; #1000
+    $display("%b  %b  | %b  %b  %b  %b  |  %b  | I3 Only (high)", addr0, addr1, in0, in1, in2, in3, out);
+    end
+endmodule
diff --git a/src/multiplexer.v b/src/multiplexer.v
new file mode 100644
index 0000000..319ed08
--- /dev/null
+++ b/src/multiplexer.v
@@ -0,0 +1,27 @@
+// Multiplexer circuit
+
+`include "decoder.v"
+
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
+module structuralMultiplexer
+(
+    output out,
+    input a0, a1,
+    input in0, in1, in2, in3
+);
+    wire b0, b1, b2, b3;
+    wire m0, m1, m2, m3;
+    wire n0, n1;
+    structuralDecoder decoder(b0, b1, b2, b3, a0, a1, 1);
+    `AND(m0, b0, in0);
+    `AND(m1, b1, in1);
+    `AND(m2, b2, in2);
+    `AND(m3, b3, in3);
+    `OR(n0, m0, m1);
+    `OR(n1, m2, m3);
+    `OR(out, n0, n1);
+endmodule