diff --git a/Deliverables1and6.pdf b/Deliverables1and6.pdf
new file mode 100644
index 0000000..fa107eb
Binary files /dev/null and b/Deliverables1and6.pdf differ
diff --git a/mux.v b/mux.v
new file mode 100644
index 0000000..50e7634
--- /dev/null
+++ b/mux.v
@@ -0,0 +1,58 @@
+
+//
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+	wire[31:0] inputsofmux;
+	wire       outputofmux;
+	assign outputofmux=inputsofmux[address];
+endmodule
+
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+
+  assign mux[0] = input0;		// Connect the sources of the array
+  assign mux[1] = input1;		// Connect the sources of the array
+  assign mux[2] = input2;		// Connect the sources of the array
+  assign mux[3] = input3;		// Connect the sources of the array
+  assign mux[4] = input4;		// Connect the sources of the array
+  assign mux[5] = input5;		// Connect the sources of the array
+  assign mux[6] = input6;		// Connect the sources of the array
+  assign mux[7] = input7;		// Connect the sources of the array
+  assign mux[8] = input8;		// Connect the sources of the array
+  assign mux[9] = input9;		// Connect the sources of the array
+  assign mux[10] = input10;		// Connect the sources of the array
+  assign mux[11] = input11;		// Connect the sources of the array
+  assign mux[12] = input12;		// Connect the sources of the array
+  assign mux[13] = input13;		// Connect the sources of the array
+  assign mux[14] = input14;		// Connect the sources of the array
+  assign mux[15] = input15;		// Connect the sources of the array
+  assign mux[16] = input16;		// Connect the sources of the array
+  assign mux[17] = input17;		// Connect the sources of the array
+  assign mux[18] = input18;		// Connect the sources of the array
+  assign mux[19] = input19;		// Connect the sources of the array
+  assign mux[20] = input20;		// Connect the sources of the array
+  assign mux[21] = input21;		// Connect the sources of the array
+  assign mux[22] = input22;		// Connect the sources of the array
+  assign mux[23] = input23;		// Connect the sources of the array
+  assign mux[24] = input24;		// Connect the sources of the array
+  assign mux[25] = input25;		// Connect the sources of the array
+  assign mux[26] = input26;		// Connect the sources of the array
+  assign mux[27] = input27;		// Connect the sources of the array
+  assign mux[28] = input28;		// Connect the sources of the array
+  assign mux[29] = input29;		// Connect the sources of the array
+  assign mux[30] = input30;		// Connect the sources of the array
+  assign mux[31] = input31;		// Connect the sources of the array
+
+  assign out = mux[address];	// Connect the output of the array
+endmodule
\ No newline at end of file
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..12f470a 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -3,6 +3,7 @@
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -35,6 +36,7 @@ module hw4testbenchharness();
   (
     .begintest(begintest),
     .endtest(endtest), 
+
     .dutpassed(dutpassed),
     .ReadData1(ReadData1),
     .ReadData2(ReadData2),
@@ -107,14 +109,14 @@ output reg		Clk
     dutpassed = 1;
     #10
 
+
   // Test Case 1: 
   //   Write '42' to register 2, verify with Read Ports 1 and 2
-  //   (Passes because example register file is hardwired to return 42)
-  WriteRegister = 5'd2;
+  WriteRegister = 5'd1;
   WriteData = 32'd42;
   RegWrite = 1;
-  ReadRegister1 = 5'd2;
-  ReadRegister2 = 5'd2;
+  ReadRegister1 = 5'd1;
+  ReadRegister2 = 5'd1;
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
   // Verify expectations and report test result
@@ -125,12 +127,11 @@ output reg		Clk
 
   // Test Case 2: 
   //   Write '15' to register 2, verify with Read Ports 1 and 2
-  //   (Fails with example register file, but should pass with yours)
-  WriteRegister = 5'd2;
+  WriteRegister = 5'd1;
   WriteData = 32'd15;
   RegWrite = 1;
-  ReadRegister1 = 5'd2;
-  ReadRegister2 = 5'd2;
+  ReadRegister1 = 5'd1;
+  ReadRegister2 = 5'd1;
   #5 Clk=1; #5 Clk=0;
 
   if((ReadData1 != 15) || (ReadData2 != 15)) begin
@@ -138,6 +139,264 @@ output reg		Clk
     $display("Test Case 2 Failed");
   end
 
+//Test Case 3: Check Register Zero
+//Write to Register Zero with a value, and check it is zero and if it is a register 
+WriteRegister =  5'd0;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd0;
+ReadRegister2 = 5'd0;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 32'b0)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+
+//Test Case 4: Check Enable
+// Write '15' to register 2, verify with Read Ports 1 and 2 on 2 different registers that there have been no changes
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 0;
+ReadRegister1 = 5'd2;
+ReadRegister2 = 5'd20;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+
+//Test Case 5: Check Decoder
+// Write '15' to register 2, verify that register 2 is correct, and check that the other registers haven't been written to (exaustively)
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd1;
+ReadRegister2 = 5'd1;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != WriteData) || (ReadData2 != WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd2;
+ReadRegister2 = 5'd3;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd4;
+ReadRegister2 = 5'd5;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd6;
+ReadRegister2 = 5'd7;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd8;
+ReadRegister2 = 5'd9;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+  
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd10;
+ReadRegister2 = 5'd11;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd12;
+ReadRegister2 = 5'd13;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd10;
+ReadRegister2 = 5'd11;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd12;
+ReadRegister2 = 5'd13;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd14;
+ReadRegister2 = 5'd15;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd16;
+ReadRegister2 = 5'd17;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd18;
+ReadRegister2 = 5'd19;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd20;
+ReadRegister2 = 5'd21;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd22;
+ReadRegister2 = 5'd23;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd24;
+ReadRegister2 = 5'd25;
+#5 Clk=1; #5 Clk=0;
+
+   if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd26;
+ReadRegister2 = 5'd27;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd27;
+ReadRegister2 = 5'd28;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd29;
+ReadRegister2 = 5'd30;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+WriteRegister = 5'd1;
+WriteData = 32'd15;
+RegWrite = 1;
+ReadRegister1 = 5'd31;
+ReadRegister2 = 5'd31;
+#5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
 
   // All done!  Wait a moment and signal test completion.
   #5
diff --git a/regfile.v b/regfile.v
index b8a3c74..d5af0c9 100644
--- a/regfile.v
+++ b/regfile.v
@@ -6,6 +6,10 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "decoders.v"
+`include "register.v"
+`include "mux.v"
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -18,10 +22,50 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+//create register to assign 
+  wire [31:0] activeregister;
+  decoder1to32 decoder(activeregister, RegWrite, WriteRegister); 
+
+  wire[31:0] q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15,q16, q17, q18, q19, q20, q21, q22, q23, q24, q25, q26, q27, q28, q29, q30, q31;
+
+
+//Assign appropriate data to appropriate register
+  register32zero register0(q0, WriteData, activeregister[0], Clk);
+  register32 register1( q1,  WriteData, activeregister[1], Clk);
+  register32 register2( q2,  WriteData, activeregister[2], Clk);
+  register32 register3( q3,  WriteData, activeregister[3], Clk);
+  register32 register4( q4,  WriteData, activeregister[4], Clk);
+  register32 register5( q5,  WriteData, activeregister[5], Clk);
+  register32 register6( q6,  WriteData, activeregister[6], Clk);
+  register32 register7( q7,  WriteData, activeregister[7], Clk);
+  register32 register8( q8,  WriteData, activeregister[8], Clk);
+  register32 register9( q9,  WriteData, activeregister[9], Clk);
+  register32 register10(q10, WriteData, activeregister[10], Clk);
+  register32 register11(q11, WriteData, activeregister[11], Clk);
+  register32 register12(q12, WriteData, activeregister[12], Clk);
+  register32 register13(q13, WriteData, activeregister[13], Clk);
+  register32 register14(q14, WriteData, activeregister[14], Clk);
+  register32 register15(q15, WriteData, activeregister[15], Clk);
+  register32 register16(q16, WriteData, activeregister[16], Clk);
+  register32 register17(q17, WriteData, activeregister[17], Clk);
+  register32 register18(q18, WriteData, activeregister[18], Clk);
+  register32 register19(q19, WriteData, activeregister[19], Clk);
+  register32 register20(q20, WriteData, activeregister[20], Clk);
+  register32 register21(q21, WriteData, activeregister[21], Clk);
+  register32 register22(q22, WriteData, activeregister[22], Clk);
+  register32 register23(q23, WriteData, activeregister[23], Clk);
+  register32 register24(q24, WriteData, activeregister[24], Clk);
+  register32 register25(q25, WriteData, activeregister[25], Clk);
+  register32 register26(q26, WriteData, activeregister[26], Clk);
+  register32 register27(q27, WriteData, activeregister[27], Clk);
+  register32 register28(q28, WriteData, activeregister[28], Clk);
+  register32 register29(q29, WriteData, activeregister[29], Clk);
+  register32 register30(q30, WriteData, activeregister[30], Clk);
+  register32 register31(q31, WriteData, activeregister[31], Clk);
+
+// Use MUX tp select registers to read
+mux32to1by32 mux1(ReadData1, ReadRegister1, q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15, q16, q17, q18, q19, q20, q21, q22, q23, q24, q25, q26, q27, q28, q29, q30, q31 );
+
+mux32to1by32 mux2(ReadData2, ReadRegister2, q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15, q16, q17, q18, q19, q20, q21, q22, q23, q24, q25, q26, q27, q28, q29, q30, q31);
 
 endmodule
\ No newline at end of file
diff --git a/register.v b/register.v
index dc9b8cb..05e5392 100644
--- a/register.v
+++ b/register.v
@@ -14,4 +14,60 @@ input		clk
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
+
+//32-Bit D Flip FLop w/ enable and positive edge triggered
+module register32
+(
+output 	[31:0] q,
+input	[31:0] d,
+input	wrenable,
+input	clk
+);
+//assign each of q to corresponding d
+
+	register getbit0(q[0], d[0], wrenable, clk);
+	register getbit1(q[1], d[1], wrenable, clk);
+	register getbit2(q[2], d[2], wrenable, clk);
+	register getbit3(q[3], d[3], wrenable, clk);
+	register getbit4(q[4], d[4], wrenable, clk);
+	register getbit5(q[5], d[5], wrenable, clk);
+	register getbit6(q[6], d[6], wrenable, clk);
+	register getbit7(q[7], d[7], wrenable, clk);
+	register getbit8(q[8], d[8], wrenable, clk);
+	register getbit9(q[9], d[9], wrenable, clk);
+	register getbit10(q[10], d[10], wrenable, clk);
+	register getbit11(q[11], d[11], wrenable, clk);
+	register getbit12(q[12], d[12], wrenable, clk);
+	register getbit13(q[13], d[13], wrenable, clk);
+	register getbit14(q[14], d[14], wrenable, clk);
+	register getbit15(q[15], d[15], wrenable, clk);
+	register getbit16(q[16], d[16], wrenable, clk);
+	register getbit17(q[17], d[17], wrenable, clk);
+	register getbit18(q[18], d[18], wrenable, clk);
+	register getbit19(q[19], d[19], wrenable, clk);
+	register getbit20(q[20], d[20], wrenable, clk);
+	register getbit21(q[21], d[21], wrenable, clk);
+	register getbit22(q[22], d[22], wrenable, clk);
+	register getbit23(q[23], d[23], wrenable, clk);
+	register getbit24(q[24], d[24], wrenable, clk);
+	register getbit25(q[25], d[25], wrenable, clk);
+	register getbit26(q[26], d[26], wrenable, clk);
+	register getbit27(q[27], d[27], wrenable, clk);
+	register getbit28(q[28], d[28], wrenable, clk);
+	register getbit29(q[29], d[29], wrenable, clk);
+	register getbit30(q[30], d[30], wrenable, clk);
+	register getbit31(q[31], d[31], wrenable, clk);
+
+endmodule
+
+module register32zero
+(
+output 	[31:0] q,
+input	[31:0] d,
+input	wrenable,
+input	clk
+);
+//assign all of q to 0
+	assign q = 32'b0;
+endmodule