diff --git a/Deliverable1.jpg b/Deliverable1.jpg
new file mode 100644
index 0000000..fc2c689
Binary files /dev/null and b/Deliverable1.jpg differ
diff --git a/Deliverable6.txt b/Deliverable6.txt
new file mode 100644
index 0000000..f5d418c
--- /dev/null
+++ b/Deliverable6.txt
@@ -0,0 +1 @@
+This module is a decoder.  The address does a bitshift on the enable signal moving it from the least significant bit to the most significant bit.  The output is those either all 0s or the value at which the address inputs is 1.  Thus behaviorally it is a decoder.
diff --git a/decoders.v b/decoders.v
index dd467c2..d6b8cdf 100644
--- a/decoders.v
+++ b/decoders.v
@@ -8,7 +8,6 @@ input		enable,
 input[4:0]	address
 );
 
-    assign out = enable<<address; 
+    assign out = enable<<address;
 
 endmodule
-
diff --git a/mux32to1by1.v b/mux32to1by1.v
new file mode 100644
index 0000000..5b77ac2
--- /dev/null
+++ b/mux32to1by1.v
@@ -0,0 +1,8 @@
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+  assign out = inputs[address];
+endmodule
diff --git a/mux32to1by32.v b/mux32to1by32.v
new file mode 100644
index 0000000..4c011fb
--- /dev/null
+++ b/mux32to1by32.v
@@ -0,0 +1,72 @@
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0,
+input1,
+input2,
+input3,
+input4,
+input5,
+input6,
+input7,
+input8,
+input9,
+input10,
+input11,
+input12,
+input13,
+input14,
+input15,
+input16,
+input17,
+input18,
+input19,
+input20,
+input21,
+input22,
+input23,
+input24,
+input25,
+input26,
+input27,
+input28,
+input29,
+input30,
+input31
+);
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = input0;		// Connect the sources of the array
+  assign mux[1] = input1;
+  assign mux[2] = input2;
+  assign mux[3] = input3;
+  assign mux[4] = input4;
+  assign mux[5] = input5;
+  assign mux[6] = input6;
+  assign mux[7] = input7;
+  assign mux[8] = input8;
+  assign mux[9] = input9;
+  assign mux[10] = input10;
+  assign mux[11] = input11;
+  assign mux[12] = input12;
+  assign mux[13] = input13;
+  assign mux[14] = input14;
+  assign mux[15] = input15;
+  assign mux[16] = input16;
+  assign mux[17] = input17;
+  assign mux[18] = input18;
+  assign mux[19] = input19;
+  assign mux[20] = input20;
+  assign mux[21] = input21;
+  assign mux[22] = input22;
+  assign mux[23] = input23;
+  assign mux[24] = input24;
+  assign mux[25] = input25;
+  assign mux[26] = input26;
+  assign mux[27] = input27;
+  assign mux[28] = input28;
+  assign mux[29] = input29;
+  assign mux[30] = input30;
+  assign mux[31] = input31;
+  assign out = mux[address];	// Connect the output of the array
+endmodule
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..189896f 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -1,7 +1,8 @@
 //------------------------------------------------------------------------------
-// Test harness validates hw4testbench by connecting it to various functional 
+// Test harness validates hw4testbench by connecting it to various functional
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
+`include "regfile.v"
 
 module hw4testbenchharness();
 
@@ -34,15 +35,15 @@ module hw4testbenchharness();
   hw4testbench tester
   (
     .begintest(begintest),
-    .endtest(endtest), 
+    .endtest(endtest),
     .dutpassed(dutpassed),
     .ReadData1(ReadData1),
     .ReadData2(ReadData2),
-    .WriteData(WriteData), 
-    .ReadRegister1(ReadRegister1), 
+    .WriteData(WriteData),
+    .ReadRegister1(ReadRegister1),
     .ReadRegister2(ReadRegister2),
     .WriteRegister(WriteRegister),
-    .RegWrite(RegWrite), 
+    .RegWrite(RegWrite),
     .Clk(Clk)
   );
 
@@ -63,7 +64,7 @@ endmodule
 
 
 //------------------------------------------------------------------------------
-// Your HW4 test bench
+//   Your HW4 test bench
 //   Generates signals to drive register file and passes them back up one
 //   layer to the test harness. This lets us plug in various working and
 //   broken register files to test.
@@ -72,7 +73,6 @@ endmodule
 //   Once your test is conclusive, set 'dutpassed' appropriately and then
 //   raise 'endtest'.
 //------------------------------------------------------------------------------
-
 module hw4testbench
 (
 // Test bench driver signal connections
@@ -90,8 +90,8 @@ output reg[4:0]		WriteRegister,
 output reg		RegWrite,
 output reg		Clk
 );
-
-  // Initialize register driver signals
+  wire unset;
+// Initialize register driver signals
   initial begin
     WriteData=32'd0;
     ReadRegister1=5'd0;
@@ -107,42 +107,159 @@ output reg		Clk
     dutpassed = 1;
     #10
 
-  // Test Case 1: 
-  //   Write '42' to register 2, verify with Read Ports 1 and 2
-  //   (Passes because example register file is hardwired to return 42)
-  WriteRegister = 5'd2;
-  WriteData = 32'd42;
-  RegWrite = 1;
-  ReadRegister1 = 5'd2;
-  ReadRegister2 = 5'd2;
-  #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
-
-  // Verify expectations and report test result
-  if((ReadData1 != 42) || (ReadData2 != 42)) begin
-    dutpassed = 0;	// Set to 'false' on failure
-    $display("Test Case 1 Failed");
-  end
+    // Test Case 1:
+    //   Write '42' to register 2, verify with Read Ports 1 and 2
+    //   (Passes because example register file is hardwired to return 42)
+    WriteRegister = 5'd2;
+    WriteData = 32'd42;
+    RegWrite = 1;
+    ReadRegister1 = 5'd2;
+    ReadRegister2 = 5'd2;
+    #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
-  // Test Case 2: 
-  //   Write '15' to register 2, verify with Read Ports 1 and 2
-  //   (Fails with example register file, but should pass with yours)
-  WriteRegister = 5'd2;
-  WriteData = 32'd15;
-  RegWrite = 1;
-  ReadRegister1 = 5'd2;
-  ReadRegister2 = 5'd2;
-  #5 Clk=1; #5 Clk=0;
-
-  if((ReadData1 != 15) || (ReadData2 != 15)) begin
-    dutpassed = 0;
-    $display("Test Case 2 Failed");
-  end
+    // Verify expectations and report test result
+    //$display("%b | %b | %b", ReadData1, ReadData2, WriteData);
+    if((ReadData1 != 42) || (ReadData2 != 42) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;	// Set to 'false' on failure
+      $display("Test Case 1 Failed");
+    end
+
+    // Test Case 2:
+    //   Write '15' to register 2, verify with Read Ports 1 and 2
+    //   (Fails with example register file, but should pass with yours)
+    WriteRegister = 5'd2;
+    WriteData = 32'd15;
+    RegWrite = 1;
+    ReadRegister1 = 5'd2;
+    ReadRegister2 = 5'd2;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 15) || (ReadData2 != 15) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 2 Failed");
+    end
+
+    // Test Case 3:
+    //   Write '34' to register 4,  Then writes '68' to the same register with regwrite as false.
+    //   Check that 34 is the answer that was left.
+    //   (Fails with example register file, but should pass with yours)
+    WriteRegister = 5'd4;
+    WriteData = 32'd34;
+    RegWrite = 1;
+    ReadRegister1 = 5'd4;
+    ReadRegister2 = 5'd4;
+    #5 Clk=1; #5 Clk=0;
+    WriteRegister = 5'd4;
+    WriteData = 32'd68;
+    RegWrite = 0;
+    ReadRegister1 = 5'd4;
+    ReadRegister2 = 5'd4;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 34) || (ReadData2 != 34) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 3 Failed");
+    end
+
+    // Test Case 4:
+    //   Write '24' to register 10, then write '12' to register 11, then read register 10 with ReadData1 to make sure it was set correctly, and read register 11 with Readdata2.
+    //   Check that register 10 didn't change when register 11 was written.
+    //   (Fails with example register file, but should pass with yours)
+    WriteRegister = 5'd10;
+    WriteData = 32'd24;
+    RegWrite = 1;
+    ReadRegister1 = 5'd10;
+    ReadRegister2 = 5'd10;
+    #5 Clk=1; #5 Clk=0;
+    WriteRegister = 5'd11;
+    WriteData = 32'd12;
+    RegWrite = 1;
+    ReadRegister1 = 5'd10;
+    ReadRegister2 = 5'd11;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 24) || (ReadData2 != 12) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 4 Failed");
+    end
 
+    // Test Case 5:
+    //   Write '1989' to register 0, and read register 0
+    //   Make certain that register 0 is in fact 0
+    //   (Fails with example register file, but should pass with yours)
+    WriteRegister = 5'd0;
+    WriteData = 32'd1989;
+    RegWrite = 1;
+    ReadRegister1 = 5'd0;
+    ReadRegister2 = 5'd0;
+    #5 Clk=1; #5 Clk=0;
+    if((ReadData1 != 0) || (ReadData2 != 0) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 5 Failed");
+    end
 
-  // All done!  Wait a moment and signal test completion.
-  #5
-  endtest = 1;
+    //   Test Case 5:
+    //   Write '7' to reg 7, '8' to reg 8, and '9' to reg 9, then read each one with each read port.
+    //   Check that they all correctly read each register
+    //   (Fails with example register file, but should pass with yours)
 
-end
+    //write reg7 to 7
+    WriteRegister = 5'd7;
+    WriteData = 32'd7;
+    RegWrite = 1;
+    #5 Clk=1; #5 Clk=0;
 
-endmodule
\ No newline at end of file
+    //write reg8 to 8
+    WriteRegister = 5'd8;
+    WriteData = 32'd8;
+    RegWrite = 1;
+    #5 Clk=1; #5 Clk=0;
+
+    //write reg9 to 9
+    WriteRegister = 5'd9;
+    WriteData = 32'd9;
+    RegWrite = 1;
+    #5 Clk=1; #5 Clk=0;
+
+    //write nothing and turn off write enabled
+    WriteRegister = 5'd0;
+    WriteData = 32'd0;
+    RegWrite = 0;
+
+    // read and check answer from reg 7
+    ReadRegister1 = 5'd7;
+    ReadRegister2 = 5'd7;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 7) || (ReadData2 != 7) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 6.1 Failed");
+    end
+
+    // read and check answer from reg 8
+    ReadRegister1 = 5'd8;
+    ReadRegister2 = 5'd8;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 8) || (ReadData2 != 8) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 6.2 Failed");
+    end
+
+    // read and check answer from reg 9
+    ReadRegister1 = 5'd9;
+    ReadRegister2 = 5'd9;
+    #5 Clk=1; #5 Clk=0;
+
+    if((ReadData1 != 9) || (ReadData2 != 9) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+      dutpassed = 0;
+      $display("Test Case 6.3 Failed");
+    end
+
+    // All done!  Wait a moment and signal test completion.
+    #5
+    endtest = 1;
+
+  end
+
+endmodule
diff --git a/regfile.v b/regfile.v
index b8a3c74..cc91c5f 100644
--- a/regfile.v
+++ b/regfile.v
@@ -5,6 +5,10 @@
 //   2 asynchronous read ports
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
+`include "register32.v"
+`include "register32zero.v"
+`include "mux32to1by32.v"
+`include "decoders.v"
 
 module regfile
 (
@@ -17,11 +21,136 @@ input[4:0]	WriteRegister,	// Address of register to write
 input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
-
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
-
-endmodule
\ No newline at end of file
+  wire[31:0] wrenable;
+  wire[31:0] input0;
+  wire[31:0] input1;
+  wire[31:0] input2;
+  wire[31:0] input3;
+  wire[31:0] input4;
+  wire[31:0] input5;
+  wire[31:0] input6;
+  wire[31:0] input7;
+  wire[31:0] input8;
+  wire[31:0] input9;
+  wire[31:0] input10;
+  wire[31:0] input11;
+  wire[31:0] input12;
+  wire[31:0] input13;
+  wire[31:0] input14;
+  wire[31:0] input15;
+  wire[31:0] input16;
+  wire[31:0] input17;
+  wire[31:0] input18;
+  wire[31:0] input19;
+  wire[31:0] input20;
+  wire[31:0] input21;
+  wire[31:0] input22;
+  wire[31:0] input23;
+  wire[31:0] input24;
+  wire[31:0] input25;
+  wire[31:0] input26;
+  wire[31:0] input27;
+  wire[31:0] input28;
+  wire[31:0] input29;
+  wire[31:0] input30;
+  wire[31:0] input31;
+  decoder1to32 decoder(wrenable, RegWrite, WriteRegister);
+  register32zero reg0(input0, Clk);
+  register32 reg1(input1, WriteData, wrenable[1], Clk);
+  register32 reg2(input2, WriteData, wrenable[2], Clk);
+  register32 reg3(input3, WriteData, wrenable[3], Clk);
+  register32 reg4(input4, WriteData, wrenable[4], Clk);
+  register32 reg5(input5, WriteData, wrenable[5], Clk);
+  register32 reg6(input6, WriteData, wrenable[6], Clk);
+  register32 reg7(input7, WriteData, wrenable[7], Clk);
+  register32 reg8(input8, WriteData, wrenable[8], Clk);
+  register32 reg9(input9, WriteData, wrenable[9], Clk);
+  register32 reg10(input10, WriteData, wrenable[10], Clk);
+  register32 reg11(input11, WriteData, wrenable[11], Clk);
+  register32 reg12(input12, WriteData, wrenable[12], Clk);
+  register32 reg13(input13, WriteData, wrenable[13], Clk);
+  register32 reg14(input14, WriteData, wrenable[14], Clk);
+  register32 reg15(input15, WriteData, wrenable[15], Clk);
+  register32 reg16(input16, WriteData, wrenable[16], Clk);
+  register32 reg17(input17, WriteData, wrenable[17], Clk);
+  register32 reg18(input18, WriteData, wrenable[18], Clk);
+  register32 reg19(input19, WriteData, wrenable[19], Clk);
+  register32 reg20(input20, WriteData, wrenable[20], Clk);
+  register32 reg21(input21, WriteData, wrenable[21], Clk);
+  register32 reg22(input22, WriteData, wrenable[22], Clk);
+  register32 reg23(input23, WriteData, wrenable[23], Clk);
+  register32 reg24(input24, WriteData, wrenable[24], Clk);
+  register32 reg25(input25, WriteData, wrenable[25], Clk);
+  register32 reg26(input26, WriteData, wrenable[26], Clk);
+  register32 reg27(input27, WriteData, wrenable[27], Clk);
+  register32 reg28(input28, WriteData, wrenable[28], Clk);
+  register32 reg29(input29, WriteData, wrenable[29], Clk);
+  register32 reg30(input30, WriteData, wrenable[30], Clk);
+  register32 reg31(input31, WriteData, wrenable[31], Clk);
+  mux32to1by32 data1(ReadData1, ReadRegister1, input0,
+    input1,
+    input2,
+    input3,
+    input4,
+    input5,
+    input6,
+    input7,
+    input8,
+    input9,
+    input10,
+    input11,
+    input12,
+    input13,
+    input14,
+    input15,
+    input16,
+    input17,
+    input18,
+    input19,
+    input20,
+    input21,
+    input22,
+    input23,
+    input24,
+    input25,
+    input26,
+    input27,
+    input28,
+    input29,
+    input30,
+    input31
+    );
+  mux32to1by32 data2(ReadData2, ReadRegister2, input0,
+    input1,
+    input2,
+    input3,
+    input4,
+    input5,
+    input6,
+    input7,
+    input8,
+    input9,
+    input10,
+    input11,
+    input12,
+    input13,
+    input14,
+    input15,
+    input16,
+    input17,
+    input18,
+    input19,
+    input20,
+    input21,
+    input22,
+    input23,
+    input24,
+    input25,
+    input26,
+    input27,
+    input28,
+    input29,
+    input30,
+    input31
+    );
+endmodule
diff --git a/register32.v b/register32.v
new file mode 100644
index 0000000..2dc39ab
--- /dev/null
+++ b/register32.v
@@ -0,0 +1,13 @@
+module register32
+(
+output reg[31:0]	q,
+input[31:0]		d,
+input		wrenable,
+input		clk
+);
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q = d;
+        end
+    end
+endmodule
diff --git a/register32zero.v b/register32zero.v
new file mode 100644
index 0000000..6f413b1
--- /dev/null
+++ b/register32zero.v
@@ -0,0 +1,9 @@
+module register32zero
+(
+output reg[31:0]	q,
+input		clk
+);
+    always @(posedge clk) begin
+        q = 32'b0;
+    end
+endmodule