diff --git a/WRITEUP.md b/WRITEUP.md new file mode 100644 index 0000000..3b25c51 --- /dev/null +++ b/WRITEUP.md @@ -0,0 +1,27 @@ +# Homework 4 +### Alexander Hoppe + +## Deliverable 1 + +The first implementation uses a multiplexer to control whether or not the device is taking new inputs or just using its previous one. + + + +The second implementation uses an AND gate on the CLK line, which is less robust to glitches in the WREN signal. If WREN glitches high during the high period of the CLK signal, the flipflop will pass through the state of the D pin, which is not the intended behavior. + + + +## Deliverable 6 + +```verilog +module decoder1to32 +( +output[31:0] out, +input enable, +input[4:0] address +); + assign out = enable<, C4; +v0x9d7d30_0 .net8 "ReadData1", 31 0, RS_0x7f6b24eb7048; 2 drivers +v0x9d7e40_0 .net "ReadData2", 31 0, C4; 0 drivers +v0x9d7ec0_0 .net "ReadRegister1", 4 0, v0x9c86b0_0; 1 drivers +v0x9d7f40_0 .net "ReadRegister2", 4 0, v0x9c8760_0; 1 drivers +v0x9d7fc0_0 .net "RegWrite", 0 0, v0x9c8800_0; 1 drivers +v0x9d8040_0 .net "WriteData", 31 0, v0x9c88e0_0; 1 drivers +v0x9d80c0_0 .net "WriteRegister", 4 0, v0x9c8980_0; 1 drivers +v0x9d8140_0 .var "begintest", 0 0; +v0x9d81c0_0 .net "dutpassed", 0 0, v0x9c8b10_0; 1 drivers +v0x9d8240_0 .net "endtest", 0 0, v0x9c8c10_0; 1 drivers +E_0x98e7b0 .event posedge, v0x9c8c10_0; +S_0x9c8dc0 .scope module, "DUT" "regfile" 2 23, 3 14, S_0x98f260; + .timescale 0 0; +v0x9d76a0_0 .alias "Clk", 0 0, v0x9d7cb0_0; +v0x9d7720_0 .alias "ReadData1", 31 0, v0x9d7d30_0; +v0x9d77a0_0 .alias "ReadData2", 31 0, v0x9d7e40_0; +v0x9d7820_0 .alias "ReadRegister1", 4 0, v0x9d7ec0_0; +v0x9d78a0_0 .alias "ReadRegister2", 4 0, v0x9d7f40_0; +v0x9d7920_0 .alias "RegWrite", 0 0, v0x9d7fc0_0; +v0x9d79a0_0 .alias "WriteData", 31 0, v0x9d8040_0; +v0x9d7a20_0 .alias "WriteRegister", 4 0, v0x9d80c0_0; +v0x9d7aa0_0 .net "enable", 31 0, L_0x9d9ff0; 1 drivers +v0x9d7b20 .array "regout", 0 31; +v0x9d7b20_0 .net v0x9d7b20 0, 31 0, v0x9cde30_0; 1 drivers +v0x9d7b20_1 .net v0x9d7b20 1, 31 0, v0x9d2ad0_0; 1 drivers +v0x9d7b20_2 .net v0x9d7b20 2, 31 0, v0x9d25e0_0; 1 drivers +v0x9d7b20_3 .net v0x9d7b20 3, 31 0, v0x9d20f0_0; 1 drivers +v0x9d7b20_4 .net v0x9d7b20 4, 31 0, v0x9d1c00_0; 1 drivers +v0x9d7b20_5 .net v0x9d7b20 5, 31 0, v0x9d1710_0; 1 drivers +v0x9d7b20_6 .net v0x9d7b20 6, 31 0, v0x9d1220_0; 1 drivers +v0x9d7b20_7 .net v0x9d7b20 7, 31 0, v0x9d0d30_0; 1 drivers +v0x9d7b20_8 .net v0x9d7b20 8, 31 0, v0x9d0840_0; 1 drivers +v0x9d7b20_9 .net v0x9d7b20 9, 31 0, v0x9d0350_0; 1 drivers +v0x9d7b20_10 .net v0x9d7b20 10, 31 0, v0x9cfe60_0; 1 drivers +v0x9d7b20_11 .net v0x9d7b20 11, 31 0, v0x9cf970_0; 1 drivers +v0x9d7b20_12 .net v0x9d7b20 12, 31 0, v0x9cf480_0; 1 drivers +v0x9d7b20_13 .net v0x9d7b20 13, 31 0, v0x9cef90_0; 1 drivers +v0x9d7b20_14 .net v0x9d7b20 14, 31 0, v0x9ceaa0_0; 1 drivers +v0x9d7b20_15 .net v0x9d7b20 15, 31 0, v0x9ce5b0_0; 1 drivers +v0x9d7b20_16 .net v0x9d7b20 16, 31 0, v0x9cb610_0; 1 drivers +v0x9d7b20_17 .net v0x9d7b20 17, 31 0, v0x9cd9c0_0; 1 drivers +v0x9d7b20_18 .net v0x9d7b20 18, 31 0, v0x9cd4d0_0; 1 drivers +v0x9d7b20_19 .net v0x9d7b20 19, 31 0, v0x9ccfe0_0; 1 drivers +v0x9d7b20_20 .net v0x9d7b20 20, 31 0, v0x9ccaf0_0; 1 drivers +v0x9d7b20_21 .net v0x9d7b20 21, 31 0, v0x9cc600_0; 1 drivers +v0x9d7b20_22 .net v0x9d7b20 22, 31 0, v0x9cc110_0; 1 drivers +v0x9d7b20_23 .net v0x9d7b20 23, 31 0, v0x9cbc20_0; 1 drivers +v0x9d7b20_24 .net v0x9d7b20 24, 31 0, v0x9ca1c0_0; 1 drivers +v0x9d7b20_25 .net v0x9d7b20 25, 31 0, v0x9cb120_0; 1 drivers +v0x9d7b20_26 .net v0x9d7b20 26, 31 0, v0x9cac30_0; 1 drivers +v0x9d7b20_27 .net v0x9d7b20 27, 31 0, v0x9ca740_0; 1 drivers +v0x9d7b20_28 .net v0x9d7b20 28, 31 0, v0x9ca250_0; 1 drivers +v0x9d7b20_29 .net v0x9d7b20 29, 31 0, v0x9c9c70_0; 1 drivers +v0x9d7b20_30 .net v0x9d7b20 30, 31 0, v0x9c97b0_0; 1 drivers +v0x9d7b20_31 .net v0x9d7b20 31, 31 0, v0x9c92b0_0; 1 drivers +L_0x9d82c0 .part L_0x9d9ff0, 1, 1; +L_0x9d8360 .part L_0x9d9ff0, 2, 1; +L_0x9d8400 .part L_0x9d9ff0, 3, 1; +L_0x9d8530 .part L_0x9d9ff0, 4, 1; +L_0x9d85d0 .part L_0x9d9ff0, 5, 1; +L_0x9d8670 .part L_0x9d9ff0, 6, 1; +L_0x9d8710 .part L_0x9d9ff0, 7, 1; +L_0x9d88c0 .part L_0x9d9ff0, 8, 1; +L_0x9d8960 .part L_0x9d9ff0, 9, 1; +L_0x9d8a00 .part L_0x9d9ff0, 10, 1; +L_0x9d8aa0 .part L_0x9d9ff0, 11, 1; +L_0x9d8b40 .part L_0x9d9ff0, 12, 1; +L_0x9d8be0 .part L_0x9d9ff0, 13, 1; +L_0x9d8c80 .part L_0x9d9ff0, 14, 1; +L_0x9d8d20 .part L_0x9d9ff0, 15, 1; +L_0x9d87b0 .part L_0x9d9ff0, 16, 1; +L_0x9d8fd0 .part L_0x9d9ff0, 17, 1; +L_0x9d9070 .part L_0x9d9ff0, 18, 1; +L_0x9d91b0 .part L_0x9d9ff0, 19, 1; +L_0x9d9250 .part L_0x9d9ff0, 20, 1; +L_0x9d9110 .part L_0x9d9ff0, 21, 1; +L_0x9d93a0 .part L_0x9d9ff0, 22, 1; +L_0x9d92f0 .part L_0x9d9ff0, 23, 1; +L_0x9d9500 .part L_0x9d9ff0, 24, 1; +L_0x9d9440 .part L_0x9d9ff0, 25, 1; +L_0x9d96a0 .part L_0x9d9ff0, 26, 1; +L_0x9d95a0 .part L_0x9d9ff0, 27, 1; +L_0x9d9850 .part L_0x9d9ff0, 28, 1; +L_0x9d9770 .part L_0x9d9ff0, 29, 1; +L_0x9d9a10 .part L_0x9d9ff0, 30, 1; +L_0x9d9920 .part L_0x9d9ff0, 31, 1; +L_0x9da120 .part L_0x9d9ff0, 0, 1; +S_0x9cdf80 .scope module, "en_decoder" "decoder1to32" 3 30, 4 1, S_0x9c8dc0; + .timescale 0 0; +v0x9ce070_0 .net *"_s0", 31 0, L_0x9d8dc0; 1 drivers +v0x9ce130_0 .net *"_s3", 30 0, C4<0000000000000000000000000000000>; 1 drivers +v0x9ce1d0_0 .alias "address", 4 0, v0x9d80c0_0; +v0x9d75a0_0 .alias "enable", 0 0, v0x9d7fc0_0; +v0x9d7620_0 .alias "out", 31 0, v0x9d7aa0_0; +L_0x9d8dc0 .concat [ 1 31 0 0], v0x9c8800_0, C4<0000000000000000000000000000000>; +L_0x9d9ff0 .shift/l 32, L_0x9d8dc0, v0x9c8980_0; +S_0x9d6c90 .scope module, "register0" "register32zero" 3 33, 5 3, S_0x9c8dc0; + .timescale 0 0; +v0x9d66e0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d38f0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cde30_0 .var "q", 31 0; +v0x9cdf00_0 .net "wrenable", 0 0, L_0x9da120; 1 drivers +S_0x9d4630 .scope module, "mux_d1" "mux32to1by32" 3 41, 6 3, S_0x9c8dc0; + .timescale 0 0; +L_0x9d2f80 .functor BUFZ 32, v0x9cde30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9d9b70 .functor BUFZ 32, v0x9d2ad0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da390 .functor BUFZ 32, v0x9d25e0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da4b0 .functor BUFZ 32, v0x9d20f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da600 .functor BUFZ 32, v0x9d1c00_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da720 .functor BUFZ 32, v0x9d1710_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da880 .functor BUFZ 32, v0x9d1220_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9da970 .functor BUFZ 32, v0x9d0d30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9daa90 .functor BUFZ 32, v0x9d0840_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dabb0 .functor BUFZ 32, v0x9d0350_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dad30 .functor BUFZ 32, v0x9cfe60_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dae50 .functor BUFZ 32, v0x9cf970_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dacd0 .functor BUFZ 32, v0x9cf480_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db070 .functor BUFZ 32, v0x9cef90_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db210 .functor BUFZ 32, v0x9ceaa0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db330 .functor BUFZ 32, v0x9ce5b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db4e0 .functor BUFZ 32, v0x9cb610_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db600 .functor BUFZ 32, v0x9cd9c0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db450 .functor BUFZ 32, v0x9cd4d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db850 .functor BUFZ 32, v0x9ccfe0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db720 .functor BUFZ 32, v0x9ccaf0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dbab0 .functor BUFZ 32, v0x9cc600_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9db970 .functor BUFZ 32, v0x9cc110_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dbd20 .functor BUFZ 32, v0x9cbc20_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dbbd0 .functor BUFZ 32, v0x9ca1c0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dbfa0 .functor BUFZ 32, v0x9cb120_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dbe40 .functor BUFZ 32, v0x9cac30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc200 .functor BUFZ 32, v0x9ca740_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9d5a80 .functor BUFZ 32, v0x9ca250_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc3e0 .functor BUFZ 32, v0x9c9c70_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc2f0 .functor BUFZ 32, v0x9c97b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc380 .functor BUFZ 32, v0x9c92b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9d43a0 .functor BUFZ 32, L_0x9dc500, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x9d4990_0 .net *"_s96", 31 0, L_0x9dc500; 1 drivers +v0x9d4a10_0 .alias "address", 4 0, v0x9d7ec0_0; +v0x9d4a90_0 .alias "input0", 31 0, v0x9d7b20_0; +v0x9d4b10_0 .alias "input1", 31 0, v0x9d7b20_1; +v0x9d4b90_0 .alias "input10", 31 0, v0x9d7b20_10; +v0x9d4c60_0 .alias "input11", 31 0, v0x9d7b20_11; +v0x9d4d70_0 .alias "input12", 31 0, v0x9d7b20_12; +v0x9d4e40_0 .alias "input13", 31 0, v0x9d7b20_13; +v0x9d4f60_0 .alias "input14", 31 0, v0x9d7b20_14; +v0x9d5030_0 .alias "input15", 31 0, v0x9d7b20_15; +v0x9d5110_0 .alias "input16", 31 0, v0x9d7b20_16; +v0x9d51e0_0 .alias "input17", 31 0, v0x9d7b20_17; +v0x9d5320_0 .alias "input18", 31 0, v0x9d7b20_18; +v0x9d53f0_0 .alias "input19", 31 0, v0x9d7b20_19; +v0x9d5540_0 .alias "input2", 31 0, v0x9d7b20_2; +v0x9d5610_0 .alias "input20", 31 0, v0x9d7b20_20; +v0x9d5470_0 .alias "input21", 31 0, v0x9d7b20_21; +v0x9d57c0_0 .alias "input22", 31 0, v0x9d7b20_22; +v0x9d58e0_0 .alias "input23", 31 0, v0x9d7b20_23; +v0x9d59b0_0 .alias "input24", 31 0, v0x9d7b20_24; +v0x9d5ae0_0 .alias "input25", 31 0, v0x9d7b20_25; +v0x9d5b60_0 .alias "input26", 31 0, v0x9d7b20_26; +v0x9d5ca0_0 .alias "input27", 31 0, v0x9d7b20_27; +v0x9d5d20_0 .alias "input28", 31 0, v0x9d7b20_28; +v0x9d5e70_0 .alias "input29", 31 0, v0x9d7b20_29; +v0x9d5ef0_0 .alias "input3", 31 0, v0x9d7b20_3; +v0x9d5df0_0 .alias "input30", 31 0, v0x9d7b20_30; +v0x9d60a0_0 .alias "input31", 31 0, v0x9d7b20_31; +v0x9d5fc0_0 .alias "input4", 31 0, v0x9d7b20_4; +v0x9d6260_0 .alias "input5", 31 0, v0x9d7b20_5; +v0x9d6170_0 .alias "input6", 31 0, v0x9d7b20_6; +v0x9d6430_0 .alias "input7", 31 0, v0x9d7b20_7; +v0x9d6330_0 .alias "input8", 31 0, v0x9d7b20_8; +v0x9d6610_0 .alias "input9", 31 0, v0x9d7b20_9; +v0x9d6500 .array "mux", 0 31; +v0x9d6500_0 .net v0x9d6500 0, 31 0, L_0x9d2f80; 1 drivers +v0x9d6500_1 .net v0x9d6500 1, 31 0, L_0x9d9b70; 1 drivers +v0x9d6500_2 .net v0x9d6500 2, 31 0, L_0x9da390; 1 drivers +v0x9d6500_3 .net v0x9d6500 3, 31 0, L_0x9da4b0; 1 drivers +v0x9d6500_4 .net v0x9d6500 4, 31 0, L_0x9da600; 1 drivers +v0x9d6500_5 .net v0x9d6500 5, 31 0, L_0x9da720; 1 drivers +v0x9d6500_6 .net v0x9d6500 6, 31 0, L_0x9da880; 1 drivers +v0x9d6500_7 .net v0x9d6500 7, 31 0, L_0x9da970; 1 drivers +v0x9d6500_8 .net v0x9d6500 8, 31 0, L_0x9daa90; 1 drivers +v0x9d6500_9 .net v0x9d6500 9, 31 0, L_0x9dabb0; 1 drivers +v0x9d6500_10 .net v0x9d6500 10, 31 0, L_0x9dad30; 1 drivers +v0x9d6500_11 .net v0x9d6500 11, 31 0, L_0x9dae50; 1 drivers +v0x9d6500_12 .net v0x9d6500 12, 31 0, L_0x9dacd0; 1 drivers +v0x9d6500_13 .net v0x9d6500 13, 31 0, L_0x9db070; 1 drivers +v0x9d6500_14 .net v0x9d6500 14, 31 0, L_0x9db210; 1 drivers +v0x9d6500_15 .net v0x9d6500 15, 31 0, L_0x9db330; 1 drivers +v0x9d6500_16 .net v0x9d6500 16, 31 0, L_0x9db4e0; 1 drivers +v0x9d6500_17 .net v0x9d6500 17, 31 0, L_0x9db600; 1 drivers +v0x9d6500_18 .net v0x9d6500 18, 31 0, L_0x9db450; 1 drivers +v0x9d6500_19 .net v0x9d6500 19, 31 0, L_0x9db850; 1 drivers +v0x9d6500_20 .net v0x9d6500 20, 31 0, L_0x9db720; 1 drivers +v0x9d6500_21 .net v0x9d6500 21, 31 0, L_0x9dbab0; 1 drivers +v0x9d6500_22 .net v0x9d6500 22, 31 0, L_0x9db970; 1 drivers +v0x9d6500_23 .net v0x9d6500 23, 31 0, L_0x9dbd20; 1 drivers +v0x9d6500_24 .net v0x9d6500 24, 31 0, L_0x9dbbd0; 1 drivers +v0x9d6500_25 .net v0x9d6500 25, 31 0, L_0x9dbfa0; 1 drivers +v0x9d6500_26 .net v0x9d6500 26, 31 0, L_0x9dbe40; 1 drivers +v0x9d6500_27 .net v0x9d6500 27, 31 0, L_0x9dc200; 1 drivers +v0x9d6500_28 .net v0x9d6500 28, 31 0, L_0x9d5a80; 1 drivers +v0x9d6500_29 .net v0x9d6500 29, 31 0, L_0x9dc3e0; 1 drivers +v0x9d6500_30 .net v0x9d6500 30, 31 0, L_0x9dc2f0; 1 drivers +v0x9d6500_31 .net v0x9d6500 31, 31 0, L_0x9dc380; 1 drivers +v0x9d6ae0_0 .alias "out", 31 0, v0x9d7d30_0; +L_0x9dc500 .array/port v0x9d6500, v0x9c86b0_0; +S_0x9d2c20 .scope module, "mux_d2" "mux32to1by32" 3 74, 6 3, S_0x9c8dc0; + .timescale 0 0; +L_0x9dc8f0 .functor BUFZ 32, v0x9cde30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc950 .functor BUFZ 32, v0x9d2ad0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dc9b0 .functor BUFZ 32, v0x9d25e0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dca40 .functor BUFZ 32, v0x9d20f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcb00 .functor BUFZ 32, v0x9d1c00_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcb90 .functor BUFZ 32, v0x9d1710_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcc20 .functor BUFZ 32, v0x9d1220_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcc80 .functor BUFZ 32, v0x9d0d30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcd10 .functor BUFZ 32, v0x9d0840_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcda0 .functor BUFZ 32, v0x9d0350_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dce90 .functor BUFZ 32, v0x9cfe60_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcf20 .functor BUFZ 32, v0x9cf970_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dce30 .functor BUFZ 32, v0x9cf480_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dcfe0 .functor BUFZ 32, v0x9cef90_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd070 .functor BUFZ 32, v0x9ceaa0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd100 .functor BUFZ 32, v0x9ce5b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd220 .functor BUFZ 32, v0x9cb610_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd2b0 .functor BUFZ 32, v0x9cd9c0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd190 .functor BUFZ 32, v0x9cd4d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd3e0 .functor BUFZ 32, v0x9ccfe0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd340 .functor BUFZ 32, v0x9ccaf0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd520 .functor BUFZ 32, v0x9cc600_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd470 .functor BUFZ 32, v0x9cc110_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd670 .functor BUFZ 32, v0x9cbc20_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd5b0 .functor BUFZ 32, v0x9ca1c0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd7d0 .functor BUFZ 32, v0x9cb120_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd700 .functor BUFZ 32, v0x9cac30_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd910 .functor BUFZ 32, v0x9ca740_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd830 .functor BUFZ 32, v0x9ca250_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dda60 .functor BUFZ 32, v0x9c9c70_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dd970 .functor BUFZ 32, v0x9c97b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9dda00 .functor BUFZ 32, v0x9c92b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x9d40d0 .functor BUFZ 32, L_0x9ddac0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x9d2d10_0 .net *"_s96", 31 0, L_0x9ddac0; 1 drivers +v0x9d2dd0_0 .alias "address", 4 0, v0x9d7f40_0; +v0x9d2e80_0 .alias "input0", 31 0, v0x9d7b20_0; +v0x9d2f00_0 .alias "input1", 31 0, v0x9d7b20_1; +v0x9d2fe0_0 .alias "input10", 31 0, v0x9d7b20_10; +v0x9d3090_0 .alias "input11", 31 0, v0x9d7b20_11; +v0x9d3150_0 .alias "input12", 31 0, v0x9d7b20_12; +v0x9d3200_0 .alias "input13", 31 0, v0x9d7b20_13; +v0x9d32b0_0 .alias "input14", 31 0, v0x9d7b20_14; +v0x9d3360_0 .alias "input15", 31 0, v0x9d7b20_15; +v0x9d3410_0 .alias "input16", 31 0, v0x9d7b20_16; +v0x9d34c0_0 .alias "input17", 31 0, v0x9d7b20_17; +v0x9d35e0_0 .alias "input18", 31 0, v0x9d7b20_18; +v0x9d3690_0 .alias "input19", 31 0, v0x9d7b20_19; +v0x9d37c0_0 .alias "input2", 31 0, v0x9d7b20_2; +v0x9d3870_0 .alias "input20", 31 0, v0x9d7b20_20; +v0x9d3710_0 .alias "input21", 31 0, v0x9d7b20_21; +v0x9d39e0_0 .alias "input22", 31 0, v0x9d7b20_22; +v0x9d3b00_0 .alias "input23", 31 0, v0x9d7b20_23; +v0x9d3b80_0 .alias "input24", 31 0, v0x9d7b20_24; +v0x9d3a60_0 .alias "input25", 31 0, v0x9d7b20_25; +v0x9d3ce0_0 .alias "input26", 31 0, v0x9d7b20_26; +v0x9d3c30_0 .alias "input27", 31 0, v0x9d7b20_27; +v0x9d3e50_0 .alias "input28", 31 0, v0x9d7b20_28; +v0x9d3d90_0 .alias "input29", 31 0, v0x9d7b20_29; +v0x9d3fd0_0 .alias "input3", 31 0, v0x9d7b20_3; +v0x9d3ed0_0 .alias "input30", 31 0, v0x9d7b20_30; +v0x9d4130_0 .alias "input31", 31 0, v0x9d7b20_31; +v0x9d4050_0 .alias "input4", 31 0, v0x9d7b20_4; +v0x9d42a0_0 .alias "input5", 31 0, v0x9d7b20_5; +v0x9d41b0_0 .alias "input6", 31 0, v0x9d7b20_6; +v0x9d4420_0 .alias "input7", 31 0, v0x9d7b20_7; +v0x9d4320_0 .alias "input8", 31 0, v0x9d7b20_8; +v0x9d45b0_0 .alias "input9", 31 0, v0x9d7b20_9; +v0x9d44a0 .array "mux", 0 31; +v0x9d44a0_0 .net v0x9d44a0 0, 31 0, L_0x9dc8f0; 1 drivers +v0x9d44a0_1 .net v0x9d44a0 1, 31 0, L_0x9dc950; 1 drivers +v0x9d44a0_2 .net v0x9d44a0 2, 31 0, L_0x9dc9b0; 1 drivers +v0x9d44a0_3 .net v0x9d44a0 3, 31 0, L_0x9dca40; 1 drivers +v0x9d44a0_4 .net v0x9d44a0 4, 31 0, L_0x9dcb00; 1 drivers +v0x9d44a0_5 .net v0x9d44a0 5, 31 0, L_0x9dcb90; 1 drivers +v0x9d44a0_6 .net v0x9d44a0 6, 31 0, L_0x9dcc20; 1 drivers +v0x9d44a0_7 .net v0x9d44a0 7, 31 0, L_0x9dcc80; 1 drivers +v0x9d44a0_8 .net v0x9d44a0 8, 31 0, L_0x9dcd10; 1 drivers +v0x9d44a0_9 .net v0x9d44a0 9, 31 0, L_0x9dcda0; 1 drivers +v0x9d44a0_10 .net v0x9d44a0 10, 31 0, L_0x9dce90; 1 drivers +v0x9d44a0_11 .net v0x9d44a0 11, 31 0, L_0x9dcf20; 1 drivers +v0x9d44a0_12 .net v0x9d44a0 12, 31 0, L_0x9dce30; 1 drivers +v0x9d44a0_13 .net v0x9d44a0 13, 31 0, L_0x9dcfe0; 1 drivers +v0x9d44a0_14 .net v0x9d44a0 14, 31 0, L_0x9dd070; 1 drivers +v0x9d44a0_15 .net v0x9d44a0 15, 31 0, L_0x9dd100; 1 drivers +v0x9d44a0_16 .net v0x9d44a0 16, 31 0, L_0x9dd220; 1 drivers +v0x9d44a0_17 .net v0x9d44a0 17, 31 0, L_0x9dd2b0; 1 drivers +v0x9d44a0_18 .net v0x9d44a0 18, 31 0, L_0x9dd190; 1 drivers +v0x9d44a0_19 .net v0x9d44a0 19, 31 0, L_0x9dd3e0; 1 drivers +v0x9d44a0_20 .net v0x9d44a0 20, 31 0, L_0x9dd340; 1 drivers +v0x9d44a0_21 .net v0x9d44a0 21, 31 0, L_0x9dd520; 1 drivers +v0x9d44a0_22 .net v0x9d44a0 22, 31 0, L_0x9dd470; 1 drivers +v0x9d44a0_23 .net v0x9d44a0 23, 31 0, L_0x9dd670; 1 drivers +v0x9d44a0_24 .net v0x9d44a0 24, 31 0, L_0x9dd5b0; 1 drivers +v0x9d44a0_25 .net v0x9d44a0 25, 31 0, L_0x9dd7d0; 1 drivers +v0x9d44a0_26 .net v0x9d44a0 26, 31 0, L_0x9dd700; 1 drivers +v0x9d44a0_27 .net v0x9d44a0 27, 31 0, L_0x9dd910; 1 drivers +v0x9d44a0_28 .net v0x9d44a0 28, 31 0, L_0x9dd830; 1 drivers +v0x9d44a0_29 .net v0x9d44a0 29, 31 0, L_0x9dda60; 1 drivers +v0x9d44a0_30 .net v0x9d44a0 30, 31 0, L_0x9dd970; 1 drivers +v0x9d44a0_31 .net v0x9d44a0 31, 31 0, L_0x9dda00; 1 drivers +v0x9d4520_0 .alias "out", 31 0, v0x9d7d30_0; +L_0x9ddac0 .array/port v0x9d44a0, v0x9c8760_0; +S_0x9d2730 .scope generate, "register_generate[1]" "register_generate[1]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d2828 .param/l "i" 3 35, +C4<01>; +S_0x9d28e0 .scope module, "register" "register32" 3 36, 7 3, S_0x9d2730; + .timescale 0 0; +v0x9d29d0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d2a50_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d2ad0_0 .var "q", 31 0; +v0x9d2b70_0 .net "wrenable", 0 0, L_0x9d82c0; 1 drivers +S_0x9d2240 .scope generate, "register_generate[2]" "register_generate[2]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d2338 .param/l "i" 3 35, +C4<010>; +S_0x9d23f0 .scope module, "register" "register32" 3 36, 7 3, S_0x9d2240; + .timescale 0 0; +v0x9d24e0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d2560_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d25e0_0 .var "q", 31 0; +v0x9d2680_0 .net "wrenable", 0 0, L_0x9d8360; 1 drivers +S_0x9d1d50 .scope generate, "register_generate[3]" "register_generate[3]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d1e48 .param/l "i" 3 35, +C4<011>; +S_0x9d1f00 .scope module, "register" "register32" 3 36, 7 3, S_0x9d1d50; + .timescale 0 0; +v0x9d1ff0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d2070_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d20f0_0 .var "q", 31 0; +v0x9d2190_0 .net "wrenable", 0 0, L_0x9d8400; 1 drivers +S_0x9d1860 .scope generate, "register_generate[4]" "register_generate[4]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d1958 .param/l "i" 3 35, +C4<0100>; +S_0x9d1a10 .scope module, "register" "register32" 3 36, 7 3, S_0x9d1860; + .timescale 0 0; +v0x9d1b00_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d1b80_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d1c00_0 .var "q", 31 0; +v0x9d1ca0_0 .net "wrenable", 0 0, L_0x9d8530; 1 drivers +S_0x9d1370 .scope generate, "register_generate[5]" "register_generate[5]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d1468 .param/l "i" 3 35, +C4<0101>; +S_0x9d1520 .scope module, "register" "register32" 3 36, 7 3, S_0x9d1370; + .timescale 0 0; +v0x9d1610_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d1690_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d1710_0 .var "q", 31 0; +v0x9d17b0_0 .net "wrenable", 0 0, L_0x9d85d0; 1 drivers +S_0x9d0e80 .scope generate, "register_generate[6]" "register_generate[6]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d0f78 .param/l "i" 3 35, +C4<0110>; +S_0x9d1030 .scope module, "register" "register32" 3 36, 7 3, S_0x9d0e80; + .timescale 0 0; +v0x9d1120_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d11a0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d1220_0 .var "q", 31 0; +v0x9d12c0_0 .net "wrenable", 0 0, L_0x9d8670; 1 drivers +S_0x9d0990 .scope generate, "register_generate[7]" "register_generate[7]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d0a88 .param/l "i" 3 35, +C4<0111>; +S_0x9d0b40 .scope module, "register" "register32" 3 36, 7 3, S_0x9d0990; + .timescale 0 0; +v0x9d0c30_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d0cb0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d0d30_0 .var "q", 31 0; +v0x9d0dd0_0 .net "wrenable", 0 0, L_0x9d8710; 1 drivers +S_0x9d04a0 .scope generate, "register_generate[8]" "register_generate[8]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d0598 .param/l "i" 3 35, +C4<01000>; +S_0x9d0650 .scope module, "register" "register32" 3 36, 7 3, S_0x9d04a0; + .timescale 0 0; +v0x9d0740_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d07c0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d0840_0 .var "q", 31 0; +v0x9d08e0_0 .net "wrenable", 0 0, L_0x9d88c0; 1 drivers +S_0x9cffb0 .scope generate, "register_generate[9]" "register_generate[9]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9d00a8 .param/l "i" 3 35, +C4<01001>; +S_0x9d0160 .scope module, "register" "register32" 3 36, 7 3, S_0x9cffb0; + .timescale 0 0; +v0x9d0250_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9d02d0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9d0350_0 .var "q", 31 0; +v0x9d03f0_0 .net "wrenable", 0 0, L_0x9d8960; 1 drivers +S_0x9cfac0 .scope generate, "register_generate[10]" "register_generate[10]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cfbb8 .param/l "i" 3 35, +C4<01010>; +S_0x9cfc70 .scope module, "register" "register32" 3 36, 7 3, S_0x9cfac0; + .timescale 0 0; +v0x9cfd60_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cfde0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cfe60_0 .var "q", 31 0; +v0x9cff00_0 .net "wrenable", 0 0, L_0x9d8a00; 1 drivers +S_0x9cf5d0 .scope generate, "register_generate[11]" "register_generate[11]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cf6c8 .param/l "i" 3 35, +C4<01011>; +S_0x9cf780 .scope module, "register" "register32" 3 36, 7 3, S_0x9cf5d0; + .timescale 0 0; +v0x9cf870_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cf8f0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cf970_0 .var "q", 31 0; +v0x9cfa10_0 .net "wrenable", 0 0, L_0x9d8aa0; 1 drivers +S_0x9cf0e0 .scope generate, "register_generate[12]" "register_generate[12]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cf1d8 .param/l "i" 3 35, +C4<01100>; +S_0x9cf290 .scope module, "register" "register32" 3 36, 7 3, S_0x9cf0e0; + .timescale 0 0; +v0x9cf380_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cf400_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cf480_0 .var "q", 31 0; +v0x9cf520_0 .net "wrenable", 0 0, L_0x9d8b40; 1 drivers +S_0x9cebf0 .scope generate, "register_generate[13]" "register_generate[13]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cece8 .param/l "i" 3 35, +C4<01101>; +S_0x9ceda0 .scope module, "register" "register32" 3 36, 7 3, S_0x9cebf0; + .timescale 0 0; +v0x9cee90_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cef10_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cef90_0 .var "q", 31 0; +v0x9cf030_0 .net "wrenable", 0 0, L_0x9d8be0; 1 drivers +S_0x9ce700 .scope generate, "register_generate[14]" "register_generate[14]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9ce7f8 .param/l "i" 3 35, +C4<01110>; +S_0x9ce8b0 .scope module, "register" "register32" 3 36, 7 3, S_0x9ce700; + .timescale 0 0; +v0x9ce9a0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cea20_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ceaa0_0 .var "q", 31 0; +v0x9ceb40_0 .net "wrenable", 0 0, L_0x9d8c80; 1 drivers +S_0x9ce250 .scope generate, "register_generate[15]" "register_generate[15]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cb768 .param/l "i" 3 35, +C4<01111>; +S_0x9ce3c0 .scope module, "register" "register32" 3 36, 7 3, S_0x9ce250; + .timescale 0 0; +v0x9ce4b0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9ce530_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ce5b0_0 .var "q", 31 0; +v0x9ce650_0 .net "wrenable", 0 0, L_0x9d8d20; 1 drivers +S_0x9cdb10 .scope generate, "register_generate[16]" "register_generate[16]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cdc08 .param/l "i" 3 35, +C4<010000>; +S_0x9cdcc0 .scope module, "register" "register32" 3 36, 7 3, S_0x9cdb10; + .timescale 0 0; +v0x9cddb0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cb590_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cb610_0 .var "q", 31 0; +v0x9cb6b0_0 .net "wrenable", 0 0, L_0x9d87b0; 1 drivers +S_0x9cd620 .scope generate, "register_generate[17]" "register_generate[17]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cd718 .param/l "i" 3 35, +C4<010001>; +S_0x9cd7d0 .scope module, "register" "register32" 3 36, 7 3, S_0x9cd620; + .timescale 0 0; +v0x9cd8c0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cd940_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cd9c0_0 .var "q", 31 0; +v0x9cda60_0 .net "wrenable", 0 0, L_0x9d8fd0; 1 drivers +S_0x9cd130 .scope generate, "register_generate[18]" "register_generate[18]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cd228 .param/l "i" 3 35, +C4<010010>; +S_0x9cd2e0 .scope module, "register" "register32" 3 36, 7 3, S_0x9cd130; + .timescale 0 0; +v0x9cd3d0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cd450_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cd4d0_0 .var "q", 31 0; +v0x9cd570_0 .net "wrenable", 0 0, L_0x9d9070; 1 drivers +S_0x9ccc40 .scope generate, "register_generate[19]" "register_generate[19]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9ccd38 .param/l "i" 3 35, +C4<010011>; +S_0x9ccdf0 .scope module, "register" "register32" 3 36, 7 3, S_0x9ccc40; + .timescale 0 0; +v0x9ccee0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9ccf60_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ccfe0_0 .var "q", 31 0; +v0x9cd080_0 .net "wrenable", 0 0, L_0x9d91b0; 1 drivers +S_0x9cc750 .scope generate, "register_generate[20]" "register_generate[20]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cc848 .param/l "i" 3 35, +C4<010100>; +S_0x9cc900 .scope module, "register" "register32" 3 36, 7 3, S_0x9cc750; + .timescale 0 0; +v0x9cc9f0_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cca70_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ccaf0_0 .var "q", 31 0; +v0x9ccb90_0 .net "wrenable", 0 0, L_0x9d9250; 1 drivers +S_0x9cc260 .scope generate, "register_generate[21]" "register_generate[21]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cc358 .param/l "i" 3 35, +C4<010101>; +S_0x9cc410 .scope module, "register" "register32" 3 36, 7 3, S_0x9cc260; + .timescale 0 0; +v0x9cc500_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cc580_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cc600_0 .var "q", 31 0; +v0x9cc6a0_0 .net "wrenable", 0 0, L_0x9d9110; 1 drivers +S_0x9cbd70 .scope generate, "register_generate[22]" "register_generate[22]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cbe68 .param/l "i" 3 35, +C4<010110>; +S_0x9cbf20 .scope module, "register" "register32" 3 36, 7 3, S_0x9cbd70; + .timescale 0 0; +v0x9cc010_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cc090_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cc110_0 .var "q", 31 0; +v0x9cc1b0_0 .net "wrenable", 0 0, L_0x9d93a0; 1 drivers +S_0x9cb880 .scope generate, "register_generate[23]" "register_generate[23]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cb978 .param/l "i" 3 35, +C4<010111>; +S_0x9cba30 .scope module, "register" "register32" 3 36, 7 3, S_0x9cb880; + .timescale 0 0; +v0x9cbb20_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cbba0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cbc20_0 .var "q", 31 0; +v0x9cbcc0_0 .net "wrenable", 0 0, L_0x9d92f0; 1 drivers +S_0x9cb270 .scope generate, "register_generate[24]" "register_generate[24]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cb368 .param/l "i" 3 35, +C4<011000>; +S_0x9cb420 .scope module, "register" "register32" 3 36, 7 3, S_0x9cb270; + .timescale 0 0; +v0x9cb510_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9ca0b0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ca1c0_0 .var "q", 31 0; +v0x9cb7d0_0 .net "wrenable", 0 0, L_0x9d9500; 1 drivers +S_0x9cad80 .scope generate, "register_generate[25]" "register_generate[25]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9cae78 .param/l "i" 3 35, +C4<011001>; +S_0x9caf30 .scope module, "register" "register32" 3 36, 7 3, S_0x9cad80; + .timescale 0 0; +v0x9cb020_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cb0a0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cb120_0 .var "q", 31 0; +v0x9cb1c0_0 .net "wrenable", 0 0, L_0x9d9440; 1 drivers +S_0x9ca890 .scope generate, "register_generate[26]" "register_generate[26]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9ca988 .param/l "i" 3 35, +C4<011010>; +S_0x9caa40 .scope module, "register" "register32" 3 36, 7 3, S_0x9ca890; + .timescale 0 0; +v0x9cab30_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9cabb0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9cac30_0 .var "q", 31 0; +v0x9cacd0_0 .net "wrenable", 0 0, L_0x9d96a0; 1 drivers +S_0x9ca3a0 .scope generate, "register_generate[27]" "register_generate[27]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9ca498 .param/l "i" 3 35, +C4<011011>; +S_0x9ca550 .scope module, "register" "register32" 3 36, 7 3, S_0x9ca3a0; + .timescale 0 0; +v0x9ca640_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9ca6c0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ca740_0 .var "q", 31 0; +v0x9ca7e0_0 .net "wrenable", 0 0, L_0x9d95a0; 1 drivers +S_0x9c9d90 .scope generate, "register_generate[28]" "register_generate[28]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9c9e88 .param/l "i" 3 35, +C4<011100>; +S_0x9c9f40 .scope module, "register" "register32" 3 36, 7 3, S_0x9c9d90; + .timescale 0 0; +v0x9ca030_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9ca140_0 .alias "d", 31 0, v0x9d8040_0; +v0x9ca250_0 .var "q", 31 0; +v0x9ca2f0_0 .net "wrenable", 0 0, L_0x9d9850; 1 drivers +S_0x9c98d0 .scope generate, "register_generate[29]" "register_generate[29]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9c99c8 .param/l "i" 3 35, +C4<011101>; +S_0x9c9a80 .scope module, "register" "register32" 3 36, 7 3, S_0x9c98d0; + .timescale 0 0; +v0x9c9b70_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9c9bf0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9c9c70_0 .var "q", 31 0; +v0x9c9d10_0 .net "wrenable", 0 0, L_0x9d9770; 1 drivers +S_0x9c93e0 .scope generate, "register_generate[30]" "register_generate[30]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9c94d8 .param/l "i" 3 35, +C4<011110>; +S_0x9c9570 .scope module, "register" "register32" 3 36, 7 3, S_0x9c93e0; + .timescale 0 0; +v0x9c9660_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9c96e0_0 .alias "d", 31 0, v0x9d8040_0; +v0x9c97b0_0 .var "q", 31 0; +v0x9c9850_0 .net "wrenable", 0 0, L_0x9d9a10; 1 drivers +S_0x9c8eb0 .scope generate, "register_generate[31]" "register_generate[31]" 3 35, 3 35, S_0x9c8dc0; + .timescale 0 0; +P_0x9c8888 .param/l "i" 3 35, +C4<011111>; +S_0x9c9020 .scope module, "register" "register32" 3 36, 7 3, S_0x9c8eb0; + .timescale 0 0; +v0x9c9130_0 .alias "clk", 0 0, v0x9d7cb0_0; +v0x9c9200_0 .alias "d", 31 0, v0x9d8040_0; +v0x9c92b0_0 .var "q", 31 0; +v0x9c9330_0 .net "wrenable", 0 0, L_0x9d9920; 1 drivers +E_0x9c8730 .event posedge, v0x9a6260_0; +S_0x98fac0 .scope module, "tester" "hw4testbench" 2 36, 2 78, S_0x98f260; + .timescale 0 0; +v0x9a6260_0 .var "Clk", 0 0; +v0x9c8570_0 .alias "ReadData1", 31 0, v0x9d7d30_0; +v0x9c8610_0 .alias "ReadData2", 31 0, v0x9d7e40_0; +v0x9c86b0_0 .var "ReadRegister1", 4 0; +v0x9c8760_0 .var "ReadRegister2", 4 0; +v0x9c8800_0 .var "RegWrite", 0 0; +v0x9c88e0_0 .var "WriteData", 31 0; +v0x9c8980_0 .var "WriteRegister", 4 0; +v0x9c8a70_0 .net "begintest", 0 0, v0x9d8140_0; 1 drivers +v0x9c8b10_0 .var "dutpassed", 0 0; +v0x9c8c10_0 .var "endtest", 0 0; +v0x9c8cb0_0 .var "index", 5 0; +E_0x98f660 .event posedge, v0x9c8a70_0; + .scope S_0x9d28e0; +T_0 ; + %wait E_0x9c8730; + %load/v 8, v0x9d2b70_0, 1; + %jmp/0xz T_0.0, 8; + %load/v 8, v0x9d2a50_0, 32; + %set/v v0x9d2ad0_0, 8, 32; +T_0.0 ; + %jmp T_0; + .thread T_0; + .scope S_0x9d23f0; +T_1 ; + %wait E_0x9c8730; + %load/v 8, v0x9d2680_0, 1; + %jmp/0xz T_1.0, 8; + %load/v 8, v0x9d2560_0, 32; + %set/v v0x9d25e0_0, 8, 32; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_0x9d1f00; +T_2 ; + %wait E_0x9c8730; + %load/v 8, v0x9d2190_0, 1; + %jmp/0xz T_2.0, 8; + %load/v 8, v0x9d2070_0, 32; + %set/v v0x9d20f0_0, 8, 32; +T_2.0 ; + %jmp T_2; + .thread T_2; + .scope S_0x9d1a10; +T_3 ; + %wait E_0x9c8730; + %load/v 8, v0x9d1ca0_0, 1; + %jmp/0xz T_3.0, 8; + %load/v 8, v0x9d1b80_0, 32; + %set/v v0x9d1c00_0, 8, 32; +T_3.0 ; + %jmp T_3; + .thread T_3; + .scope S_0x9d1520; +T_4 ; + %wait E_0x9c8730; + %load/v 8, v0x9d17b0_0, 1; + %jmp/0xz T_4.0, 8; + %load/v 8, v0x9d1690_0, 32; + %set/v v0x9d1710_0, 8, 32; +T_4.0 ; + %jmp T_4; + .thread T_4; + .scope S_0x9d1030; +T_5 ; + %wait E_0x9c8730; + %load/v 8, v0x9d12c0_0, 1; + %jmp/0xz T_5.0, 8; + %load/v 8, v0x9d11a0_0, 32; + %set/v v0x9d1220_0, 8, 32; +T_5.0 ; + %jmp T_5; + .thread T_5; + .scope S_0x9d0b40; +T_6 ; + %wait E_0x9c8730; + %load/v 8, v0x9d0dd0_0, 1; + %jmp/0xz T_6.0, 8; + %load/v 8, v0x9d0cb0_0, 32; + %set/v v0x9d0d30_0, 8, 32; +T_6.0 ; + %jmp T_6; + .thread T_6; + .scope S_0x9d0650; +T_7 ; + %wait E_0x9c8730; + %load/v 8, v0x9d08e0_0, 1; + %jmp/0xz T_7.0, 8; + %load/v 8, v0x9d07c0_0, 32; + %set/v v0x9d0840_0, 8, 32; +T_7.0 ; + %jmp T_7; + .thread T_7; + .scope S_0x9d0160; +T_8 ; + %wait E_0x9c8730; + %load/v 8, v0x9d03f0_0, 1; + %jmp/0xz T_8.0, 8; + %load/v 8, v0x9d02d0_0, 32; + %set/v v0x9d0350_0, 8, 32; +T_8.0 ; + %jmp T_8; + .thread T_8; + .scope S_0x9cfc70; +T_9 ; + %wait E_0x9c8730; + %load/v 8, v0x9cff00_0, 1; + %jmp/0xz T_9.0, 8; + %load/v 8, v0x9cfde0_0, 32; + %set/v v0x9cfe60_0, 8, 32; +T_9.0 ; + %jmp T_9; + .thread T_9; + .scope S_0x9cf780; +T_10 ; + %wait E_0x9c8730; + %load/v 8, v0x9cfa10_0, 1; + %jmp/0xz T_10.0, 8; + %load/v 8, v0x9cf8f0_0, 32; + %set/v v0x9cf970_0, 8, 32; +T_10.0 ; + %jmp T_10; + .thread T_10; + .scope S_0x9cf290; +T_11 ; + %wait E_0x9c8730; + %load/v 8, v0x9cf520_0, 1; + %jmp/0xz T_11.0, 8; + %load/v 8, v0x9cf400_0, 32; + %set/v v0x9cf480_0, 8, 32; +T_11.0 ; + %jmp T_11; + .thread T_11; + .scope S_0x9ceda0; +T_12 ; + %wait E_0x9c8730; + %load/v 8, v0x9cf030_0, 1; + %jmp/0xz T_12.0, 8; + %load/v 8, v0x9cef10_0, 32; + %set/v v0x9cef90_0, 8, 32; +T_12.0 ; + %jmp T_12; + .thread T_12; + .scope S_0x9ce8b0; +T_13 ; + %wait E_0x9c8730; + %load/v 8, v0x9ceb40_0, 1; + %jmp/0xz T_13.0, 8; + %load/v 8, v0x9cea20_0, 32; + %set/v v0x9ceaa0_0, 8, 32; +T_13.0 ; + %jmp T_13; + .thread T_13; + .scope S_0x9ce3c0; +T_14 ; + %wait E_0x9c8730; + %load/v 8, v0x9ce650_0, 1; + %jmp/0xz T_14.0, 8; + %load/v 8, v0x9ce530_0, 32; + %set/v v0x9ce5b0_0, 8, 32; +T_14.0 ; + %jmp T_14; + .thread T_14; + .scope S_0x9cdcc0; +T_15 ; + %wait E_0x9c8730; + %load/v 8, v0x9cb6b0_0, 1; + %jmp/0xz T_15.0, 8; + %load/v 8, v0x9cb590_0, 32; + %set/v v0x9cb610_0, 8, 32; +T_15.0 ; + %jmp T_15; + .thread T_15; + .scope S_0x9cd7d0; +T_16 ; + %wait E_0x9c8730; + %load/v 8, v0x9cda60_0, 1; + %jmp/0xz T_16.0, 8; + %load/v 8, v0x9cd940_0, 32; + %set/v v0x9cd9c0_0, 8, 32; +T_16.0 ; + %jmp T_16; + .thread T_16; + .scope S_0x9cd2e0; +T_17 ; + %wait E_0x9c8730; + %load/v 8, v0x9cd570_0, 1; + %jmp/0xz T_17.0, 8; + %load/v 8, v0x9cd450_0, 32; + %set/v v0x9cd4d0_0, 8, 32; +T_17.0 ; + %jmp T_17; + .thread T_17; + .scope S_0x9ccdf0; +T_18 ; + %wait E_0x9c8730; + %load/v 8, v0x9cd080_0, 1; + %jmp/0xz T_18.0, 8; + %load/v 8, v0x9ccf60_0, 32; + %set/v v0x9ccfe0_0, 8, 32; +T_18.0 ; + %jmp T_18; + .thread T_18; + .scope S_0x9cc900; +T_19 ; + %wait E_0x9c8730; + %load/v 8, v0x9ccb90_0, 1; + %jmp/0xz T_19.0, 8; + %load/v 8, v0x9cca70_0, 32; + %set/v v0x9ccaf0_0, 8, 32; +T_19.0 ; + %jmp T_19; + .thread T_19; + .scope S_0x9cc410; +T_20 ; + %wait E_0x9c8730; + %load/v 8, v0x9cc6a0_0, 1; + %jmp/0xz T_20.0, 8; + %load/v 8, v0x9cc580_0, 32; + %set/v v0x9cc600_0, 8, 32; +T_20.0 ; + %jmp T_20; + .thread T_20; + .scope S_0x9cbf20; +T_21 ; + %wait E_0x9c8730; + %load/v 8, v0x9cc1b0_0, 1; + %jmp/0xz T_21.0, 8; + %load/v 8, v0x9cc090_0, 32; + %set/v v0x9cc110_0, 8, 32; +T_21.0 ; + %jmp T_21; + .thread T_21; + .scope S_0x9cba30; +T_22 ; + %wait E_0x9c8730; + %load/v 8, v0x9cbcc0_0, 1; + %jmp/0xz T_22.0, 8; + %load/v 8, v0x9cbba0_0, 32; + %set/v v0x9cbc20_0, 8, 32; +T_22.0 ; + %jmp T_22; + .thread T_22; + .scope S_0x9cb420; +T_23 ; + %wait E_0x9c8730; + %load/v 8, v0x9cb7d0_0, 1; + %jmp/0xz T_23.0, 8; + %load/v 8, v0x9ca0b0_0, 32; + %set/v v0x9ca1c0_0, 8, 32; +T_23.0 ; + %jmp T_23; + .thread T_23; + .scope S_0x9caf30; +T_24 ; + %wait E_0x9c8730; + %load/v 8, v0x9cb1c0_0, 1; + %jmp/0xz T_24.0, 8; + %load/v 8, v0x9cb0a0_0, 32; + %set/v v0x9cb120_0, 8, 32; +T_24.0 ; + %jmp T_24; + .thread T_24; + .scope S_0x9caa40; +T_25 ; + %wait E_0x9c8730; + %load/v 8, v0x9cacd0_0, 1; + %jmp/0xz T_25.0, 8; + %load/v 8, v0x9cabb0_0, 32; + %set/v v0x9cac30_0, 8, 32; +T_25.0 ; + %jmp T_25; + .thread T_25; + .scope S_0x9ca550; +T_26 ; + %wait E_0x9c8730; + %load/v 8, v0x9ca7e0_0, 1; + %jmp/0xz T_26.0, 8; + %load/v 8, v0x9ca6c0_0, 32; + %set/v v0x9ca740_0, 8, 32; +T_26.0 ; + %jmp T_26; + .thread T_26; + .scope S_0x9c9f40; +T_27 ; + %wait E_0x9c8730; + %load/v 8, v0x9ca2f0_0, 1; + %jmp/0xz T_27.0, 8; + %load/v 8, v0x9ca140_0, 32; + %set/v v0x9ca250_0, 8, 32; +T_27.0 ; + %jmp T_27; + .thread T_27; + .scope S_0x9c9a80; +T_28 ; + %wait E_0x9c8730; + %load/v 8, v0x9c9d10_0, 1; + %jmp/0xz T_28.0, 8; + %load/v 8, v0x9c9bf0_0, 32; + %set/v v0x9c9c70_0, 8, 32; +T_28.0 ; + %jmp T_28; + .thread T_28; + .scope S_0x9c9570; +T_29 ; + %wait E_0x9c8730; + %load/v 8, v0x9c9850_0, 1; + %jmp/0xz T_29.0, 8; + %load/v 8, v0x9c96e0_0, 32; + %set/v v0x9c97b0_0, 8, 32; +T_29.0 ; + %jmp T_29; + .thread T_29; + .scope S_0x9c9020; +T_30 ; + %wait E_0x9c8730; + %load/v 8, v0x9c9330_0, 1; + %jmp/0xz T_30.0, 8; + %load/v 8, v0x9c9200_0, 32; + %set/v v0x9c92b0_0, 8, 32; +T_30.0 ; + %jmp T_30; + .thread T_30; + .scope S_0x9d6c90; +T_31 ; + %wait E_0x9c8730; + %load/v 8, v0x9cdf00_0, 1; + %jmp/0xz T_31.0, 8; + %set/v v0x9cde30_0, 0, 32; +T_31.0 ; + %jmp T_31; + .thread T_31; + .scope S_0x98fac0; +T_32 ; + %set/v v0x9c88e0_0, 0, 32; + %set/v v0x9c86b0_0, 0, 5; + %set/v v0x9c8760_0, 0, 5; + %set/v v0x9c8980_0, 0, 5; + %set/v v0x9c8800_0, 0, 1; + %set/v v0x9a6260_0, 0, 1; + %end; + .thread T_32; + .scope S_0x98fac0; +T_33 ; + %wait E_0x98f660; + %set/v v0x9c8c10_0, 0, 1; + %set/v v0x9c8b10_0, 1, 1; + %delay 10, 0; + %movi 8, 2, 5; + %set/v v0x9c8980_0, 8, 5; + %movi 8, 42, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 1, 1; + %movi 8, 2, 5; + %set/v v0x9c86b0_0, 8, 5; + %movi 8, 2, 5; + %set/v v0x9c8760_0, 8, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 42, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 42, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.0, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 128 "$display", "Test Case 1 Failed"; +T_33.0 ; + %movi 8, 2, 5; + %set/v v0x9c8980_0, 8, 5; + %movi 8, 15, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 1, 1; + %movi 8, 2, 5; + %set/v v0x9c86b0_0, 8, 5; + %movi 8, 2, 5; + %set/v v0x9c8760_0, 8, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 15, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 15, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.2, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 143 "$display", "Test Case 2 Failed"; +T_33.2 ; + %movi 8, 1, 6; + %set/v v0x9c8cb0_0, 8, 6; +T_33.4 ; + %load/v 8, v0x9c8cb0_0, 6; + %mov 14, 0, 2; + %cmpi/u 8, 32, 8; + %jmp/0xz T_33.5, 5; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c8980_0, 8, 5; + %movi 8, 145, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 1, 1; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c86b0_0, 8, 5; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c8760_0, 8, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 145, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 145, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.6, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 160 "$display", "Test Case Failed Wrote 145 r:%b Read %d from %b and %d from %b", &PV, v0x9c8570_0, v0x9c86b0_0, v0x9c8610_0, v0x9c8760_0; +T_33.6 ; + %load/v 8, v0x9c8cb0_0, 6; + %mov 14, 0, 26; + %addi 8, 1, 32; + %set/v v0x9c8cb0_0, 8, 6; + %jmp T_33.4; +T_33.5 ; + %movi 8, 1, 6; + %set/v v0x9c8cb0_0, 8, 6; +T_33.8 ; + %load/v 8, v0x9c8cb0_0, 6; + %mov 14, 0, 2; + %cmpi/u 8, 32, 8; + %jmp/0xz T_33.9, 5; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c8980_0, 8, 5; + %movi 8, 132, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 0, 1; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c86b0_0, 8, 5; + %load/v 8, v0x9c8cb0_0, 5; Only need 5 of 6 bits +; Save base=8 wid=5 in lookaside. + %set/v v0x9c8760_0, 8, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 145, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 145, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.10, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 179 "$display", "Test Case WriteEnable Failed r:%b Read %d from %b and %d from %b", &PV, v0x9c8570_0, v0x9c86b0_0, v0x9c8610_0, v0x9c8760_0; +T_33.10 ; + %load/v 8, v0x9c8cb0_0, 6; + %mov 14, 0, 26; + %addi 8, 1, 32; + %set/v v0x9c8cb0_0, 8, 6; + %jmp T_33.8; +T_33.9 ; + %movi 8, 17, 5; + %set/v v0x9c8980_0, 8, 5; + %movi 8, 299, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 1, 1; + %movi 8, 16, 5; + %set/v v0x9c86b0_0, 8, 5; + %movi 8, 18, 5; + %set/v v0x9c8760_0, 8, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 145, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 145, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.12, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 196 "$display", "Test Case decoder Failed Wrote %d to %b and Read %d from %b and %d from %b", v0x9c88e0_0, v0x9c8980_0, v0x9c8570_0, v0x9c86b0_0, v0x9c8610_0, v0x9c8760_0; +T_33.12 ; + %set/v v0x9c8980_0, 0, 5; + %movi 8, 299, 32; + %set/v v0x9c88e0_0, 8, 32; + %set/v v0x9c8800_0, 1, 1; + %set/v v0x9c86b0_0, 0, 5; + %set/v v0x9c8760_0, 0, 5; + %delay 5, 0; + %set/v v0x9a6260_0, 1, 1; + %delay 5, 0; + %set/v v0x9a6260_0, 0, 1; + %load/v 8, v0x9c8570_0, 32; + %cmpi/u 8, 0, 32; + %inv 4, 1; + %mov 8, 4, 1; + %load/v 9, v0x9c8610_0, 32; + %cmpi/u 9, 0, 32; + %inv 4, 1; + %or 8, 4, 1; + %jmp/0xz T_33.14, 8; + %set/v v0x9c8b10_0, 0, 1; + %vpi_call 2 212 "$display", "Test Case zero reg Failed Read %d from %b and %d from %b", v0x9c8570_0, v0x9c86b0_0, v0x9c8610_0, v0x9c8760_0; +T_33.14 ; + %delay 5, 0; + %set/v v0x9c8c10_0, 1, 1; + %jmp T_33; + .thread T_33; + .scope S_0x98f260; +T_34 ; + %set/v v0x9d8140_0, 0, 1; + %delay 10, 0; + %set/v v0x9d8140_0, 1, 1; + %delay 1000, 0; + %end; + .thread T_34; + .scope S_0x98f260; +T_35 ; + %wait E_0x98e7b0; + %vpi_call 2 61 "$display", "DUT passed?: %b", v0x9d81c0_0; + %jmp T_35; + .thread T_35; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "regfile.t.v"; + "./regfile.v"; + "./decoder1to32.v"; + "./register32zero.v"; + "./mux32to1by32.v"; + "./register32.v"; diff --git a/regfile.t.v b/regfile.t.v index f13815a..1baca73 100644 --- a/regfile.t.v +++ b/regfile.t.v @@ -1,8 +1,10 @@ //------------------------------------------------------------------------------ -// Test harness validates hw4testbench by connecting it to various functional +// Test harness validates hw4testbench by connecting it to various functional // or broken register files, and verifying that it correctly identifies each //------------------------------------------------------------------------------ +`include "regfile.v" + module hw4testbenchharness(); wire[31:0] ReadData1; // Data from first register read @@ -34,15 +36,15 @@ module hw4testbenchharness(); hw4testbench tester ( .begintest(begintest), - .endtest(endtest), + .endtest(endtest), .dutpassed(dutpassed), .ReadData1(ReadData1), .ReadData2(ReadData2), - .WriteData(WriteData), - .ReadRegister1(ReadRegister1), + .WriteData(WriteData), + .ReadRegister1(ReadRegister1), .ReadRegister2(ReadRegister2), .WriteRegister(WriteRegister), - .RegWrite(RegWrite), + .RegWrite(RegWrite), .Clk(Clk) ); @@ -91,6 +93,9 @@ output reg RegWrite, output reg Clk ); + // For looping through cases + reg [5:0] index; + // Initialize register driver signals initial begin WriteData=32'd0; @@ -107,7 +112,7 @@ output reg Clk dutpassed = 1; #10 - // Test Case 1: + // Test Case 1: // Write '42' to register 2, verify with Read Ports 1 and 2 // (Passes because example register file is hardwired to return 42) WriteRegister = 5'd2; @@ -123,7 +128,7 @@ output reg Clk $display("Test Case 1 Failed"); end - // Test Case 2: + // Test Case 2: // Write '15' to register 2, verify with Read Ports 1 and 2 // (Fails with example register file, but should pass with yours) WriteRegister = 5'd2; @@ -138,6 +143,76 @@ output reg Clk $display("Test Case 2 Failed"); end + // All correct functioning test cases + // Write 145 to given register, verify with read ports 1 and 2 + + for (index = 1; index < 32; index = index+1) begin + + WriteRegister = index[4:0]; + WriteData = 32'd145; + RegWrite = 1; + ReadRegister1 = index[4:0]; + ReadRegister2 = index[4:0]; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 != 145) || (ReadData2 != 145)) begin + dutpassed = 0; + $display("Test Case Failed Wrote 145 r:%b Read %d from %b and %d from %b", index[4:0], ReadData1, ReadRegister1, ReadData2, ReadRegister2); + end + + end + + // Check if Write Enable works + // Write 132 to all registers with RegWrite = 0, verify all ports are still 145 + + for (index = 1; index < 32; index = index+1) begin + + WriteRegister = index[4:0]; + WriteData = 32'd132; + RegWrite = 0; + ReadRegister1 = index[4:0]; + ReadRegister2 = index[4:0]; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 != 145) || (ReadData2 != 145)) begin + dutpassed = 0; + $display("Test Case WriteEnable Failed r:%b Read %d from %b and %d from %b", index[4:0], ReadData1, ReadRegister1, ReadData2, ReadRegister2); + end + + end + + // Test decoder works and only one register is being written + // Write 6983 to address 17, read address 16 and 18 as 145 still + + WriteRegister = 5'd17; + WriteData = 32'd299; + RegWrite = 1; + ReadRegister1 = 5'd16; + ReadRegister2 = 5'd18; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 != 145) || (ReadData2 != 145)) begin + dutpassed = 0; + $display("Test Case decoder Failed Wrote %d to %b and Read %d from %b and %d from %b", WriteData, WriteRegister, ReadData1, ReadRegister1, ReadData2, ReadRegister2); + end + + + // Zero register working test cases + // Write 299 to register address zero, read zero from ports 1 and 2 + + WriteRegister = 5'b0; + WriteData = 32'd299; + RegWrite = 1; + ReadRegister1 = 5'b0; + ReadRegister2 = 5'b0; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 != 0) || (ReadData2 != 0)) begin + dutpassed = 0; + $display("Test Case zero reg Failed Read %d from %b and %d from %b", ReadData1, ReadRegister1, ReadData2, ReadRegister2); + end + + // All done! Wait a moment and signal test completion. #5 @@ -145,4 +220,4 @@ output reg Clk end -endmodule \ No newline at end of file +endmodule diff --git a/regfile.v b/regfile.v index b8a3c74..47691d4 100644 --- a/regfile.v +++ b/regfile.v @@ -6,6 +6,11 @@ // 1 synchronous, positive edge triggered write port //------------------------------------------------------------------------------ +`include "register32.v" +`include "register32zero.v" +`include "decoder1to32.v" +`include "mux32to1by32.v" + module regfile ( output[31:0] ReadData1, // Contents of first register read @@ -17,11 +22,86 @@ input[4:0] WriteRegister, // Address of register to write input RegWrite, // Enable writing of register when High input Clk // Clock (Positive Edge Triggered) ); + wire [31:0] enable; + wire [31:0] regout[31:0]; + genvar i; + + // Instantiate decoder + decoder1to32 en_decoder(enable[31:0], RegWrite, WriteRegister); - // These two lines are clearly wrong. They are included to showcase how the - // test harness works. Delete them after you understand the testing process, - // and replace them with your actual code. - assign ReadData1 = 42; - assign ReadData2 = 42; + // First register is always zero + register32zero register0(regout[0], WriteData, enable[0], Clk); + generate + for (i = 1; i < 32; i=i+1) begin : register_generate + register32 register (regout[i], WriteData, enable[i], Clk); + end + endgenerate -endmodule \ No newline at end of file + //Output Muxes + mux32to1by32 mux_d1 (ReadData1, ReadRegister1, + regout[0], + regout[1], + regout[2], + regout[3], + regout[4], + regout[5], + regout[6], + regout[7], + regout[8], + regout[9], + regout[10], + regout[11], + regout[12], + regout[13], + regout[14], + regout[15], + regout[16], + regout[17], + regout[18], + regout[19], + regout[20], + regout[21], + regout[22], + regout[23], + regout[24], + regout[25], + regout[26], + regout[27], + regout[28], + regout[29], + regout[30], + regout[31]); + mux32to1by32 mux_d2 (ReadData1, ReadRegister2, + regout[0], + regout[1], + regout[2], + regout[3], + regout[4], + regout[5], + regout[6], + regout[7], + regout[8], + regout[9], + regout[10], + regout[11], + regout[12], + regout[13], + regout[14], + regout[15], + regout[16], + regout[17], + regout[18], + regout[19], + regout[20], + regout[21], + regout[22], + regout[23], + regout[24], + regout[25], + regout[26], + regout[27], + regout[28], + regout[29], + regout[30], + regout[31]); +endmodule diff --git a/register32.v b/register32.v new file mode 100644 index 0000000..ef2e01e --- /dev/null +++ b/register32.v @@ -0,0 +1,17 @@ +// 32 Bit D Flip-Flop with enable +// Positive edge triggered +module register32 +( + output reg[31:0] q, + input[31:0] d, + input wrenable, + input clk + ); + + always @(posedge clk) begin + if(wrenable) begin + q = d; + end + end + +endmodule diff --git a/register32zero.v b/register32zero.v new file mode 100644 index 0000000..7a8af28 --- /dev/null +++ b/register32zero.v @@ -0,0 +1,17 @@ +// 32 Bit dummy register with enable +// Positive edge triggered +module register32zero +( + output reg[31:0] q, + input[31:0] d, + input wrenable, + input clk + ); + + always @(posedge clk) begin + if(wrenable) begin + q = 0; + end + end + +endmodule diff --git a/run_tests.sh b/run_tests.sh new file mode 100755 index 0000000..60700b9 --- /dev/null +++ b/run_tests.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +iverilog -Wall -o regfile.out regfile.t.v +vvp regfile.out