Executing wfi in U-mode does not raise an exception #249
Description
Bug Description:
In RISC-V, the TW bit is bit 21 of the mstatus CSR.
In NutShell, when mstatus.TW is set to 1 and wfi is executed in U-mode, the core does not trigger an illegal instruction exception.
However, Spike (the reference model) raises an illegal instruction exception under the same conditions.
Test program: test_wfi.zip
Log information:
root@e08b13761a9a:/xs-env/NutShell# ./build/emu -b 0 -e 0 -i /xs-env/NutShell/test_wfi.img --diff /xs-env/ready-to-run/riscv64-nutshell-spike-so
emu compiled at Nov 28 2025, 02:32:02
Using simulated 32768B flash
Using simulated 8192MB RAM
The image is /xs-env/NutShell/test_wfi.img
The reference model is /xs-env/ready-to-run/riscv64-nutshell-spike-so
The first instruction of core 0 has commited. Difftest enabled.
============== In the last commit group ==============
the first commit instr pc of DUT is 0x000000008000005a
the first commit instr pc of REF is 0x000000008000005a
============== Commit Group Trace (Core 0) ==============
commit group [00]: pc 0080000012 cmtcnt 1
commit group [01]: pc 0080000016 cmtcnt 1
commit group [02]: pc 008000001a cmtcnt 1
commit group [03]: pc 008000001e cmtcnt 1
commit group [04]: pc 0080000022 cmtcnt 1
commit group [05]: pc 0080000026 cmtcnt 1
commit group [06]: pc 008000002a cmtcnt 1
commit group [07]: pc 008000002e cmtcnt 1
commit group [08]: pc 0080000032 cmtcnt 1
commit group [09]: pc 0080000036 cmtcnt 1
commit group [10]: pc 008000003a cmtcnt 1
commit group [11]: pc 008000003e cmtcnt 1
commit group [12]: pc 0080000050 cmtcnt 1
commit group [13]: pc 0080000054 cmtcnt 1
commit group [14]: pc 0080000058 cmtcnt 1
commit group [15]: pc 008000005a cmtcnt 1 <--
============== Commit Instr Trace ==============
[00] commit pc 0000000080000000 inst f14022f3 wen 1 dst 05 data 0000000000000000 idx 000 csrr t0, mhartid
[01] commit pc 0000000080000004 inst 82634301 wen 1 dst 06 data 0000000000000000 idx 000 c.li t1, 0
[02] commit pc 0000000080000006 inst 00628263 wen 0 dst 00 data 0000000000000000 idx 000 beq t0, t1, pc + 4
[03] commit pc 000000008000000a inst 00000417 wen 1 dst 08 data 000000008000000a idx 000 auipc s0, 0x0
[04] commit pc 000000008000000e inst 00c40413 wen 1 dst 08 data 0000000080000016 idx 000 addi s0, s0, 12
[05] commit pc 0000000080000012 inst 00040067 wen 0 dst 00 data 0000000080000016 idx 000 jr s0
[06] commit pc 0000000080000016 inst 00000697 wen 1 dst 13 data 0000000080000016 idx 000 auipc a3, 0x0
[07] commit pc 000000008000001a inst 06a68693 wen 1 dst 13 data 0000000080000080 idx 000 addi a3, a3, 106
[08] commit pc 000000008000001e inst 30569073 wen 0 dst 00 data 0000000080000080 idx 000 csrw mtvec, a3
[09] commit pc 0000000080000022 inst 00000697 wen 1 dst 13 data 0000000080000022 idx 000 auipc a3, 0x0
[10] commit pc 0000000080000026 inst 02e68693 wen 1 dst 13 data 0000000080000050 idx 000 addi a3, a3, 46
[11] commit pc 000000008000002a inst 34169073 wen 0 dst 00 data 0000000080000050 idx 000 csrw mepc, a3
[12] commit pc 000000008000002e inst 002005b7 wen 1 dst 11 data 0000000000200000 idx 000 lui a1, 0x200
[13] commit pc 0000000080000032 inst 30059073 wen 0 dst 00 data 0000000000200000 idx 000 csrw mstatus, a1
[14] commit pc 0000000080000036 inst 30405073 wen 0 dst 00 data 0000000000200000 idx 000 csrwi mie, 0
[15] commit pc 000000008000003a inst 30002973 wen 1 dst 18 data 0000000a00200000 idx 000 csrr s2, mstatus
[16] commit pc 000000008000003e inst 30200073 wen 0 dst 00 data 0000000a00200000 idx 000 mret
[17] commit pc 0000000080000050 inst 00001117 wen 1 dst 02 data 0000000080001050 idx 000 auipc sp, 0x1
[18] commit pc 0000000080000054 inst ff810113 wen 1 dst 02 data 0000000080001048 idx 000 addi sp, sp, -8
[19] commit pc 0000000080000058 inst 0073a009 wen 0 dst 00 data 0000000080001048 idx 000 c.j pc + 2
[20] commit pc 000000008000005a inst 10500073 wen 0 dst 00 data 0000000080001048 idx 000 wfi <--
============== REF Regs ==============
zero: 0x0000000000000000 ra: 0x923361a4e29d1b72 sp: 0x0000000080001048 gp: 0xad3432412e25ca7c
tp: 0x4964b9cfd653f186 t0: 0x0000000000000000 t1: 0x0000000000000000 t2: 0x885e7398d5ffdcf6
s0: 0x0000000080000016 s1: 0xb956c90fbf1cfecd a0: 0xdf71aa24a179d94b a1: 0x0000000000200000
a2: 0x46933b2161d0c883 a3: 0x0000000080000050 a4: 0xceb2f48d8dc09b40 a5: 0xa5a19c327ee3c242
a6: 0xbb78f217d74bd655 a7: 0x744c109a8b9e2f1d s2: 0x0000000a00200000 s3: 0x89970b0f1ecb7e81
s4: 0x3938b180b94b7e1a s5: 0xae462cbb0096e7ae s6: 0x38950c8d637d2157 s7: 0x1fd14d5ad32577c2
s8: 0x43d22b1e7929f70f s9: 0x1bb9fad0701147f1 s10: 0x67ddf33466602ec2 s11: 0x9a163648c2093fbd
t3: 0x1cc636ce56ffc75e t4: 0xbd25f29ca461e4eb t5: 0x93ef6e148f8d2a0b t6: 0xd5af0c5471b79a9e
ft0: 0x7ff8000000000000 ft1: 0x7ff8000000000000 ft2: 0x7ff8000000000000 ft3: 0x7ff8000000000000
ft4: 0x7ff8000000000000 ft5: 0x7ff8000000000000 ft6: 0x7ff8000000000000 ft7: 0x7ff8000000000000
fs0: 0x7ff8000000000000 fs1: 0x7ff8000000000000 fa0: 0x7ff8000000000000 fa1: 0x7ff8000000000000
fa2: 0x7ff8000000000000 fa3: 0x7ff8000000000000 fa4: 0x7ff8000000000000 fa5: 0x7ff8000000000000
fa6: 0x7ff8000000000000 fa7: 0x7ff8000000000000 fs2: 0x7ff8000000000000 fs3: 0x7ff8000000000000
fs4: 0x7ff8000000000000 fs5: 0x7ff8000000000000 fs6: 0x7ff8000000000000 fs7: 0x7ff8000000000000
fs8: 0x7ff8000000000000 fs9: 0x7ff8000000000000 fs10: 0x7ff8000000000000 fs11: 0x7ff8000000000000
ft8: 0x7ff8000000000000 ft9: 0x7ff8000000000000 ft10: 0x7ff8000000000000 ft11: 0x7ff8000000000000
pc: 0x0000000080000080 mstatus: 0x0000000a00200000 mcause: 0x0000000000000002 mepc: 0x000000008000005a
sstatus: 0x0000000200000000 scause: 0x0000000000000000 sepc: 0x0000000000000000
satp: 0x0000000000000000
mip: 0x0000000000000000 mie: 0x0000000000000000 mscratch: 0x0000000000000000 sscratch: 0x0000000000000000
mideleg: 0x0000000000000000 medeleg: 0x0000000000000000
mtval: 0x0000000000000000 stval: 0xb8923d6126918fa0 mtvec: 0x0000000080000080 stvec: 0x0000000000000000
privilege mode:3
privilegeMode: 0
mode different at pc = 0x008000005a, right= 0x0000000000000003, wrong = 0x0000000000000000
mstatus different at pc = 0x008000005a, right= 0x0000000a00200000, wrong = 0x0000000a00200080
mepc different at pc = 0x008000005a, right= 0x000000008000005a, wrong = 0x0000000080000050
mcause different at pc = 0x008000005a, right= 0x0000000000000002, wrong = 0x0000000000000000
Core 0: ABORT at pc = 0x80000060
Core-0 instrCnt = 21, cycleCnt = 606, IPC = 0.034653
Seed=0 Guest cycle spent: 607 (this will be different from cycleCnt if emu loads a snapshot)
Host time spent: 91ms
Environment:
NutShell: commit e315a27