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Description
Bug Description:
TVM is bit 20 of the mstatus register.
The RISCV specification is as follows:
The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.
However, when TVM is 1, the NutShell processor will not cause an illegal instruction exception when executing SFENCE.VMA in S mode.
Test program and log information: test_SFENCE.zip
Inconsistent information:
Environment:
NutShell: commit e315a27
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