From 66120cde6c6472598e94d7409a2f37c8b308b716 Mon Sep 17 00:00:00 2001 From: =youzi27 <=809891392@qq.com> Date: Wed, 6 Dec 2023 13:36:29 +0800 Subject: [PATCH 1/2] Fix:epc[0] value is always 0 --- src/main/scala/nutcore/backend/fu/CSR.scala | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala index 3e594656..46bd3bb1 100644 --- a/src/main/scala/nutcore/backend/fu/CSR.scala +++ b/src/main/scala/nutcore/backend/fu/CSR.scala @@ -385,7 +385,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ // User Trap Handling // MaskedRegMap(Uscratch, uscratch), - // MaskedRegMap(Uepc, uepc), + //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use + //MaskedRegMap(Uepc, uepc, wfn = (value: UInt) => (value & ~1.U(64.W))), + // MaskedRegMap(Ucause, ucause), // MaskedRegMap(Utval, utval), // MaskedRegMap(Uip, uip), @@ -411,7 +413,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ // Supervisor Trap Handling MaskedRegMap(Sscratch, sscratch), - MaskedRegMap(Sepc, sepc), + //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use + MaskedRegMap(Sepc, sepc, wfn = (value: UInt) => (value & ~1.U(64.W))), + MaskedRegMap(Scause, scause), MaskedRegMap(Stval, stval), MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask), @@ -437,7 +441,10 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ // Machine Trap Handling MaskedRegMap(Mscratch, mscratch), - MaskedRegMap(Mepc, mepc), + //MaskedRegMap(Mepc, mepc), + //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use + MaskedRegMap(Mepc, mepc, wfn = (value: UInt) => (value & ~1.U(64.W))), + MaskedRegMap(Mcause, mcause), MaskedRegMap(Mtval, mtval), MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable), @@ -654,6 +661,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ ret := isMret || isSret || isUret trapTarget := Mux(delegS, stvec, mtvec)(VAddrBits-1, 0) + retTarget := DontCare // TODO redirect target // val illegalEret = TODO @@ -668,7 +676,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ mstatusNew.mpp := ModeU mstatus := mstatusNew.asUInt lr := false.B - retTarget := mepc(VAddrBits-1, 0) + retTarget := mepc } when (valid && isSret) { @@ -681,7 +689,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ mstatusNew.spp := ModeU mstatus := mstatusNew.asUInt lr := false.B - retTarget := sepc(VAddrBits-1, 0) + retTarget := sepc } when (valid && isUret) { @@ -692,7 +700,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ priviledgeMode := ModeU mstatusNew.pie.u := true.B mstatus := mstatusNew.asUInt - retTarget := uepc(VAddrBits-1, 0) + retTarget := uepc } when (raiseExceptionIntr) { @@ -946,3 +954,4 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ } } } + From 30fa1ca8e3ebe5ef33b13b6579d449a4b28937cd Mon Sep 17 00:00:00 2001 From: =youzi27 <=809891392@qq.com> Date: Wed, 6 Dec 2023 13:39:39 +0800 Subject: [PATCH 2/2] Fix:epc[0] value is always 0 --- src/main/scala/nutcore/backend/fu/CSR.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala index 46bd3bb1..5071af6d 100644 --- a/src/main/scala/nutcore/backend/fu/CSR.scala +++ b/src/main/scala/nutcore/backend/fu/CSR.scala @@ -661,7 +661,6 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ ret := isMret || isSret || isUret trapTarget := Mux(delegS, stvec, mtvec)(VAddrBits-1, 0) - retTarget := DontCare // TODO redirect target // val illegalEret = TODO