From 4a0b14f07ed51adbe9bd4fafc8024a04e7165180 Mon Sep 17 00:00:00 2001 From: Yangyang Zhu <68588633+DavidZyy@users.noreply.github.com> Date: Thu, 28 Dec 2023 22:37:16 +0800 Subject: [PATCH] Update Crossbar.scala Fix potential bugs that make io.in.resp.valid only valid in s_resp state. outSelRespVec is one beat slower than outSelVec, if the chosen slave in outSelRespVec return valid in one cycle, and the outSelVec is another slave, it will return the false result to master. And only ready to receive request at s_idle state make the logic more clear. --- src/main/scala/bus/simplebus/Crossbar.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/bus/simplebus/Crossbar.scala b/src/main/scala/bus/simplebus/Crossbar.scala index 815d8885..4d1a3366 100644 --- a/src/main/scala/bus/simplebus/Crossbar.scala +++ b/src/main/scala/bus/simplebus/Crossbar.scala @@ -58,7 +58,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module { } // bind out.req channel - io.in.req.ready := Mux1H(outSelVec, io.out.map(_.req.ready)) || reqInvalidAddr + io.in.req.ready := Mux1H(outSelVec, io.out.map(_.req.ready)) && state === s_idle || reqInvalidAddr for (i <- 0 until io.out.length) { io.out(i).req.valid := outSelVec(i) && io.in.req.valid && state === s_idle io.out(i).req.bits := io.in.req.bits @@ -68,7 +68,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module { for (i <- 0 until io.out.length) { io.out(i).resp.ready := outSelRespVec(i) && io.in.resp.ready && state === s_resp } - io.in.resp.valid := Mux1H(outSelRespVec, io.out.map(_.resp.valid)) || state === s_error + io.in.resp.valid := Mux1H(outSelRespVec, io.out.map(_.resp.valid)) && state === s_resp || state === s_error io.in.resp.bits := Mux1H(outSelRespVec, io.out.map(_.resp.bits)) // io.in.resp.bits.exc.get := state === s_error @@ -183,4 +183,4 @@ class SimpleBusAutoIDCrossbarNto1(n: Int, userBits: Int = 0) extends Module { } } -} \ No newline at end of file +}