diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala index 583fa532..8c717898 100644 --- a/src/test/scala/TopMain.scala +++ b/src/test/scala/TopMain.scala @@ -92,5 +92,6 @@ object TopMain extends App { (new ChiselStage).execute(newArgs, Seq(generator) ++ firtoolOptions :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog) :+ FirtoolOption("--disable-annotation-unknown") + :+ FirtoolOption("--default-layer-specialization=enable") ) } \ No newline at end of file