From 0a2cb092e52af2d5defa8c1dfea14b5a50f6bf58 Mon Sep 17 00:00:00 2001 From: klin02 Date: Sat, 8 Nov 2025 00:30:07 +0800 Subject: [PATCH 1/3] fpga_diff: expose extra IO with difftest createTopIOs --- src/main/scala/sim/NutShellSim.scala | 3 ++- src/test/scala/TopMain.scala | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala index 51b84872..b175e9b3 100644 --- a/src/main/scala/sim/NutShellSim.scala +++ b/src/main/scala/sim/NutShellSim.scala @@ -45,7 +45,8 @@ class NutShellSim extends Module with HasDiffTestInterfaces { val uart = IO(new UARTIO) uart <> mmio.io.uart - override def connectTopIOs(difftest: DifftestTopIO): Unit = { + override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = { difftest.uart <> uart + Seq.empty } } diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala index bd53e61f..4678e81a 100644 --- a/src/test/scala/TopMain.scala +++ b/src/test/scala/TopMain.scala @@ -39,9 +39,8 @@ class Top extends Module { class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces { override def desiredName: String = "NutShell" override def cpuName: Option[String] = Some("NutShell") - override def connectTopIOs(difftest: DifftestTopIO): Unit = { - val io = IO(chiselTypeOf(this.io)) - io <> this.io + override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = { + Seq(io) } } From 4bbf792d003f243a0e8a38307b08e0d152c76ed3 Mon Sep 17 00:00:00 2001 From: klin02 Date: Tue, 11 Nov 2025 16:08:33 +0800 Subject: [PATCH 2/3] feat(difftest): replace ArchReg and Writeback with PhyRegState This change refactors Difftest interfaces, replacing the previous ArchReg and WriteBack with PhyRegState and ArchRenameTable. Note when PhyReg size equals ArchReg, RenameTable can be skipped. By default, Difftest still extracts PhyReg and RenameTable into ArchReg on the hardware side, so that the extra multi-read area is accounted for within Difftest. When acceleration is enabled, this extraction is deferred to the software side, eliminating the extra hardware area overhead. --- src/main/scala/nutcore/RF.scala | 1 + .../scala/nutcore/backend/ooo/Backend.scala | 6 ++--- src/main/scala/nutcore/backend/ooo/ROB.scala | 6 ----- src/main/scala/nutcore/backend/seq/ISU.scala | 6 ++--- src/main/scala/nutcore/backend/seq/WBU.scala | 22 +++++++------------ 5 files changed, 15 insertions(+), 26 deletions(-) diff --git a/src/main/scala/nutcore/RF.scala b/src/main/scala/nutcore/RF.scala index ad47b01d..0923f199 100644 --- a/src/main/scala/nutcore/RF.scala +++ b/src/main/scala/nutcore/RF.scala @@ -29,6 +29,7 @@ trait HasRegFileParameter { class RegFile extends HasRegFileParameter with HasNutCoreParameter { val rf = Mem(NRReg, UInt(XLEN.W)) def read(addr: UInt) : UInt = Mux(addr === 0.U, 0.U, rf(addr)) + def read_all: Seq[UInt] = Seq(0.U) ++ (1 until NRReg).map { idx => rf(idx) } def write(addr: UInt, data: UInt) = { rf(addr) := data(XLEN-1,0) } } diff --git a/src/main/scala/nutcore/backend/ooo/Backend.scala b/src/main/scala/nutcore/backend/ooo/Backend.scala index 97da45fb..ac9ef6e5 100644 --- a/src/main/scala/nutcore/backend/ooo/Backend.scala +++ b/src/main/scala/nutcore/backend/ooo/Backend.scala @@ -640,9 +640,9 @@ class Backend_ooo(implicit val p: NutCoreConfig) extends NutCoreModule with HasR BoringUtils.addSource(!io.in(0).valid, "perfCntCondMdpNoInst") if (!p.FPGAPlatform || p.FPGADifftest) { - val difftest = DifftestModule(new DiffArchIntRegState) - difftest.coreid := 0.U // TODO - difftest.value := VecInit((0 to NRReg-1).map(i => rf.read(i.U))) + val difftest = DifftestModule(new DiffPhyIntRegState(NRReg)) // Size = NRREG, use as ArchIntReg + difftest.coreid := 0.U + difftest.value := VecInit(rf.read_all) } if (!p.FPGAPlatform || p.FPGADifftest) { diff --git a/src/main/scala/nutcore/backend/ooo/ROB.scala b/src/main/scala/nutcore/backend/ooo/ROB.scala index 70f279ce..4effc778 100644 --- a/src/main/scala/nutcore/backend/ooo/ROB.scala +++ b/src/main/scala/nutcore/backend/ooo/ROB.scala @@ -510,12 +510,6 @@ class ROB(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstrType difftest_commit.fpwen := false.B difftest_commit.wdest := io.wb(i).rfDest difftest_commit.wpdest := io.wb(i).rfDest - - val difftest_wb = DifftestModule(new DiffIntWriteback, delay = 1) - difftest_wb.coreid := 0.U - difftest_wb.valid := io.wb(i).rfWen && io.wb(i).rfDest =/= 0.U - difftest_wb.address := io.wb(i).rfDest - difftest_wb.data := io.wb(i).rfData } } else { BoringUtils.addSource(retireATerm, "ilaWBUvalid") diff --git a/src/main/scala/nutcore/backend/seq/ISU.scala b/src/main/scala/nutcore/backend/seq/ISU.scala index 3aaeea36..e051c492 100644 --- a/src/main/scala/nutcore/backend/seq/ISU.scala +++ b/src/main/scala/nutcore/backend/seq/ISU.scala @@ -99,8 +99,8 @@ class ISU(implicit val p: NutCoreConfig) extends NutCoreModule with HasRegFilePa BoringUtils.addSource(WireInit(io.out.fire), "perfCntCondISUIssue") if (!p.FPGAPlatform || p.FPGADifftest) { - val difftest = DifftestModule(new DiffArchIntRegState) - difftest.coreid := 0.U // TODO - difftest.value := VecInit((0 to NRReg-1).map(i => rf.read(i.U))) + val difftest = DifftestModule(new DiffPhyIntRegState(NRReg)) // Size = NRREG, use as ArchIntReg + difftest.coreid := 0.U + difftest.value := VecInit(rf.read_all) } } diff --git a/src/main/scala/nutcore/backend/seq/WBU.scala b/src/main/scala/nutcore/backend/seq/WBU.scala index 71da3532..3cdaf8bb 100644 --- a/src/main/scala/nutcore/backend/seq/WBU.scala +++ b/src/main/scala/nutcore/backend/seq/WBU.scala @@ -1,17 +1,17 @@ /************************************************************************************** * Copyright (c) 2020 Institute of Computing Technology, CAS * Copyright (c) 2020 University of Chinese Academy of Sciences -* +* * NutShell is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. * You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR -* FIT FOR A PARTICULAR PURPOSE. +* http://license.coscl.org.cn/MulanPSL2 +* +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +* FIT FOR A PARTICULAR PURPOSE. * -* See the Mulan PSL v2 for more details. +* See the Mulan PSL v2 for more details. ***************************************************************************************/ package nutcore @@ -57,12 +57,6 @@ class WBU(implicit val p: NutCoreConfig) extends NutCoreModule{ difftest_commit.fpwen := false.B difftest_commit.wdest := io.wb.rfDest difftest_commit.wpdest := io.wb.rfDest - - val difftest_wb = DifftestModule(new DiffIntWriteback, delay = 1) - difftest_wb.coreid := 0.U - difftest_wb.valid := io.wb.rfWen && io.wb.rfDest =/= 0.U - difftest_wb.address := io.wb.rfDest - difftest_wb.data := io.wb.rfData } else { BoringUtils.addSource(io.in.valid, "ilaWBUvalid") BoringUtils.addSource(io.in.bits.decode.cf.pc, "ilaWBUpc") From 43ef0b923c68312eaece100b8c3e64f635f59ebb Mon Sep 17 00:00:00 2001 From: klin02 Date: Wed, 12 Nov 2025 23:08:50 +0800 Subject: [PATCH 3/3] bump difftest --- difftest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/difftest b/difftest index 3cb2104b..43a308e8 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 3cb2104b27d12b8da5888075544db88613eda714 +Subproject commit 43a308e89ae28dfb52425c26e6995c7db2291daa