diff --git a/README.md b/README.md index 9263f44e..18f2695c 100644 --- a/README.md +++ b/README.md @@ -43,4 +43,25 @@ openmotordrive/framework is a framework for embedded applications, primarily tar |uavcan_restart|Provides a uavcan.protocol.RestartNode server| |worker_thread|Provides worker threads that can process timer tasks, which run after a delay, or listener tasks, which listen to pubsub messages| +## REQUIREMENTS +Some installations requirements and help. + +### Submodules : +After cloning, get the submodules with : + +```bash +git submodule update --init --recursive +``` + +### Toolchain : +Tested with gcc6 and gcc7 + +On Ubuntu 16.04, you can use [team-gcc-arm-embedded](https://launchpad.net/~team-gcc-arm-embedded/+archive/ubuntu/ppa) version + +### Others +It needs crcmod and uavcan python package + +```bash +sudo pip install -U crcmod uavcan +``` diff --git a/examples/basic_uavcan_functionality/README.md b/examples/basic_uavcan_functionality/README.md new file mode 100644 index 00000000..60b40c65 --- /dev/null +++ b/examples/basic_uavcan_functionality/README.md @@ -0,0 +1,8 @@ +## Usage +Set BOARD_DIR according to you board directory. + +### Example + +```bash +BOARD_DIR=boards/com.hex.cube_1.0 make +``` diff --git a/examples/basic_uavcan_functionality/boards/org.proficnc.uwb_1.0/board.h b/examples/basic_uavcan_functionality/boards/org.proficnc.uwb_1.0/board.h index 2276d31c..2cbd4a60 100644 --- a/examples/basic_uavcan_functionality/boards/org.proficnc.uwb_1.0/board.h +++ b/examples/basic_uavcan_functionality/boards/org.proficnc.uwb_1.0/board.h @@ -3,6 +3,18 @@ #include #include +#define BOARD_CONFIG_HW_NAME "org.proficnc.uwb" +#define BOARD_CONFIG_HW_MAJOR_VER 1 +#define BOARD_CONFIG_HW_MINOR_VER 0 + +#define BOARD_CONFIG_HW_INFO_STRUCTURE { \ + .hw_name = BOARD_CONFIG_HW_NAME, \ + .hw_major_version = BOARD_CONFIG_HW_MAJOR_VER, \ + .hw_minor_version = BOARD_CONFIG_HW_MINOR_VER, \ + .board_desc_fmt = SHARED_HW_INFO_BOARD_DESC_FMT_NONE, \ + .board_desc = 0, \ +} + #define BOARD_PAL_LINE_SPI_SCK PAL_LINE(GPIOB,3) #define BOARD_PAL_LINE_SPI_MISO PAL_LINE(GPIOB,4) #define BOARD_PAL_LINE_SPI_MOSI PAL_LINE(GPIOB,5) diff --git a/examples/basic_uwb_functionality/.cproject b/examples/basic_uwb_functionality/.cproject new file mode 100644 index 00000000..90475ef4 --- /dev/null +++ b/examples/basic_uwb_functionality/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/basic_uwb_functionality/.gitignore b/examples/basic_uwb_functionality/.gitignore new file mode 100644 index 00000000..7a0bbe9e --- /dev/null +++ b/examples/basic_uwb_functionality/.gitignore @@ -0,0 +1,2 @@ +build +.dep diff --git a/examples/basic_uwb_functionality/.project b/examples/basic_uwb_functionality/.project new file mode 100644 index 00000000..4c434ef7 --- /dev/null +++ b/examples/basic_uwb_functionality/.project @@ -0,0 +1,90 @@ + + + usb + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/examples/basic_uwb_functionality/Makefile b/examples/basic_uwb_functionality/Makefile new file mode 100755 index 00000000..65913169 --- /dev/null +++ b/examples/basic_uwb_functionality/Makefile @@ -0,0 +1,27 @@ +CSRC = $(shell find src -name "*.c") +INCDIR = ./include + +MODULES_ENABLED = \ +chibios_sys_init \ +chibios_hal_init \ +app_descriptor \ +boot_msg \ +timing \ +system \ +pubsub \ +worker_thread \ +can_driver_stm32 \ +can \ +can_autobaud \ +uavcan \ +uavcan_nodestatus_publisher \ +uavcan_getnodeinfo_server \ +uavcan_beginfirmwareupdate_server \ +uavcan_allocatee \ +uavcan_restart \ +freemem_check + +MESSAGES_ENABLED = \ +uavcan.protocol.debug.LogMessage + +include ../../include.mk diff --git a/examples/basic_uwb_functionality/README.md b/examples/basic_uwb_functionality/README.md new file mode 100644 index 00000000..60b40c65 --- /dev/null +++ b/examples/basic_uwb_functionality/README.md @@ -0,0 +1,8 @@ +## Usage +Set BOARD_DIR according to you board directory. + +### Example + +```bash +BOARD_DIR=boards/com.hex.cube_1.0 make +``` diff --git a/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.c b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.c new file mode 100644 index 00000000..7e7bf043 --- /dev/null +++ b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.c @@ -0,0 +1,25 @@ +#include + +void boardInit(void) { + palSetLineMode(BOARD_PAL_LINE_SPI_SCK, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_PULLDOWN); // SPI3 SCK + palSetLineMode(BOARD_PAL_LINE_SPI_MISO, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // SPI3 MISO + palSetLineMode(BOARD_PAL_LINE_SPI_MOSI, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // SPI3 MOSI + palSetLineMode(BOARD_PAL_LINE_SPI_UWB_CS, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // UWB CS + palSetLineMode(PAL_LINE(GPIOB, 6), PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // TEST POINT 1 + palSetLineMode(PAL_LINE(GPIOB, 7), PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // TEST POINT 2 + palSetLineMode(BOARD_PAL_LINE_UWB_IRQ, PAL_STM32_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_PULLDOWN); // UWB IRQ + palSetLineMode(BOARD_PAL_LINE_CAN_RX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); + palSetLineMode(BOARD_PAL_LINE_CAN_TX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); + + palSetLineMode(LINE_UART2_RTS, PAL_MODE_ALTERNATE(7) | PAL_STM32_OSPEED_LOWEST | PAL_STM32_PUPDR_PULLUP); + palSetLineMode(LINE_UART2_CTS, PAL_MODE_ALTERNATE(7) | PAL_STM32_OSPEED_LOWEST | PAL_STM32_PUPDR_PULLUP); + palSetLineMode(LINE_UART2_RX, PAL_MODE_ALTERNATE(7) | PAL_STM32_OSPEED_LOWEST | PAL_STM32_PUPDR_PULLUP); + palSetLineMode(LINE_UART2_TX, PAL_MODE_ALTERNATE(7) | PAL_STM32_OSPEED_LOWEST | PAL_STM32_PUPDR_PULLUP); + + //palSetLineMode(LINE_OTG_HS_VBUS, PAL_MODE_ALTERNATE(10) | PAL_STM32_OSPEED_LOWEST | PAL_STM32_PUPDR_PULLDOWN); + //palSetLineMode(LINE_OTG_HS_DM, PAL_MODE_ALTERNATE(10) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING); + // palSetLineMode(LINE_OTG_HS_DP, PAL_MODE_ALTERNATE(10) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING); + palSetLineMode(LINE_SWDIO, PAL_MODE_ALTERNATE(0) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_PULLUP); + palSetLineMode(LINE_SWCLK, PAL_MODE_ALTERNATE(0) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_PULLDOWN); + +} \ No newline at end of file diff --git a/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.h b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.h new file mode 100644 index 00000000..fd0264a5 --- /dev/null +++ b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.h @@ -0,0 +1,63 @@ +#pragma once + +#include +#include + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 24000000U +#endif + +#define STM32F401xC +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330U + +#define BOARD_CONFIG_HW_NAME "org.skt.uwb" +#define BOARD_CONFIG_HW_MAJOR_VER 1 +#define BOARD_CONFIG_HW_MINOR_VER 0 + +#define BOARD_CONFIG_HW_INFO_STRUCTURE { \ + .hw_name = BOARD_CONFIG_HW_NAME, \ + .hw_major_version = BOARD_CONFIG_HW_MAJOR_VER, \ + .hw_minor_version = BOARD_CONFIG_HW_MINOR_VER, \ + .board_desc_fmt = SHARED_HW_INFO_BOARD_DESC_FMT_NONE, \ + .board_desc = 0, \ +} + +#define BOARD_PAL_LINE_SPI_SCK PAL_LINE(GPIOB,3) +#define BOARD_PAL_LINE_SPI_MISO PAL_LINE(GPIOB,4) +#define BOARD_PAL_LINE_SPI_MOSI PAL_LINE(GPIOB,5) +#define BOARD_PAL_LINE_SPI_UWB_CS PAL_LINE(GPIOA,15) // NOTE: never drive high by external source +#define BOARD_PAL_LINE_UWB_NRST PAL_LINE(GPIOB,8) +#define BOARD_PAL_LINE_UWB_IRQ PAL_LINE(GPIOB,12) +#define BOARD_PAL_LINE_CAN_RX PAL_LINE(GPIOB,6) +#define BOARD_PAL_LINE_CAN_TX PAL_LINE(GPIOB,7) +#define DW1000_SPI_BUS 3 + +#define SERIAL_DEFAULT_BITRATE 57600 + +/* + * IO pins assignments. + */ + +#define LINE_UART2_RTS PAL_LINE(GPIOA, 0U) +#define LINE_UART2_CTS PAL_LINE(GPIOA, 1U) +#define LINE_UART2_RX PAL_LINE(GPIOA, 2U) +#define LINE_UART2_TX PAL_LINE(GPIOA, 3U) + +#define LINE_OTG_HS_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_OTG_HS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_HS_DP PAL_LINE(GPIOA, 12U) + +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) diff --git a/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.mk b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.mk new file mode 100644 index 00000000..e57a4e04 --- /dev/null +++ b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/board.mk @@ -0,0 +1,4 @@ +BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) +BOARD_SRC = $(BOARD_DIR)/board.c +BOARD_INC = $(BOARD_DIR) +MODULES_ENABLED += platform_stm32f401 diff --git a/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/mcuconf.h b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/mcuconf.h new file mode 100644 index 00000000..904ae56c --- /dev/null +++ b/examples/basic_uwb_functionality/boards/org.skt.uwb_1.0/mcuconf.h @@ -0,0 +1,78 @@ +#pragma once + +#define STM32F4xx_MCUCONF + +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_HSI // Main clock source selection. +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK + +#define STM32_RTCSEL STM32_RTCSEL_LSI + +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 \ No newline at end of file diff --git a/examples/basic_uwb_functionality/debug/uwb (OpenOCD, Flash and Run).launch b/examples/basic_uwb_functionality/debug/uwb (OpenOCD, Flash and Run).launch new file mode 100644 index 00000000..758801e8 --- /dev/null +++ b/examples/basic_uwb_functionality/debug/uwb (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/basic_uwb_functionality/include/app_config.h b/examples/basic_uwb_functionality/include/app_config.h new file mode 100644 index 00000000..6d5e357f --- /dev/null +++ b/examples/basic_uwb_functionality/include/app_config.h @@ -0,0 +1,9 @@ +#pragma once + +#define APP_CONFIG_BOOT_DELAY_SEC 0 +#define APP_CONFIG_CAN_DEFAULT_BAUDRATE 1000000 +#define APP_CONFIG_CAN_LOCAL_NODE_ID 0 +#define APP_CONFIG_CAN_AUTO_BAUD_ENABLE 0 + +#define SHARED_APP_DESCRIPTOR_MAJOR_VERSION 1 +#define SHARED_APP_DESCRIPTOR_MINOR_VERSION 0 diff --git a/examples/basic_uwb_functionality/include/framework_conf.h b/examples/basic_uwb_functionality/include/framework_conf.h new file mode 100644 index 00000000..53b00d00 --- /dev/null +++ b/examples/basic_uwb_functionality/include/framework_conf.h @@ -0,0 +1,47 @@ +#pragma once + +// +// Configure worker threads +// +#define HAL_USE_SERIAL TRUE + +#define TIMING_WORKER_THREAD lpwork_thread +#define UAVCAN_NODESTATUS_PUBLISHER_WORKER_THREAD lpwork_thread +#define CAN_AUTOBAUD_WORKER_THREAD lpwork_thread +#define UAVCAN_PARAM_INTERFACE_WORKER_THREAD lpwork_thread +#define UAVCAN_GETNODEINFO_SERVER_WORKER_THREAD lpwork_thread +#define UAVCAN_RESTART_WORKER_THREAD lpwork_thread +#define UAVCAN_BEGINFIRMWAREUPDATE_SERVER_WORKER_THREAD lpwork_thread +#define UAVCAN_ALLOCATEE_WORKER_THREAD lpwork_thread +#define PIN_CHANGE_PUBLISHER_WORKER_THREAD lpwork_thread + +#define CAN_TRX_WORKER_THREAD can_thread +#define CAN_EXPIRE_WORKER_THREAD can_thread +#define UAVCAN_RX_WORKER_THREAD can_thread + +// +// Configure topic groups +// + +#define PUBSUB_DEFAULT_TOPIC_GROUP default_topic_group + +// +// Misc configs +// + +#define REQUIRED_RAM_MARGIN_AFTER_INIT 512 + +// +// Configure debug checks +// + +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_STACK_CHECK TRUE + +#define CH_CFG_USE_EVENTS TRUE +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#define CH_CFG_USE_HEAP TRUE + +#define SHELL_CMD_TEST_ENABLED FALSE diff --git a/examples/basic_uwb_functionality/openocd.cfg b/examples/basic_uwb_functionality/openocd.cfg new file mode 100644 index 00000000..7101d263 --- /dev/null +++ b/examples/basic_uwb_functionality/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink-v2-1.cfg] +source [find target/stm32f4x.cfg] +init +reset halt +$_TARGETNAME configure -rtos ChibiOS diff --git a/examples/basic_uwb_functionality/src/setup.c b/examples/basic_uwb_functionality/src/setup.c new file mode 100644 index 00000000..53ad7f5d --- /dev/null +++ b/examples/basic_uwb_functionality/src/setup.c @@ -0,0 +1,8 @@ +#include +#include + +WORKER_THREAD_TAKEOVER_MAIN(lpwork_thread, LOWPRIO) +WORKER_THREAD_SPAWN(can_thread, LOWPRIO, 1024) +WORKER_THREAD_SPAWN(hpwork_thread, HIGHPRIO, 1024) + +PUBSUB_TOPIC_GROUP_CREATE(default_topic_group, 1024) diff --git a/examples/basic_uwb_functionality/src/usb_test.c b/examples/basic_uwb_functionality/src/usb_test.c new file mode 100644 index 00000000..93c4dfb2 --- /dev/null +++ b/examples/basic_uwb_functionality/src/usb_test.c @@ -0,0 +1,93 @@ +#include + +#include + +#include + +#include +#include +#include +#include /* atoi */ + + +#define WT hpwork_thread +WORKER_THREAD_DECLARE_EXTERN(WT) + +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (true) { + chprintf((BaseSequentialStream *)&SD2, "plop [%d]\r\n", (unsigned long)chVTGetSystemTime()); + chThdSleepMilliseconds(1000); + } +} + +// handle request to change blink speed on green led +void cmd_blinkspeed(BaseSequentialStream *chp, int argc, char *argv[]) { + + (void)argv; + uint16_t millis = 500; + if (argc != 1) { + chprintf(chp, "Usage: blinkspeed speed [ms]\r\n"); + return; + } + millis = atoi(argv[0]); + chprintf(chp, "Got speed [%d]\r\n", millis); // TODO : add UAVCAN Debug + +} + +static const ShellCommand commands[] = { + {"blinkspeed", cmd_blinkspeed} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static THD_WORKING_AREA(waShellThread, 2048); +static THD_FUNCTION(ShellThread, arg) { + (void)arg; + chRegSetThreadName("shellthread"); + while (true) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } +} + +// Init the USB +void usb_init(void) { + sdStart(&SD2, NULL); + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + // usbDisconnectBus(serusbcfg.usbp); + // chThdSleepMilliseconds(1500); + // usbStart(serusbcfg.usbp, &usbcfg); + // usbConnectBus(serusbcfg.usbp); + /* + * Shell manager initialization. + */ + shellInit(); + chThdCreateStatic(waShellThread, sizeof(waShellThread), NORMALPRIO+1, + ShellThread, NULL); + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO + 10, Thread1, NULL); + +} + +// Function call after the end of init +RUN_AFTER(INIT_END) { + usb_init(); + // Add new tasks to worker thread + // make led blink and report every 1000ms (repeated) +} diff --git a/examples/driver_invensense/README.md b/examples/driver_invensense/README.md new file mode 100644 index 00000000..60b40c65 --- /dev/null +++ b/examples/driver_invensense/README.md @@ -0,0 +1,8 @@ +## Usage +Set BOARD_DIR according to you board directory. + +### Example + +```bash +BOARD_DIR=boards/com.hex.cube_1.0 make +``` diff --git a/examples/driver_invensense/boards/com.hex.flow_1.0/board.h b/examples/driver_invensense/boards/com.hex.flow_1.0/board.h index 0f5ad357..4bd593ee 100644 --- a/examples/driver_invensense/boards/com.hex.flow_1.0/board.h +++ b/examples/driver_invensense/boards/com.hex.flow_1.0/board.h @@ -2,6 +2,19 @@ #include + +#define BOARD_CONFIG_HW_NAME "org.proficnc.flow" +#define BOARD_CONFIG_HW_MAJOR_VER 1 +#define BOARD_CONFIG_HW_MINOR_VER 0 + +#define BOARD_CONFIG_HW_INFO_STRUCTURE { \ + .hw_name = BOARD_CONFIG_HW_NAME, \ + .hw_major_version = BOARD_CONFIG_HW_MAJOR_VER, \ + .hw_minor_version = BOARD_CONFIG_HW_MINOR_VER, \ + .board_desc_fmt = SHARED_HW_INFO_BOARD_DESC_FMT_NONE, \ + .board_desc = 0, \ +} + #define BOARD_PAL_LINE_SPI3_SCK PAL_LINE(GPIOB,3) #define BOARD_PAL_LINE_SPI3_MISO PAL_LINE(GPIOB,4) #define BOARD_PAL_LINE_SPI3_MOSI PAL_LINE(GPIOB,5) diff --git a/examples/driver_usb/.gitignore b/examples/driver_usb/.gitignore new file mode 100644 index 00000000..7a0bbe9e --- /dev/null +++ b/examples/driver_usb/.gitignore @@ -0,0 +1,2 @@ +build +.dep diff --git a/examples/driver_usb/Makefile b/examples/driver_usb/Makefile new file mode 100755 index 00000000..4d027704 --- /dev/null +++ b/examples/driver_usb/Makefile @@ -0,0 +1,28 @@ +CSRC = $(shell find src -name "*.c") +INCDIR = ./include + +MODULES_ENABLED = \ +chibios_sys_init \ +chibios_hal_init \ +app_descriptor \ +boot_msg \ +timing \ +system \ +pubsub \ +worker_thread \ +can_driver_stm32 \ +can \ +can_autobaud \ +uavcan \ +uavcan_nodestatus_publisher \ +uavcan_getnodeinfo_server \ +uavcan_beginfirmwareupdate_server \ +uavcan_allocatee \ +uavcan_restart \ +uavcan_debug \ +freemem_check + +MESSAGES_ENABLED = \ +uavcan.protocol.debug.LogMessage + +include ../../include.mk diff --git a/examples/driver_usb/README.md b/examples/driver_usb/README.md new file mode 100644 index 00000000..0daf871a --- /dev/null +++ b/examples/driver_usb/README.md @@ -0,0 +1,41 @@ +## Usage +Set BOARD_DIR according to you board directory. + +### Example + +```bash +BOARD_DIR=boards/com.hex.cube_1.0 make +``` +init the gpio used in board init , the auto initialisation from chibios as been removed to save flash + +Add a new board type : +Add new platform in modules/platform_YOURBOARDNAME +Add new platform in platforms/ARMCMx/ld/YOURBOARDNAME + +modify : + - boards/XXX/mcuconf.h + - boards/XXX/board.mk + - boards/XXX/board.h + + +Modify Makefile for include etc. +program file to compile go to src. + +Modify framework_conf.h for framework or chibios configuration +Modify MCU config in boards / XXXX/ mcuconf.h + + +openocd : +config +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only +// end config + +reset halt + +flash write_image erase /home/pierre/Workspace/framework/examples/driver_usb/build/com.skt.usb_1.0/driver_usb.elf \ No newline at end of file diff --git a/examples/driver_usb/boards/com.skt.usb_1.0/board.c b/examples/driver_usb/boards/com.skt.usb_1.0/board.c new file mode 100644 index 00000000..4a8a5e81 --- /dev/null +++ b/examples/driver_usb/boards/com.skt.usb_1.0/board.c @@ -0,0 +1,57 @@ +#include + + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +void boardInit(void) { + palSetLineMode(BOARD_PAL_LINE_CAN_RX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); + palSetLineMode(BOARD_PAL_LINE_CAN_TX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); + + palSetLineMode(BOARD_PAL_LINE_RED_LED, PAL_STM32_MODE_OUTPUT | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING); + + palSetLineMode(BOARD_PAL_LINE_GREEN_LED, PAL_STM32_MODE_OUTPUT | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING); +} diff --git a/examples/driver_usb/boards/com.skt.usb_1.0/board.h b/examples/driver_usb/boards/com.skt.usb_1.0/board.h new file mode 100644 index 00000000..0fa5d1e4 --- /dev/null +++ b/examples/driver_usb/boards/com.skt.usb_1.0/board.h @@ -0,0 +1,1383 @@ +#pragma once + +#include +#include + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U +/* + * MCU type as defined in the ST header. + */ +#define STM32F429xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_MEMS_INT1 1U +#define GPIOA_MEMS_INT2 2U +#define GPIOA_LCD_B5 3U +#define GPIOA_LCD_VSYNC 4U +#define GPIOA_PIN5 5U +#define GPIOA_LCD_G2 6U +#define GPIOA_ACP_RST 7U +#define GPIOA_I2C3_SCL 8U +#define GPIOA_UART_TX 9U +#define GPIOA_UART_RX 10U +#define GPIOA_LCD_R4 11U +#define GPIOA_LCD_R5 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_TP_INT 15U + +#define GPIOB_LCD_R3 0U +#define GPIOB_LCD_R6 1U +#define GPIOB_BOOT1 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_FMC_SDCKE1 5U +#define GPIOB_FMC_SDNE1 6U +#define GPIOB_PIN7 7U +#define GPIOB_LCD_B6 8U +#define GPIOB_LCD_B7 9U +#define GPIOB_LCD_G4 10U +#define GPIOB_LCD_G5 11U +#define GPIOB_OTG_HS_ID 12U +#define GPIOB_OTG_HS_VBUS 13U +#define GPIOB_OTG_HS_DM 14U +#define GPIOB_OTG_HS_DP 15U + +#define GPIOC_FMC_SDNWE 0U +#define GPIOC_SPI5_MEMS_CS 1U +#define GPIOC_SPI5_LCD_CS 2U +#define GPIOC_PIN3 3U +#define GPIOC_OTG_HS_PSO 4U +#define GPIOC_OTG_HS_OC 5U +#define GPIOC_LCD_HSYNC 6U +#define GPIOC_LCD_G6 7U +#define GPIOC_PIN8 8U +#define GPIOC_I2C3_SDA 9U +#define GPIOC_LCD_R2 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_FMC_D2 0U +#define GPIOD_FMC_D3 1U +#define GPIOD_PIN2 2U +#define GPIOD_LCD_G7 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_LCD_B2 6U +#define GPIOD_PIN7 7U +#define GPIOD_FMC_D13 8U +#define GPIOD_FMC_D14 9U +#define GPIOD_FMC_D15 10U +#define GPIOD_LCD_TE 11U +#define GPIOD_LCD_RDX 12U +#define GPIOD_LCD_WRX 13U +#define GPIOD_FMC_D0 14U +#define GPIOD_FMC_D1 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_FMC_D4 7U +#define GPIOE_FMC_D5 8U +#define GPIOE_FMC_D6 9U +#define GPIOE_FMC_D7 10U +#define GPIOE_FMC_D8 11U +#define GPIOE_FMC_D9 12U +#define GPIOE_FMC_D10 13U +#define GPIOE_FMC_D11 14U +#define GPIOE_FMC_D12 15U + +#define GPIOF_FMC_A0 0U +#define GPIOF_FMC_A1 1U +#define GPIOF_FMC_A2 2U +#define GPIOF_FMC_A3 3U +#define GPIOF_FMC_A4 4U +#define GPIOF_FMC_A5 5U +#define GPIOF_PIN6 6U +#define GPIOF_LCD_DCX 7U +#define GPIOF_SPI5_MISO 8U +#define GPIOF_SPI5_MOSI 9U +#define GPIOF_LCD_DE 10U +#define GPIOF_FMC_SDNRAS 11U +#define GPIOF_FMC_A6 12U +#define GPIOF_FMC_A7 13U +#define GPIOF_FMC_A8 14U +#define GPIOF_FMC_A9 15U + +#define GPIOG_FMC_A10 0U +#define GPIOG_FMC_A11 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_FMC_BA0 4U +#define GPIOG_FMC_BA1 5U +#define GPIOG_LCD_R7 6U +#define GPIOG_LCD_CLK 7U +#define GPIOG_FMC_SDCLK 8U +#define GPIOG_PIN9 9U +#define GPIOG_LCD_G3 10U +#define GPIOG_LCD_B3 11U +#define GPIOG_LCD_B4 12U +#define GPIOG_LED3_GREEN 13U +#define GPIOG_LED4_RED 14U +#define GPIOG_FMC_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_MEMS_INT1 PAL_LINE(GPIOA, 1U) +#define LINE_MEMS_INT2 PAL_LINE(GPIOA, 2U) +#define LINE_LCD_B5 PAL_LINE(GPIOA, 3U) +#define LINE_LCD_VSYNC PAL_LINE(GPIOA, 4U) +#define LINE_LCD_G2 PAL_LINE(GPIOA, 6U) +#define LINE_ACP_RST PAL_LINE(GPIOA, 7U) +#define LINE_I2C3_SCL PAL_LINE(GPIOA, 8U) +#define LINE_UART_TX PAL_LINE(GPIOA, 9U) +#define LINE_UART_RX PAL_LINE(GPIOA, 10U) +#define LINE_LCD_R4 PAL_LINE(GPIOA, 11U) +#define LINE_LCD_R5 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_TP_INT PAL_LINE(GPIOA, 15U) + +#define LINE_LCD_R3 PAL_LINE(GPIOB, 0U) +#define LINE_LCD_R6 PAL_LINE(GPIOB, 1U) +#define LINE_BOOT1 PAL_LINE(GPIOB, 2U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_FMC_SDCKE1 PAL_LINE(GPIOB, 5U) +#define LINE_FMC_SDNE1 PAL_LINE(GPIOB, 6U) +#define LINE_LCD_B6 PAL_LINE(GPIOB, 8U) +#define LINE_LCD_B7 PAL_LINE(GPIOB, 9U) +#define LINE_LCD_G4 PAL_LINE(GPIOB, 10U) +#define LINE_LCD_G5 PAL_LINE(GPIOB, 11U) +#define LINE_OTG_HS_ID PAL_LINE(GPIOB, 12U) +#define LINE_OTG_HS_VBUS PAL_LINE(GPIOB, 13U) +#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U) +#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U) + +#define LINE_FMC_SDNWE PAL_LINE(GPIOC, 0U) +#define LINE_SPI5_MEMS_CS PAL_LINE(GPIOC, 1U) +#define LINE_SPI5_LCD_CS PAL_LINE(GPIOC, 2U) +#define LINE_OTG_HS_PSO PAL_LINE(GPIOC, 4U) +#define LINE_OTG_HS_OC PAL_LINE(GPIOC, 5U) +#define LINE_LCD_HSYNC PAL_LINE(GPIOC, 6U) +#define LINE_LCD_G6 PAL_LINE(GPIOC, 7U) +#define LINE_I2C3_SDA PAL_LINE(GPIOC, 9U) +#define LINE_LCD_R2 PAL_LINE(GPIOC, 10U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) +#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) +#define LINE_LCD_G7 PAL_LINE(GPIOD, 3U) +#define LINE_LCD_B2 PAL_LINE(GPIOD, 6U) +#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) +#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) +#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) +#define LINE_LCD_TE PAL_LINE(GPIOD, 11U) +#define LINE_LCD_RDX PAL_LINE(GPIOD, 12U) +#define LINE_LCD_WRX PAL_LINE(GPIOD, 13U) +#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) +#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) + +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) +#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) +#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) +#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) +#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) +#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) +#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) +#define LINE_FMC_D11 PAL_LINE(GPIOE, 14U) +#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) + +#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) +#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) +#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) +#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) +#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) +#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) +#define LINE_LCD_DCX PAL_LINE(GPIOF, 7U) +#define LINE_SPI5_MISO PAL_LINE(GPIOF, 8U) +#define LINE_SPI5_MOSI PAL_LINE(GPIOF, 9U) +#define LINE_LCD_DE PAL_LINE(GPIOF, 10U) +#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) +#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) +#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) +#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) + +#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) +#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) +#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_LCD_R7 PAL_LINE(GPIOG, 6U) +#define LINE_LCD_CLK PAL_LINE(GPIOG, 7U) +#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_LCD_G3 PAL_LINE(GPIOG, 10U) +#define LINE_LCD_B3 PAL_LINE(GPIOG, 11U) +#define LINE_LCD_B4 PAL_LINE(GPIOG, 12U) +#define LINE_LED3_GREEN PAL_LINE(GPIOG, 13U) +#define LINE_LED4_RED PAL_LINE(GPIOG, 14U) +#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - MEMS_INT1 (input floating). + * PA2 - MEMS_INT2 (input floating). + * PA3 - LCD_B5 (alternate 14). + * PA4 - LCD_VSYNC (alternate 14). + * PA5 - PIN5 (input pullup). + * PA6 - LCD_G2 (alternate 14). + * PA7 - ACP_RST (input pullup). + * PA8 - I2C3_SCL (alternate 4). + * PA9 - UART_TX (alternate 7). + * PA10 - UART_RX (alternate 7). + * PA11 - LCD_R4 (alternate 14). + * PA12 - LCD_R5 (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - TP_INT (input floating). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT1) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT2) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_B5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_VSYNC) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \ + PIN_MODE_INPUT(GPIOA_ACP_RST) | \ + PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R4) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R5) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_TP_INT)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_B5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_VSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \ + PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_TP_INT)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT1) | \ + PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT2) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_B5) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_VSYNC) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_G2) | \ + PIN_OSPEED_VERYLOW(GPIOA_ACP_RST) | \ + PIN_OSPEED_HIGH(GPIOA_I2C3_SCL) | \ + PIN_OSPEED_VERYLOW(GPIOA_UART_TX) | \ + PIN_OSPEED_VERYLOW(GPIOA_UART_RX) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_R4) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_R5) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_VERYLOW(GPIOA_TP_INT)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT1) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT2) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_B5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_VSYNC) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \ + PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_TX) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_RX) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R4) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R5) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_TP_INT)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT1) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT2) | \ + PIN_ODR_HIGH(GPIOA_LCD_B5) | \ + PIN_ODR_HIGH(GPIOA_LCD_VSYNC) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_LCD_G2) | \ + PIN_ODR_HIGH(GPIOA_ACP_RST) | \ + PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \ + PIN_ODR_HIGH(GPIOA_UART_TX) | \ + PIN_ODR_HIGH(GPIOA_UART_RX) | \ + PIN_ODR_HIGH(GPIOA_LCD_R4) | \ + PIN_ODR_HIGH(GPIOA_LCD_R5) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_TP_INT)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT1, 0U) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT2, 0U) | \ + PIN_AFIO_AF(GPIOA_LCD_B5, 14U) | \ + PIN_AFIO_AF(GPIOA_LCD_VSYNC, 14U) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOA_LCD_G2, 14U) | \ + PIN_AFIO_AF(GPIOA_ACP_RST, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4U) | \ + PIN_AFIO_AF(GPIOA_UART_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_UART_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_LCD_R4, 14U) | \ + PIN_AFIO_AF(GPIOA_LCD_R5, 14U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_TP_INT, 0U)) + +/* + * GPIOB setup: + * + * PB0 - LCD_R3 (alternate 14). + * PB1 - LCD_R6 (alternate 14). + * PB2 - BOOT1 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - FMC_SDCKE1 (alternate 12). + * PB6 - FMC_SDNE1 (alternate 12). + * PB7 - PIN7 (input pullup). + * PB8 - LCD_B6 (alternate 14). + * PB9 - LCD_B7 (alternate 14). + * PB10 - LCD_G4 (alternate 14). + * PB11 - LCD_G5 (alternate 14). + * PB12 - OTG_HS_ID (alternate 12). + * PB13 - OTG_HS_VBUS (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_LCD_R3) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_R6) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDCKE1) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDNE1) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B6) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G4) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G5) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_R3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_R6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDCKE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDNE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LCD_R3) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_R6) | \ + PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_FMC_SDCKE1) | \ + PIN_OSPEED_HIGH(GPIOB_FMC_SDNE1) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_B6) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_B7) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_G4) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_G5) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_OSPEED_VERYLOW(GPIOB_OTG_HS_VBUS) |\ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_R3) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_R6) | \ + PIN_PUPDR_PULLUP(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDCKE1) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDNE1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B6) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G4) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G5) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ + PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_R3) | \ + PIN_ODR_HIGH(GPIOB_LCD_R6) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDCKE1) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDNE1) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_LCD_B6) | \ + PIN_ODR_HIGH(GPIOB_LCD_B7) | \ + PIN_ODR_HIGH(GPIOB_LCD_G4) | \ + PIN_ODR_HIGH(GPIOB_LCD_G5) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_R3, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_R6, 14U) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_FMC_SDCKE1, 12U) | \ + PIN_AFIO_AF(GPIOB_FMC_SDNE1, 12U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_LCD_B6, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_B7, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_G4, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_G5, 14U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U)) + +/* + * GPIOC setup: + * + * PC0 - FMC_SDNWE (alternate 12). + * PC1 - SPI5_MEMS_CS (output pushpull maximum). + * PC2 - SPI5_LCD_CS (output pushpull maximum). + * PC3 - PIN3 (input pullup). + * PC4 - OTG_HS_PSO (output pushpull maximum). + * PC5 - OTG_HS_OC (input floating). + * PC6 - LCD_HSYNC (alternate 14). + * PC7 - LCD_G6 (alternate 14). + * PC8 - PIN8 (input pullup). + * PC9 - I2C3_SDA (alternate 4). + * PC10 - LCD_R2 (alternate 14). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_FMC_SDNWE) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_MEMS_CS) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_LCD_CS) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_OUTPUT(GPIOC_OTG_HS_PSO) | \ + PIN_MODE_INPUT(GPIOC_OTG_HS_OC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_HSYNC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_G6) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_R2) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_MEMS_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_LCD_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_PSO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_OC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_HSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_G6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_I2C3_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_R2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_FMC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOC_SPI5_MEMS_CS) | \ + PIN_OSPEED_HIGH(GPIOC_SPI5_LCD_CS) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_OTG_HS_PSO) | \ + PIN_OSPEED_HIGH(GPIOC_OTG_HS_OC) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_HSYNC) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_G6) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_I2C3_SDA) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_R2) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_FMC_SDNWE) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI5_MEMS_CS) |\ + PIN_PUPDR_FLOATING(GPIOC_SPI5_LCD_CS) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_PSO) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_OC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_HSYNC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_G6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_R2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOC_SPI5_MEMS_CS) | \ + PIN_ODR_HIGH(GPIOC_SPI5_LCD_CS) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_PSO) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_OC) | \ + PIN_ODR_HIGH(GPIOC_LCD_HSYNC) | \ + PIN_ODR_HIGH(GPIOC_LCD_G6) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_I2C3_SDA) | \ + PIN_ODR_HIGH(GPIOC_LCD_R2) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_FMC_SDNWE, 12U) | \ + PIN_AFIO_AF(GPIOC_SPI5_MEMS_CS, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI5_LCD_CS, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_PSO, 0U) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_OC, 0U) | \ + PIN_AFIO_AF(GPIOC_LCD_HSYNC, 14U) | \ + PIN_AFIO_AF(GPIOC_LCD_G6, 14U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_I2C3_SDA, 4U) | \ + PIN_AFIO_AF(GPIOC_LCD_R2, 14U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - PIN2 (input pullup). + * PD3 - LCD_G7 (alternate 14). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - LCD_B2 (alternate 14). + * PD7 - PIN7 (input pullup). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - LCD_TE (input floating). + * PD12 - LCD_RDX (output pushpull maximum). + * PD13 - LCD_WRX (output pushpull maximum). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_G7) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_B2) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_INPUT(GPIOD_LCD_TE) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_RDX) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_WRX) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_G7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_B2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_RDX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_WRX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_G7) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_B2) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_TE) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_RDX) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_WRX) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_G7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_B2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_TE) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_RDX) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_WRX) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_LCD_G7) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_LCD_B2) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_LCD_TE) | \ + PIN_ODR_HIGH(GPIOD_LCD_RDX) | \ + PIN_ODR_HIGH(GPIOD_LCD_WRX) | \ + PIN_ODR_HIGH(GPIOD_FMC_D0) | \ + PIN_ODR_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_G7, 14U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_B2, 14U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ + PIN_AFIO_AF(GPIOD_LCD_TE, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_RDX, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_WRX, 0U) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_D11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D11) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_D11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D11, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - PIN6 (input pullup). + * PF7 - LCD_DCX (alternate 5). + * PF8 - SPI5_MISO (alternate 5). + * PF9 - SPI5_MOSI (alternate 5). + * PF10 - LCD_DE (alternate 14). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DCX) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DE) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DCX) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DE) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_LCD_DCX) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MISO) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_OSPEED_HIGH(GPIOF_LCD_DE) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DCX) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DE) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_LCD_DCX) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_ODR_HIGH(GPIOF_LCD_DE) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_LCD_DCX, 5U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5U) | \ + PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOF_LCD_DE, 14U) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - LCD_R7 (alternate 14). + * PG7 - LCD_CLK (alternate 14). + * PG8 - FMC_SDCLK (alternate 12). + * PG9 - PIN9 (input pullup). + * PG10 - LCD_G3 (alternate 14). + * PG11 - LCD_B3 (alternate 14). + * PG12 - LCD_B4 (alternate 14). + * PG13 - LED3_GREEN (output pushpull maximum). + * PG14 - LED4_RED (output pushpull maximum). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_R7) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_G3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B4) | \ + PIN_MODE_OUTPUT(GPIOG_LED3_GREEN) | \ + PIN_MODE_OUTPUT(GPIOG_LED4_RED) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_R7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_G3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED3_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED4_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_R7) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_CLK) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_G3) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_B3) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_B4) | \ + PIN_OSPEED_HIGH(GPIOG_LED3_GREEN) | \ + PIN_OSPEED_HIGH(GPIOG_LED4_RED) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_R7) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_G3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B4) | \ + PIN_PUPDR_FLOATING(GPIOG_LED3_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOG_LED4_RED) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_LCD_R7) | \ + PIN_ODR_HIGH(GPIOG_LCD_CLK) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_LCD_G3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B4) | \ + PIN_ODR_LOW(GPIOG_LED3_GREEN) | \ + PIN_ODR_LOW(GPIOG_LED4_RED) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ + PIN_AFIO_AF(GPIOG_LCD_R7, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_CLK, 14U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_LCD_G3, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_B3, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_B4, 14U) | \ + PIN_AFIO_AF(GPIOG_LED3_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOG_LED4_RED, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +#define SERIAL_DEFAULT_BITRATE 57600 + +#define BOARD_PAL_LINE_CAN_RX PAL_LINE(GPIOA,11U) +#define BOARD_PAL_LINE_CAN_TX PAL_LINE(GPIOA,12U) + +#define BOARD_PAL_LINE_RED_LED PAL_LINE(GPIOG,14U) +#define BOARD_PAL_LINE_GREEN_LED PAL_LINE(GPIOG,13U) + +#define BOARD_CONFIG_HW_NAME "org.proficnc.uwb" +#define BOARD_CONFIG_HW_MAJOR_VER 1 +#define BOARD_CONFIG_HW_MINOR_VER 0 + +#define BOARD_CONFIG_HW_INFO_STRUCTURE { \ + .hw_name = BOARD_CONFIG_HW_NAME, \ + .hw_major_version = BOARD_CONFIG_HW_MAJOR_VER, \ + .hw_minor_version = BOARD_CONFIG_HW_MINOR_VER, \ + .board_desc_fmt = SHARED_HW_INFO_BOARD_DESC_FMT_NONE, \ + .board_desc = 0, \ +} + diff --git a/examples/driver_usb/boards/com.skt.usb_1.0/board.mk b/examples/driver_usb/boards/com.skt.usb_1.0/board.mk new file mode 100644 index 00000000..b6ef3b07 --- /dev/null +++ b/examples/driver_usb/boards/com.skt.usb_1.0/board.mk @@ -0,0 +1,4 @@ +BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) +BOARD_SRC = $(BOARD_DIR)/board.c +BOARD_INC = $(BOARD_DIR) +MODULES_ENABLED += platform_stm32f429 diff --git a/examples/driver_usb/boards/com.skt.usb_1.0/mcuconf.h b/examples/driver_usb/boards/com.skt.usb_1.0/mcuconf.h new file mode 100644 index 00000000..30270a8d --- /dev/null +++ b/examples/driver_usb/boards/com.skt.usb_1.0/mcuconf.h @@ -0,0 +1,363 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define HAL_USE_SERIAL_USB TRUE +#define HAL_USE_USB TRUE +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/examples/driver_usb/debug/usb (OpenOCD, Flash and Run).launch b/examples/driver_usb/debug/usb (OpenOCD, Flash and Run).launch new file mode 100644 index 00000000..e5446999 --- /dev/null +++ b/examples/driver_usb/debug/usb (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/driver_usb/include/app_config.h b/examples/driver_usb/include/app_config.h new file mode 100644 index 00000000..6d5e357f --- /dev/null +++ b/examples/driver_usb/include/app_config.h @@ -0,0 +1,9 @@ +#pragma once + +#define APP_CONFIG_BOOT_DELAY_SEC 0 +#define APP_CONFIG_CAN_DEFAULT_BAUDRATE 1000000 +#define APP_CONFIG_CAN_LOCAL_NODE_ID 0 +#define APP_CONFIG_CAN_AUTO_BAUD_ENABLE 0 + +#define SHARED_APP_DESCRIPTOR_MAJOR_VERSION 1 +#define SHARED_APP_DESCRIPTOR_MINOR_VERSION 0 diff --git a/examples/driver_usb/include/framework_conf.h b/examples/driver_usb/include/framework_conf.h new file mode 100644 index 00000000..1457957f --- /dev/null +++ b/examples/driver_usb/include/framework_conf.h @@ -0,0 +1,44 @@ +#pragma once + +#define CH_CFG_USE_EVENTS TRUE +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#define CH_CFG_USE_HEAP TRUE + +#define SHELL_CMD_TEST_ENABLED FALSE +// +// Configure worker threads +// + +#define TIMING_WORKER_THREAD lpwork_thread +#define UAVCAN_NODESTATUS_PUBLISHER_WORKER_THREAD lpwork_thread +#define CAN_AUTOBAUD_WORKER_THREAD lpwork_thread +#define UAVCAN_PARAM_INTERFACE_WORKER_THREAD lpwork_thread +#define UAVCAN_GETNODEINFO_SERVER_WORKER_THREAD lpwork_thread +#define UAVCAN_RESTART_WORKER_THREAD lpwork_thread +#define UAVCAN_BEGINFIRMWAREUPDATE_SERVER_WORKER_THREAD lpwork_thread +#define UAVCAN_ALLOCATEE_WORKER_THREAD lpwork_thread +#define PIN_CHANGE_PUBLISHER_WORKER_THREAD lpwork_thread + +#define CAN_TRX_WORKER_THREAD can_thread +#define CAN_EXPIRE_WORKER_THREAD can_thread +#define UAVCAN_RX_WORKER_THREAD can_thread + +// +// Configure topic groups +// + +#define PUBSUB_DEFAULT_TOPIC_GROUP default_topic_group + +// +// Misc configs +// + +#define REQUIRED_RAM_MARGIN_AFTER_INIT 512 + +// +// Configure debug checks +// +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_STACK_CHECK TRUE diff --git a/examples/driver_usb/openocd.cfg b/examples/driver_usb/openocd.cfg new file mode 100644 index 00000000..7101d263 --- /dev/null +++ b/examples/driver_usb/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink-v2-1.cfg] +source [find target/stm32f4x.cfg] +init +reset halt +$_TARGETNAME configure -rtos ChibiOS diff --git a/examples/driver_usb/src/setup.c b/examples/driver_usb/src/setup.c new file mode 100644 index 00000000..53ad7f5d --- /dev/null +++ b/examples/driver_usb/src/setup.c @@ -0,0 +1,8 @@ +#include +#include + +WORKER_THREAD_TAKEOVER_MAIN(lpwork_thread, LOWPRIO) +WORKER_THREAD_SPAWN(can_thread, LOWPRIO, 1024) +WORKER_THREAD_SPAWN(hpwork_thread, HIGHPRIO, 1024) + +PUBSUB_TOPIC_GROUP_CREATE(default_topic_group, 1024) diff --git a/examples/driver_usb/src/usb_test.c b/examples/driver_usb/src/usb_test.c new file mode 100644 index 00000000..e12e461c --- /dev/null +++ b/examples/driver_usb/src/usb_test.c @@ -0,0 +1,133 @@ +#include +#include + +#include + +#include + + +#include "usbcfg.h" +#include +#include +#include +#include /* atoi */ + + +#define WT hpwork_thread +WORKER_THREAD_DECLARE_EXTERN(WT) + +static struct worker_thread_timer_task_s blink_led_green_task; +static struct worker_thread_timer_task_s blink_led_red_task; + +static void blink_led_green_task_func(struct worker_thread_timer_task_s* task); +static void blink_led_red_task_func(struct worker_thread_timer_task_s* task); + +// handle request to change blink speed on green led +void cmd_blinkspeed(BaseSequentialStream *chp, int argc, char *argv[]) { + + (void)argv; + uint16_t millis = 500; + if (argc != 1) { + chprintf(chp, "Usage: blinkspeed speed [ms]\r\n"); + return; + } + millis = atoi(argv[0]); + chprintf(chp, "Got speed [%d]\r\n", millis); // TODO : add UAVCAN Debug + + if (millis > 5000) { + millis = 5000; + } else if(millis < 5) { + millis = 5; + } + worker_thread_timer_task_reschedule(&WT, &blink_led_green_task, MS2ST(millis)); +} + +static const ShellCommand commands[] = { + {"blinkspeed", cmd_blinkspeed} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static THD_WORKING_AREA(waShellThread, 2048); +static THD_FUNCTION(ShellThread, arg) { + (void)arg; + chRegSetThreadName("shellthread"); + while (true) { + if (SDU1.config->usbp->state == USB_ACTIVE) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + } + chThdSleepMilliseconds(1000); + } +} + +// Init the USB +void usb_init(void) { + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + /* + * Shell manager initialization. + */ + shellInit(); + chThdCreateStatic(waShellThread, sizeof(waShellThread), NORMALPRIO+1, + ShellThread, NULL); + +} + +// Hold green led state +bool led_green_on; +// Hold red led state +bool led_red_on; + +// Function call after the end of init +RUN_AFTER(INIT_END) { + usb_init(); + led_green_on = false; + led_red_on = false; + palSetPad(GPIOG, GPIOG_LED3_GREEN); + // Add new tasks to worker thread + // make led blink and report every 1000ms (repeated) + worker_thread_add_timer_task(&WT, &blink_led_green_task, blink_led_green_task_func, NULL, MS2ST(1000), true); + worker_thread_add_timer_task(&WT, &blink_led_red_task, blink_led_red_task_func, NULL, MS2ST(1000), true); +} + + +static void blink_led_green_task_func(struct worker_thread_timer_task_s* task) { + if (led_green_on) { + palClearPad(GPIOG, GPIOG_LED3_GREEN); + led_green_on = false; + } else { + palSetPad(GPIOG, GPIOG_LED3_GREEN); + led_green_on = true; + } + // TODO : add UAVCAN Debug +} + + +static void blink_led_red_task_func(struct worker_thread_timer_task_s* task) { + if (led_red_on) { + palClearPad(GPIOG, GPIOG_LED4_RED); + led_red_on = false; + } else { + palSetPad(GPIOG, GPIOG_LED4_RED); + led_red_on = true; + } + // TODO : add UAVCAN Debug +} + diff --git a/examples/driver_usb/src/usbcfg.c b/examples/driver_usb/src/usbcfg.c new file mode 100644 index 00000000..33103971 --- /dev/null +++ b/examples/driver_usb/src/usbcfg.c @@ -0,0 +1,342 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD2, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/examples/driver_usb/src/usbcfg.h b/examples/driver_usb/src/usbcfg.h new file mode 100644 index 00000000..b62a0287 --- /dev/null +++ b/examples/driver_usb/src/usbcfg.h @@ -0,0 +1,26 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ diff --git a/include/chconf.h b/include/chconf.h index 0e7a97e4..c2288abb 100644 --- a/include/chconf.h +++ b/include/chconf.h @@ -79,9 +79,7 @@ * * @note The default is @p TRUE. */ -#ifndef CH_CFG_USE_TM -#define CH_CFG_USE_TM FALSE -#endif +#define CH_CFG_USE_TM TRUE /** * @brief Threads registry APIs. @@ -100,9 +98,7 @@ * * @note The default is @p TRUE. */ -#ifndef CH_CFG_USE_WAITEXIT -#define CH_CFG_USE_WAITEXIT FALSE -#endif +#define CH_CFG_USE_WAITEXIT TRUE /** * @brief Semaphores APIs. @@ -110,9 +106,7 @@ * * @note The default is @p TRUE. */ -#ifndef CH_CFG_USE_SEMAPHORES -#define CH_CFG_USE_SEMAPHORES FALSE -#endif +#define CH_CFG_USE_SEMAPHORES TRUE /** * @brief Semaphores queuing mode. @@ -157,9 +151,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_CFG_USE_MUTEXES. */ -#ifndef CH_CFG_USE_CONDVARS -#define CH_CFG_USE_CONDVARS FALSE -#endif +#define CH_CFG_USE_CONDVARS TRUE /** * @brief Conditional Variables APIs with timeout. @@ -169,9 +161,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_CFG_USE_CONDVARS. */ -#ifndef CH_CFG_USE_CONDVARS_TIMEOUT -#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE -#endif +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE /** * @brief Events Flags APIs. @@ -179,9 +169,7 @@ * * @note The default is @p TRUE. */ -#ifndef CH_CFG_USE_EVENTS -#define CH_CFG_USE_EVENTS FALSE -#endif +#define CH_CFG_USE_EVENTS TRUE /** * @brief Events Flags APIs with timeout. @@ -191,9 +179,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_CFG_USE_EVENTS. */ -#ifndef CH_CFG_USE_EVENTS_TIMEOUT -#define CH_CFG_USE_EVENTS_TIMEOUT FALSE -#endif +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE /** * @brief Synchronous Messages APIs. @@ -202,9 +188,7 @@ * * @note The default is @p TRUE. */ -#ifndef CH_CFG_USE_MESSAGES -#define CH_CFG_USE_MESSAGES FALSE -#endif +#define CH_CFG_USE_MESSAGES TRUE /** * @brief Synchronous Messages queuing mode. @@ -252,9 +236,7 @@ * @p CH_CFG_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_CFG_USE_HEAP -#define CH_CFG_USE_HEAP FALSE -#endif +#define CH_CFG_USE_HEAP TRUE /** * @brief Memory Pools Allocator APIs. @@ -292,9 +274,16 @@ * @note Requires @p CH_CFG_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#ifndef CH_CFG_USE_DYNAMIC -#define CH_CFG_USE_DYNAMIC FALSE -#endif +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ /** * @brief Debug option, kernel statistics. diff --git a/mk/build.mk b/mk/build.mk index 7f4775f2..92fe5c3f 100644 --- a/mk/build.mk +++ b/mk/build.mk @@ -128,15 +128,17 @@ include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk INCDIR += $(CHIBIOS)/os/license \ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ - $(HALINC) $(PLATFORMINC) $(BOARD_INC) $(TESTINC)$(STREAMSINC) \ + $(HALINC) $(PLATFORMINC) $(BOARD_INC) $(TESTINC) $(STREAMSINC) \ $(CHIBIOS)/community/os/various \ $(CHIBIOS)/os/various \ $(COMMON_INC) \ $(BUILDDIR)/modules +INCDIR += $(SHELLINC) # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC += $(STARTUPSRC) \ @@ -151,6 +153,8 @@ CSRC += $(STARTUPSRC) \ $(MODULES_CSRC) \ $(STREAMSSRC) +CSRC += $(SHELLSRC) + # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. CPPSRC += diff --git a/modules/flash/flash_stm32f3.c b/modules/flash/flash_stm32f3.c index dc74531f..8038281b 100644 --- a/modules/flash/flash_stm32f3.c +++ b/modules/flash/flash_stm32f3.c @@ -3,14 +3,26 @@ #include #include #ifdef STM32F3xx_MCUCONF +#define STM32_FLASH_BASE 0x08000000 #define FLASH_WORD_SIZE sizeof(flash_word_t) typedef uint16_t flash_word_t; -uint32_t flash_getpageaddr(uint32_t page) +void* flash_get_page_addr(uint32_t page) { - return (page*2048); + return (void*)(STM32_FLASH_BASE + (page*2048)); +} + +int16_t flash_get_page_num(void *address) +{ + uint32_t _addr = (uint32_t)address; + return (_addr-STM32_FLASH_BASE)/2048; +} + +uint32_t flash_get_page_ofs(uint32_t page) +{ + return page*2048; } static void __attribute__((noinline)) flash_wait_until_ready(void) { diff --git a/modules/platform_stm32f401/module.mk b/modules/platform_stm32f401/module.mk new file mode 100644 index 00000000..2515a47e --- /dev/null +++ b/modules/platform_stm32f401/module.mk @@ -0,0 +1 @@ +TGT_MCU = stm32f401 diff --git a/modules/platform_stm32f401/platform_stm32f401.c b/modules/platform_stm32f401/platform_stm32f401.c new file mode 100644 index 00000000..af2eafef --- /dev/null +++ b/modules/platform_stm32f401/platform_stm32f401.c @@ -0,0 +1,26 @@ +#include "platform_stm32f401.h" +#include +#include + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + stm32_clock_init(); +} + +void board_get_unique_id(uint8_t* buf, uint8_t len) { + uint32_t unique_id_uint32[3]; + unique_id_uint32[0] = ((uint32_t*)0x1FFF7A10)[2]; + unique_id_uint32[1] = ((uint32_t*)0x1FFF7A10)[1]; + unique_id_uint32[2] = ((uint32_t*)0x1FFF7A10)[0]; + + if (len>12) { + memset(buf, 0, len); + memcpy(buf, unique_id_uint32, 12); + } else { + memcpy(buf, unique_id_uint32, len); + } +} diff --git a/modules/platform_stm32f401/platform_stm32f401.h b/modules/platform_stm32f401/platform_stm32f401.h new file mode 100644 index 00000000..c13adb92 --- /dev/null +++ b/modules/platform_stm32f401/platform_stm32f401.h @@ -0,0 +1,22 @@ +#pragma once + +#include + +#define STM32F427xx + +#define BOARD_PARAM1_FLASH_SIZE ((size_t)&_param1_flash_sec_end - (size_t)&_param1_flash_sec) +#define BOARD_PARAM2_FLASH_SIZE ((size_t)&_param2_flash_sec_end - (size_t)&_param2_flash_sec) + +#define BOARD_PARAM1_ADDR (&_param1_flash_sec) +#define BOARD_PARAM2_ADDR (&_param2_flash_sec) + +extern uint8_t _param1_flash_sec; +extern uint8_t _param1_flash_sec_end; +extern uint8_t _param2_flash_sec; +extern uint8_t _param2_flash_sec_end; + +void board_get_unique_id(uint8_t* buf, uint8_t len); + +#if !defined(_FROM_ASM_) +void boardInit(void); +#endif /* _FROM_ASM_ */ diff --git a/modules/platform_stm32f429/module.mk b/modules/platform_stm32f429/module.mk new file mode 100644 index 00000000..885c759f --- /dev/null +++ b/modules/platform_stm32f429/module.mk @@ -0,0 +1 @@ +TGT_MCU = stm32f429 diff --git a/modules/platform_stm32f429/platform_stm32f429.c b/modules/platform_stm32f429/platform_stm32f429.c new file mode 100644 index 00000000..2d728dcd --- /dev/null +++ b/modules/platform_stm32f429/platform_stm32f429.c @@ -0,0 +1,26 @@ +#include "platform_stm32f429.h" +#include +#include + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + stm32_clock_init(); +} + +void board_get_unique_id(uint8_t* buf, uint8_t len) { + uint32_t unique_id_uint32[3]; + unique_id_uint32[0] = ((uint32_t*)0x1FFF7A10)[2]; + unique_id_uint32[1] = ((uint32_t*)0x1FFF7A10)[1]; + unique_id_uint32[2] = ((uint32_t*)0x1FFF7A10)[0]; + + if (len>12) { + memset(buf, 0, len); + memcpy(buf, unique_id_uint32, 12); + } else { + memcpy(buf, unique_id_uint32, len); + } +} diff --git a/modules/platform_stm32f429/platform_stm32f429.h b/modules/platform_stm32f429/platform_stm32f429.h new file mode 100644 index 00000000..9fb81656 --- /dev/null +++ b/modules/platform_stm32f429/platform_stm32f429.h @@ -0,0 +1,22 @@ +#pragma once + +#include + +#define STM32F429xx + +#define BOARD_PARAM1_FLASH_SIZE ((size_t)&_param1_flash_sec_end - (size_t)&_param1_flash_sec) +#define BOARD_PARAM2_FLASH_SIZE ((size_t)&_param2_flash_sec_end - (size_t)&_param2_flash_sec) + +#define BOARD_PARAM1_ADDR (&_param1_flash_sec) +#define BOARD_PARAM2_ADDR (&_param2_flash_sec) + +extern uint8_t _param1_flash_sec; +extern uint8_t _param1_flash_sec_end; +extern uint8_t _param2_flash_sec; +extern uint8_t _param2_flash_sec_end; + +void board_get_unique_id(uint8_t* buf, uint8_t len); + +#if !defined(_FROM_ASM_) +void boardInit(void); +#endif /* _FROM_ASM_ */ diff --git a/platforms/ARMCMx/ld/stm32f302x8/memory.ld b/platforms/ARMCMx/ld/stm32f302x8/memory.ld index dc462ee1..882e323d 100644 --- a/platforms/ARMCMx/ld/stm32f302x8/memory.ld +++ b/platforms/ARMCMx/ld/stm32f302x8/memory.ld @@ -1,7 +1,7 @@ MEMORY { - bl (rx) : ORIGIN = 0x08000000, LENGTH = 12K - app (rx) : ORIGIN = 0x08000000+12K, LENGTH = 64K-12K-4K + bl (rx) : ORIGIN = 0x08000000, LENGTH = 18K + app (rx) : ORIGIN = 0x08000000+18K, LENGTH = 64K-18K-4K param1 (rx) : ORIGIN = 0x08000000+60K, LENGTH = 2K param2 (rx) : ORIGIN = 0x08000000+62K, LENGTH = 2K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K-256 diff --git a/platforms/ARMCMx/ld/stm32f401/app.ld b/platforms/ARMCMx/ld/stm32f401/app.ld new file mode 100644 index 00000000..79cd5e82 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f401/app.ld @@ -0,0 +1,5 @@ +INCLUDE memory.ld + +REGION_ALIAS("PROGRAM_REGION", app) + +INCLUDE common.ld diff --git a/platforms/ARMCMx/ld/stm32f401/bl.ld b/platforms/ARMCMx/ld/stm32f401/bl.ld new file mode 100644 index 00000000..4fc93665 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f401/bl.ld @@ -0,0 +1,5 @@ +INCLUDE memory.ld + +REGION_ALIAS("PROGRAM_REGION", bl) + +INCLUDE common.ld diff --git a/platforms/ARMCMx/ld/stm32f401/common.ld b/platforms/ARMCMx/ld/stm32f401/common.ld new file mode 100644 index 00000000..ba0aaf7b --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f401/common.ld @@ -0,0 +1,70 @@ +SECTIONS +{ + .param1(NOLOAD) : { + } >param1 + .param2(NOLOAD) : { + } >param2 +} + +PROVIDE(_app_bl_shared_sec = ORIGIN(app_bl_shared)); + +PROVIDE(_bl_flash_sec = ORIGIN(bl)); +PROVIDE(_bl_flash_sec_end = ORIGIN(bl)+LENGTH(bl)); + +PROVIDE(_app_flash_sec = ORIGIN(app)); +PROVIDE(_app_flash_sec_end = ORIGIN(app)+LENGTH(app)); + +PROVIDE(_param1_flash_sec = ORIGIN(param1)); +PROVIDE(_param1_flash_sec_end = ORIGIN(param1)+LENGTH(param1)); + +PROVIDE(_param2_flash_sec = ORIGIN(param2)); +PROVIDE(_param2_flash_sec_end = ORIGIN(param2)+LENGTH(param2)); + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", PROGRAM_REGION); +REGION_ALIAS("VECTORS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", PROGRAM_REGION); +REGION_ALIAS("XTORS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", PROGRAM_REGION); +REGION_ALIAS("TEXT_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", PROGRAM_REGION); +REGION_ALIAS("RODATA_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", PROGRAM_REGION); +REGION_ALIAS("VARIOUS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", PROGRAM_REGION); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram); +REGION_ALIAS("DATA_RAM_LMA", PROGRAM_REGION); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram); + +REGION_ALIAS("ram0", ram) + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/ARMCMx/ld/stm32f401/memory.ld b/platforms/ARMCMx/ld/stm32f401/memory.ld new file mode 100644 index 00000000..1d752392 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f401/memory.ld @@ -0,0 +1,9 @@ +MEMORY +{ + bl (rx) : ORIGIN = 0x08000000, LENGTH = 32K + app (rx) : ORIGIN = 0x08000000+64K, LENGTH = 256K-64K-16k-16k + param1 (rx) : ORIGIN = 0x08000000+224K, LENGTH = 16K + param2 (rx) : ORIGIN = 0x08000000+240K, LENGTH = 16K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K-256 + app_bl_shared (rwx) : ORIGIN = 0x20000000+(64K-256), LENGTH = 256 +} diff --git a/platforms/ARMCMx/ld/stm32f427/memory.ld b/platforms/ARMCMx/ld/stm32f427/memory.ld index 594733c8..8b7326c1 100644 --- a/platforms/ARMCMx/ld/stm32f427/memory.ld +++ b/platforms/ARMCMx/ld/stm32f427/memory.ld @@ -1,9 +1,9 @@ MEMORY { bl (rx) : ORIGIN = 0x08000000, LENGTH = 32K + app (rx) : ORIGIN = 0x08000000+64K, LENGTH = 2M-64K param1 (rx) : ORIGIN = 0x08000000+32K, LENGTH = 16K param2 (rx) : ORIGIN = 0x08000000+48K, LENGTH = 16K - app (rx) : ORIGIN = 0x08000000+64K, LENGTH = 2M-64K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K-256 app_bl_shared (rwx) : ORIGIN = 0x20000000+(192K-256), LENGTH = 256 } diff --git a/platforms/ARMCMx/ld/stm32f429/app.ld b/platforms/ARMCMx/ld/stm32f429/app.ld new file mode 100644 index 00000000..79cd5e82 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f429/app.ld @@ -0,0 +1,5 @@ +INCLUDE memory.ld + +REGION_ALIAS("PROGRAM_REGION", app) + +INCLUDE common.ld diff --git a/platforms/ARMCMx/ld/stm32f429/bl.ld b/platforms/ARMCMx/ld/stm32f429/bl.ld new file mode 100644 index 00000000..4fc93665 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f429/bl.ld @@ -0,0 +1,5 @@ +INCLUDE memory.ld + +REGION_ALIAS("PROGRAM_REGION", bl) + +INCLUDE common.ld diff --git a/platforms/ARMCMx/ld/stm32f429/common.ld b/platforms/ARMCMx/ld/stm32f429/common.ld new file mode 100644 index 00000000..ba0aaf7b --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f429/common.ld @@ -0,0 +1,70 @@ +SECTIONS +{ + .param1(NOLOAD) : { + } >param1 + .param2(NOLOAD) : { + } >param2 +} + +PROVIDE(_app_bl_shared_sec = ORIGIN(app_bl_shared)); + +PROVIDE(_bl_flash_sec = ORIGIN(bl)); +PROVIDE(_bl_flash_sec_end = ORIGIN(bl)+LENGTH(bl)); + +PROVIDE(_app_flash_sec = ORIGIN(app)); +PROVIDE(_app_flash_sec_end = ORIGIN(app)+LENGTH(app)); + +PROVIDE(_param1_flash_sec = ORIGIN(param1)); +PROVIDE(_param1_flash_sec_end = ORIGIN(param1)+LENGTH(param1)); + +PROVIDE(_param2_flash_sec = ORIGIN(param2)); +PROVIDE(_param2_flash_sec_end = ORIGIN(param2)+LENGTH(param2)); + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", PROGRAM_REGION); +REGION_ALIAS("VECTORS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", PROGRAM_REGION); +REGION_ALIAS("XTORS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", PROGRAM_REGION); +REGION_ALIAS("TEXT_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", PROGRAM_REGION); +REGION_ALIAS("RODATA_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", PROGRAM_REGION); +REGION_ALIAS("VARIOUS_FLASH_LMA", PROGRAM_REGION); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", PROGRAM_REGION); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram); +REGION_ALIAS("DATA_RAM_LMA", PROGRAM_REGION); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram); + +REGION_ALIAS("ram0", ram) + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/ARMCMx/ld/stm32f429/memory.ld b/platforms/ARMCMx/ld/stm32f429/memory.ld new file mode 100644 index 00000000..8b7326c1 --- /dev/null +++ b/platforms/ARMCMx/ld/stm32f429/memory.ld @@ -0,0 +1,9 @@ +MEMORY +{ + bl (rx) : ORIGIN = 0x08000000, LENGTH = 32K + app (rx) : ORIGIN = 0x08000000+64K, LENGTH = 2M-64K + param1 (rx) : ORIGIN = 0x08000000+32K, LENGTH = 16K + param2 (rx) : ORIGIN = 0x08000000+48K, LENGTH = 16K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K-256 + app_bl_shared (rwx) : ORIGIN = 0x20000000+(192K-256), LENGTH = 256 +}