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Dev ad9740 wip #3035

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54e4e28
ad9740: Add dts
sarpadi Oct 3, 2025
ca74221
ad9740: enable aux output; set f=128MHz
sarpadi Oct 7, 2025
da812e1
ad9740: Fix adf dts
sarpadi Oct 21, 2025
1fff25a
ad9740: Cleanup
sarpadi Oct 21, 2025
f888616
ad9740: DDS and Ramp mode working
sarpadi Oct 22, 2025
64739bd
ad9740: DMA mode working but not in cyclic mode
sarpadi Oct 23, 2025
0cc3596
ad9740: DMA mode working at 120MHz
sarpadi Oct 23, 2025
73b298b
ad9740: DTS: Update ADF clk to 210MHz
sarpadi Oct 24, 2025
b7d39cd
AD9740: Add support for all 4 devices
sarpadi Oct 28, 2025
a699234
ad9740: Fix MSB alignment
sarpadi Nov 28, 2025
318468a
ad9740: Clean up ad974x references
sarpadi Dec 3, 2025
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96 changes: 96 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9740.dts
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2025 Analog Devices Inc. */

/dts-v1/;

#include "zynq-zed.dtsi"
#include "zynq-zed-adv7511.dtsi"

/ {

clocks {
adf4351_clkin: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "refclk";
};

adf4351_clkout: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <210000000>;
clock-output-names = "adf4351_clkout";
};
};
};

&spi0 {
status="okay";

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+    status="okay";$
adf4351: adf4351@0 {
compatible = "adi,adf4351";
reg = <0>;

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+      compatible = "adi,adf4351";$

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+      reg = <0>;$
spi-max-frequency = <10000000>;

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+      spi-max-frequency = <10000000>;$
clocks = <&adf4351_clkin>;
clock-names = "clkin";

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+      clocks = <&adf4351_clkin>;$

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+      clock-names = "clkin";$
adi,channel-spacing = <10000>;
adi,power-up-frequency = <210000000>;

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+      adi,channel-spacing = <10000>;$
adi,phase-detector-polarity-positive-enable;

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+      adi,power-up-frequency = <210000000>;$
adi,charge-pump-current = <2500>;

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+      adi,phase-detector-polarity-positive-enable;$
adi,output-power = <0>;
adi,aux-output-enable;
adi,aux-output-power = <0>;
adi,muxout-select = <6>;
};
};

&fpga_axi {

dac_tx_dma: dma-controller@44a40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x44a40000 0x10000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <1>;
};
};
};

axi_dac: axi-ad9740@44a70000 {
compatible = "adi,axi-ad9740";
reg = <0x44a70000 0x1000>;
dmas = <&dac_tx_dma 0>;
dma-names = "tx";
#io-backend-cells = <0>;
clocks = <&clkc 15>, <&adf4351_clkout>;
clock-names = "s_axi_aclk", "dac_clk";

#address-cells = <1>;
#size-cells = <0>;

dac@0 {
reg = <0>;
compatible = "adi,ad9740";
reset-gpios = <&gpio0 92 GPIO_ACTIVE_LOW>;
io-backends = <&axi_dac>;
/* Data format: use offset binary (false) or 2's complement (true) */
/* adi,twos-complement; */

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+^I^I        clocks = <&adf4351_clkout>;$
};
};
};
96 changes: 96 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9742.dts
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2025 Analog Devices Inc. */

/dts-v1/;

#include "zynq-zed.dtsi"
#include "zynq-zed-adv7511.dtsi"

/ {

clocks {
adf4351_clkin: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "refclk";
};

adf4351_clkout: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <210000000>;
clock-output-names = "adf4351_clkout";
};
};
};

&spi0 {
status="okay";

adf4351: adf4351@0 {
compatible = "adi,adf4351";
reg = <0>;

spi-max-frequency = <10000000>;

clocks = <&adf4351_clkin>;
clock-names = "clkin";

adi,channel-spacing = <10000>;
adi,power-up-frequency = <210000000>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <2500>;
adi,output-power = <0>;
adi,aux-output-enable;
adi,aux-output-power = <0>;
adi,muxout-select = <6>;
};
};

&fpga_axi {

dac_tx_dma: dma-controller@44a40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x44a40000 0x10000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <1>;
};
};
};

axi_dac: axi-ad9740@44a70000 {
compatible = "adi,axi-ad9740";
reg = <0x44a70000 0x1000>;
dmas = <&dac_tx_dma 0>;
dma-names = "tx";
#io-backend-cells = <0>;
clocks = <&clkc 15>, <&adf4351_clkout>;
clock-names = "s_axi_aclk", "dac_clk";

#address-cells = <1>;
#size-cells = <0>;

dac@0 {
reg = <0>;
compatible = "adi,ad9742";
reset-gpios = <&gpio0 92 GPIO_ACTIVE_LOW>;
io-backends = <&axi_dac>;
/* Data format: use offset binary (false) or 2's complement (true) */
/* adi,twos-complement; */
};
};
};
96 changes: 96 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9744.dts
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2025 Analog Devices Inc. */

/dts-v1/;

#include "zynq-zed.dtsi"
#include "zynq-zed-adv7511.dtsi"

/ {

clocks {
adf4351_clkin: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "refclk";
};

adf4351_clkout: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <210000000>;
clock-output-names = "adf4351_clkout";
};
};
};

&spi0 {
status="okay";

adf4351: adf4351@0 {
compatible = "adi,adf4351";
reg = <0>;

spi-max-frequency = <10000000>;

clocks = <&adf4351_clkin>;
clock-names = "clkin";

adi,channel-spacing = <10000>;
adi,power-up-frequency = <210000000>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <2500>;
adi,output-power = <0>;
adi,aux-output-enable;
adi,aux-output-power = <0>;
adi,muxout-select = <6>;
};
};

&fpga_axi {

dac_tx_dma: dma-controller@44a40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x44a40000 0x10000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <1>;
};
};
};

axi_dac: axi-ad9740@44a70000 {
compatible = "adi,axi-ad9740";
reg = <0x44a70000 0x1000>;
dmas = <&dac_tx_dma 0>;
dma-names = "tx";
#io-backend-cells = <0>;
clocks = <&clkc 15>, <&adf4351_clkout>;
clock-names = "s_axi_aclk", "dac_clk";

#address-cells = <1>;
#size-cells = <0>;

dac@0 {
reg = <0>;
compatible = "adi,ad9744";
reset-gpios = <&gpio0 92 GPIO_ACTIVE_LOW>;
io-backends = <&axi_dac>;
/* Data format: use offset binary (false) or 2's complement (true) */
/* adi,twos-complement; */
};
};
};
96 changes: 96 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9748.dts
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2025 Analog Devices Inc. */

/dts-v1/;

#include "zynq-zed.dtsi"
#include "zynq-zed-adv7511.dtsi"

/ {

clocks {
adf4351_clkin: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "refclk";
};

adf4351_clkout: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <210000000>;
clock-output-names = "adf4351_clkout";
};
};
};

&spi0 {
status="okay";

adf4351: adf4351@0 {
compatible = "adi,adf4351";
reg = <0>;

spi-max-frequency = <10000000>;

clocks = <&adf4351_clkin>;
clock-names = "clkin";

adi,channel-spacing = <10000>;
adi,power-up-frequency = <210000000>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <2500>;
adi,output-power = <0>;
adi,aux-output-enable;
adi,aux-output-power = <0>;
adi,muxout-select = <6>;
};
};

&fpga_axi {

dac_tx_dma: dma-controller@44a40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x44a40000 0x10000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <1>;
};
};
};

axi_dac: axi-ad9740@44a70000 {
compatible = "adi,axi-ad9740";
reg = <0x44a70000 0x1000>;
dmas = <&dac_tx_dma 0>;
dma-names = "tx";
#io-backend-cells = <0>;
clocks = <&clkc 15>, <&adf4351_clkout>;
clock-names = "s_axi_aclk", "dac_clk";

#address-cells = <1>;
#size-cells = <0>;

dac@0 {
reg = <0>;
compatible = "adi,ad9748";
reset-gpios = <&gpio0 92 GPIO_ACTIVE_LOW>;
io-backends = <&axi_dac>;
/* Data format: use offset binary (false) or 2's complement (true) */
/* adi,twos-complement; */
};
};
};
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