From 4854b764cc03379062e14dba028a2359f77e4d3a Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 15 Dec 2025 14:58:54 +0000 Subject: [PATCH] [AArch64][GlobalISel] Add disjoint to the G_OR when lowering G_ROTR/L It looks like this is already handled for funnel shifts, we can do the same for the or created when lowering G_ROTR and G_ROTL. This allows some more add-like-ors to match. --- .../CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +- .../AArch64/GlobalISel/legalize-rotr-rotl.mir | 4 +- llvm/test/CodeGen/AArch64/fsh.ll | 494 ++++++------------ llvm/test/CodeGen/AArch64/rax1.ll | 10 +- .../AMDGPU/GlobalISel/legalize-rotl-rotr.mir | 18 +- .../legalizer/legalize-rotate-rv32.mir | 12 +- .../legalizer/legalize-rotate-rv64.mir | 16 +- 7 files changed, 197 insertions(+), 359 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 251ea4b1e019a..433107ff32753 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -8078,7 +8078,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { RevShiftVal = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); } - MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); + MIRBuilder.buildOr(Dst, ShVal, RevShiftVal, MachineInstr::Disjoint); MI.eraseFromParent(); return Legalized; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir index d2e8f15fced8e..2f0ac5ea76f2b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir @@ -116,7 +116,7 @@ body: | ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND]](<4 x s32>) ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND1]](<4 x s32>) - ; CHECK-NEXT: %rot:_(<4 x s32>) = G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: %rot:_(<4 x s32>) = disjoint G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(<4 x s32>) = COPY $q0 @@ -148,7 +148,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND]](<4 x s32>) ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND1]](<4 x s32>) - ; CHECK-NEXT: %rot:_(<4 x s32>) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: %rot:_(<4 x s32>) = disjoint G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(<4 x s32>) = COPY $q0 diff --git a/llvm/test/CodeGen/AArch64/fsh.ll b/llvm/test/CodeGen/AArch64/fsh.ll index 1db776ea6f616..eb2ca906a9cf2 100644 --- a/llvm/test/CodeGen/AArch64/fsh.ll +++ b/llvm/test/CodeGen/AArch64/fsh.ll @@ -3175,114 +3175,72 @@ entry: } define <8 x i8> @rotl_v8i8_c(<8 x i8> %a) { -; CHECK-SD-LABEL: rotl_v8i8_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.8b, v0.8b, #3 -; CHECK-SD-NEXT: usra v1.8b, v0.8b, #5 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v8i8_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.8b, v0.8b, #3 -; CHECK-GI-NEXT: ushr v0.8b, v0.8b, #5 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v8i8_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.8b, v0.8b, #3 +; CHECK-NEXT: usra v1.8b, v0.8b, #5 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %a, <8 x i8> ) ret <8 x i8> %d } define <8 x i8> @rotr_v8i8_c(<8 x i8> %a) { -; CHECK-SD-LABEL: rotr_v8i8_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.8b, v0.8b, #5 -; CHECK-SD-NEXT: usra v1.8b, v0.8b, #3 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v8i8_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.8b, v0.8b, #3 -; CHECK-GI-NEXT: shl v0.8b, v0.8b, #5 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v8i8_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.8b, v0.8b, #5 +; CHECK-NEXT: usra v1.8b, v0.8b, #3 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %a, <8 x i8> ) ret <8 x i8> %d } define <16 x i8> @rotl_v16i8_c(<16 x i8> %a) { -; CHECK-SD-LABEL: rotl_v16i8_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.16b, v0.16b, #3 -; CHECK-SD-NEXT: usra v1.16b, v0.16b, #5 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v16i8_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.16b, v0.16b, #3 -; CHECK-GI-NEXT: ushr v0.16b, v0.16b, #5 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v16i8_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.16b, v0.16b, #3 +; CHECK-NEXT: usra v1.16b, v0.16b, #5 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %a, <16 x i8> ) ret <16 x i8> %d } define <16 x i8> @rotr_v16i8_c(<16 x i8> %a) { -; CHECK-SD-LABEL: rotr_v16i8_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.16b, v0.16b, #5 -; CHECK-SD-NEXT: usra v1.16b, v0.16b, #3 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v16i8_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.16b, v0.16b, #3 -; CHECK-GI-NEXT: shl v0.16b, v0.16b, #5 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v16i8_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.16b, v0.16b, #5 +; CHECK-NEXT: usra v1.16b, v0.16b, #3 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %a, <16 x i8> ) ret <16 x i8> %d } define <4 x i16> @rotl_v4i16_c(<4 x i16> %a) { -; CHECK-SD-LABEL: rotl_v4i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.4h, v0.4h, #3 -; CHECK-SD-NEXT: usra v1.4h, v0.4h, #13 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v4i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.4h, v0.4h, #3 -; CHECK-GI-NEXT: ushr v0.4h, v0.4h, #13 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v4i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.4h, v0.4h, #3 +; CHECK-NEXT: usra v1.4h, v0.4h, #13 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %a, <4 x i16> ) ret <4 x i16> %d } define <4 x i16> @rotr_v4i16_c(<4 x i16> %a) { -; CHECK-SD-LABEL: rotr_v4i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.4h, v0.4h, #13 -; CHECK-SD-NEXT: usra v1.4h, v0.4h, #3 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v4i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.4h, v0.4h, #3 -; CHECK-GI-NEXT: shl v0.4h, v0.4h, #13 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v4i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.4h, v0.4h, #13 +; CHECK-NEXT: usra v1.4h, v0.4h, #3 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %a, <4 x i16> ) ret <4 x i16> %d @@ -3369,164 +3327,102 @@ entry: } define <8 x i16> @rotl_v8i16_c(<8 x i16> %a) { -; CHECK-SD-LABEL: rotl_v8i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.8h, v0.8h, #3 -; CHECK-SD-NEXT: usra v1.8h, v0.8h, #13 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v8i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.8h, v0.8h, #3 -; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #13 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v8i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.8h, v0.8h, #3 +; CHECK-NEXT: usra v1.8h, v0.8h, #13 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %a, <8 x i16> ) ret <8 x i16> %d } define <8 x i16> @rotr_v8i16_c(<8 x i16> %a) { -; CHECK-SD-LABEL: rotr_v8i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.8h, v0.8h, #13 -; CHECK-SD-NEXT: usra v1.8h, v0.8h, #3 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v8i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #3 -; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v8i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.8h, v0.8h, #13 +; CHECK-NEXT: usra v1.8h, v0.8h, #3 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %a, <8 x i16> ) ret <8 x i16> %d } define <16 x i16> @rotl_v16i16_c(<16 x i16> %a) { -; CHECK-SD-LABEL: rotl_v16i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.8h, v0.8h, #3 -; CHECK-SD-NEXT: shl v3.8h, v1.8h, #3 -; CHECK-SD-NEXT: usra v2.8h, v0.8h, #13 -; CHECK-SD-NEXT: usra v3.8h, v1.8h, #13 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v16i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v2.8h, v0.8h, #3 -; CHECK-GI-NEXT: shl v3.8h, v1.8h, #3 -; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #13 -; CHECK-GI-NEXT: ushr v1.8h, v1.8h, #13 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v16i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.8h, v0.8h, #3 +; CHECK-NEXT: shl v3.8h, v1.8h, #3 +; CHECK-NEXT: usra v2.8h, v0.8h, #13 +; CHECK-NEXT: usra v3.8h, v1.8h, #13 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %a, <16 x i16> ) ret <16 x i16> %d } define <16 x i16> @rotr_v16i16_c(<16 x i16> %a) { -; CHECK-SD-LABEL: rotr_v16i16_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.8h, v0.8h, #13 -; CHECK-SD-NEXT: shl v3.8h, v1.8h, #13 -; CHECK-SD-NEXT: usra v2.8h, v0.8h, #3 -; CHECK-SD-NEXT: usra v3.8h, v1.8h, #3 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v16i16_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v2.8h, v0.8h, #3 -; CHECK-GI-NEXT: ushr v3.8h, v1.8h, #3 -; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 -; CHECK-GI-NEXT: shl v1.8h, v1.8h, #13 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v16i16_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.8h, v0.8h, #13 +; CHECK-NEXT: shl v3.8h, v1.8h, #13 +; CHECK-NEXT: usra v2.8h, v0.8h, #3 +; CHECK-NEXT: usra v3.8h, v1.8h, #3 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %a, <16 x i16> ) ret <16 x i16> %d } define <2 x i32> @rotl_v2i32_c(<2 x i32> %a) { -; CHECK-SD-LABEL: rotl_v2i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.2s, v0.2s, #3 -; CHECK-SD-NEXT: usra v1.2s, v0.2s, #29 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v2i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.2s, v0.2s, #3 -; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #29 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v2i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.2s, v0.2s, #3 +; CHECK-NEXT: usra v1.2s, v0.2s, #29 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %a, <2 x i32> ) ret <2 x i32> %d } define <2 x i32> @rotr_v2i32_c(<2 x i32> %a) { -; CHECK-SD-LABEL: rotr_v2i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.2s, v0.2s, #29 -; CHECK-SD-NEXT: usra v1.2s, v0.2s, #3 -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v2i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.2s, v0.2s, #3 -; CHECK-GI-NEXT: shl v0.2s, v0.2s, #29 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v2i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.2s, v0.2s, #29 +; CHECK-NEXT: usra v1.2s, v0.2s, #3 +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret entry: %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %a, <2 x i32> ) ret <2 x i32> %d } define <4 x i32> @rotl_v4i32_c(<4 x i32> %a) { -; CHECK-SD-LABEL: rotl_v4i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.4s, v0.4s, #3 -; CHECK-SD-NEXT: usra v1.4s, v0.4s, #29 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v4i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.4s, v0.4s, #3 -; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v4i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.4s, v0.4s, #3 +; CHECK-NEXT: usra v1.4s, v0.4s, #29 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %a, <4 x i32> ) ret <4 x i32> %d } define <4 x i32> @rotr_v4i32_c(<4 x i32> %a) { -; CHECK-SD-LABEL: rotr_v4i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.4s, v0.4s, #29 -; CHECK-SD-NEXT: usra v1.4s, v0.4s, #3 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v4i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.4s, v0.4s, #3 -; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v4i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.4s, v0.4s, #29 +; CHECK-NEXT: usra v1.4s, v0.4s, #3 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %a, <4 x i32> ) ret <4 x i32> %d @@ -3558,34 +3454,33 @@ define <7 x i32> @rotl_v7i32_c(<7 x i32> %a) { ; CHECK-GI-LABEL: rotl_v7i32_c: ; CHECK-GI: // %bb.0: // %entry ; CHECK-GI-NEXT: fmov s0, w0 -; CHECK-GI-NEXT: fmov s1, w0 ; CHECK-GI-NEXT: mov w8, #29 // =0x1d -; CHECK-GI-NEXT: fmov s2, w8 +; CHECK-GI-NEXT: fmov s2, w0 +; CHECK-GI-NEXT: fmov s1, w8 ; CHECK-GI-NEXT: mov w9, #3 // =0x3 ; CHECK-GI-NEXT: fmov s3, w4 ; CHECK-GI-NEXT: fmov s4, w4 ; CHECK-GI-NEXT: fmov s5, w9 -; CHECK-GI-NEXT: mov v1.s[1], w1 ; CHECK-GI-NEXT: mov v0.s[1], w1 -; CHECK-GI-NEXT: mov v2.s[1], w8 +; CHECK-GI-NEXT: mov v2.s[1], w1 +; CHECK-GI-NEXT: mov v1.s[1], w8 ; CHECK-GI-NEXT: mov v3.s[1], w5 ; CHECK-GI-NEXT: mov v4.s[1], w5 ; CHECK-GI-NEXT: mov v5.s[1], w9 -; CHECK-GI-NEXT: mov v1.s[2], w2 ; CHECK-GI-NEXT: mov v0.s[2], w2 -; CHECK-GI-NEXT: mov v2.s[2], w8 +; CHECK-GI-NEXT: mov v2.s[2], w2 +; CHECK-GI-NEXT: mov v1.s[2], w8 ; CHECK-GI-NEXT: mov v3.s[2], w6 ; CHECK-GI-NEXT: mov v4.s[2], w6 ; CHECK-GI-NEXT: mov v5.s[2], w9 -; CHECK-GI-NEXT: mov v1.s[3], w3 ; CHECK-GI-NEXT: mov v0.s[3], w3 -; CHECK-GI-NEXT: neg v2.4s, v2.4s +; CHECK-GI-NEXT: mov v2.s[3], w3 +; CHECK-GI-NEXT: neg v1.4s, v1.4s ; CHECK-GI-NEXT: ushl v4.4s, v4.4s, v5.4s -; CHECK-GI-NEXT: shl v1.4s, v1.4s, #3 -; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v4.16b, v2.16b +; CHECK-GI-NEXT: shl v0.4s, v0.4s, #3 +; CHECK-GI-NEXT: ushl v1.4s, v3.4s, v1.4s +; CHECK-GI-NEXT: usra v0.4s, v2.4s, #29 +; CHECK-GI-NEXT: orr v1.16b, v4.16b, v1.16b ; CHECK-GI-NEXT: mov s2, v0.s[1] ; CHECK-GI-NEXT: mov s3, v0.s[2] ; CHECK-GI-NEXT: mov s4, v0.s[3] @@ -3630,34 +3525,33 @@ define <7 x i32> @rotr_v7i32_c(<7 x i32> %a) { ; CHECK-GI-LABEL: rotr_v7i32_c: ; CHECK-GI: // %bb.0: // %entry ; CHECK-GI-NEXT: fmov s0, w0 -; CHECK-GI-NEXT: fmov s1, w0 ; CHECK-GI-NEXT: mov w8, #3 // =0x3 -; CHECK-GI-NEXT: fmov s2, w8 +; CHECK-GI-NEXT: fmov s2, w0 +; CHECK-GI-NEXT: fmov s1, w8 ; CHECK-GI-NEXT: mov w9, #29 // =0x1d ; CHECK-GI-NEXT: fmov s3, w4 ; CHECK-GI-NEXT: fmov s4, w4 ; CHECK-GI-NEXT: fmov s5, w9 -; CHECK-GI-NEXT: mov v1.s[1], w1 ; CHECK-GI-NEXT: mov v0.s[1], w1 -; CHECK-GI-NEXT: mov v2.s[1], w8 +; CHECK-GI-NEXT: mov v2.s[1], w1 +; CHECK-GI-NEXT: mov v1.s[1], w8 ; CHECK-GI-NEXT: mov v3.s[1], w5 ; CHECK-GI-NEXT: mov v4.s[1], w5 ; CHECK-GI-NEXT: mov v5.s[1], w9 -; CHECK-GI-NEXT: mov v1.s[2], w2 ; CHECK-GI-NEXT: mov v0.s[2], w2 -; CHECK-GI-NEXT: mov v2.s[2], w8 +; CHECK-GI-NEXT: mov v2.s[2], w2 +; CHECK-GI-NEXT: mov v1.s[2], w8 ; CHECK-GI-NEXT: mov v3.s[2], w6 ; CHECK-GI-NEXT: mov v4.s[2], w6 ; CHECK-GI-NEXT: mov v5.s[2], w9 -; CHECK-GI-NEXT: mov v1.s[3], w3 ; CHECK-GI-NEXT: mov v0.s[3], w3 -; CHECK-GI-NEXT: neg v2.4s, v2.4s +; CHECK-GI-NEXT: mov v2.s[3], w3 +; CHECK-GI-NEXT: neg v1.4s, v1.4s ; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v5.4s -; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #3 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: ushl v2.4s, v4.4s, v2.4s -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v2.16b, v3.16b +; CHECK-GI-NEXT: ushl v1.4s, v4.4s, v1.4s +; CHECK-GI-NEXT: usra v0.4s, v2.4s, #3 +; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b ; CHECK-GI-NEXT: mov s2, v0.s[1] ; CHECK-GI-NEXT: mov s3, v0.s[2] ; CHECK-GI-NEXT: mov s4, v0.s[3] @@ -3677,138 +3571,84 @@ entry: } define <8 x i32> @rotl_v8i32_c(<8 x i32> %a) { -; CHECK-SD-LABEL: rotl_v8i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.4s, v0.4s, #3 -; CHECK-SD-NEXT: shl v3.4s, v1.4s, #3 -; CHECK-SD-NEXT: usra v2.4s, v0.4s, #29 -; CHECK-SD-NEXT: usra v3.4s, v1.4s, #29 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v8i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v2.4s, v0.4s, #3 -; CHECK-GI-NEXT: shl v3.4s, v1.4s, #3 -; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #29 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v8i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.4s, v0.4s, #3 +; CHECK-NEXT: shl v3.4s, v1.4s, #3 +; CHECK-NEXT: usra v2.4s, v0.4s, #29 +; CHECK-NEXT: usra v3.4s, v1.4s, #29 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %a, <8 x i32> ) ret <8 x i32> %d } define <8 x i32> @rotr_v8i32_c(<8 x i32> %a) { -; CHECK-SD-LABEL: rotr_v8i32_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.4s, v0.4s, #29 -; CHECK-SD-NEXT: shl v3.4s, v1.4s, #29 -; CHECK-SD-NEXT: usra v2.4s, v0.4s, #3 -; CHECK-SD-NEXT: usra v3.4s, v1.4s, #3 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v8i32_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v2.4s, v0.4s, #3 -; CHECK-GI-NEXT: ushr v3.4s, v1.4s, #3 -; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 -; CHECK-GI-NEXT: shl v1.4s, v1.4s, #29 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v8i32_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.4s, v0.4s, #29 +; CHECK-NEXT: shl v3.4s, v1.4s, #29 +; CHECK-NEXT: usra v2.4s, v0.4s, #3 +; CHECK-NEXT: usra v3.4s, v1.4s, #3 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %a, <8 x i32> ) ret <8 x i32> %d } define <2 x i64> @rotl_v2i64_c(<2 x i64> %a) { -; CHECK-SD-LABEL: rotl_v2i64_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.2d, v0.2d, #3 -; CHECK-SD-NEXT: usra v1.2d, v0.2d, #61 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v2i64_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v1.2d, v0.2d, #3 -; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #61 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v2i64_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.2d, v0.2d, #3 +; CHECK-NEXT: usra v1.2d, v0.2d, #61 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %a, <2 x i64> ) ret <2 x i64> %d } define <2 x i64> @rotr_v2i64_c(<2 x i64> %a) { -; CHECK-SD-LABEL: rotr_v2i64_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v1.2d, v0.2d, #61 -; CHECK-SD-NEXT: usra v1.2d, v0.2d, #3 -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v2i64_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v1.2d, v0.2d, #3 -; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v2i64_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v1.2d, v0.2d, #61 +; CHECK-NEXT: usra v1.2d, v0.2d, #3 +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret entry: %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %a, <2 x i64> ) ret <2 x i64> %d } define <4 x i64> @rotl_v4i64_c(<4 x i64> %a) { -; CHECK-SD-LABEL: rotl_v4i64_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.2d, v0.2d, #3 -; CHECK-SD-NEXT: shl v3.2d, v1.2d, #3 -; CHECK-SD-NEXT: usra v2.2d, v0.2d, #61 -; CHECK-SD-NEXT: usra v3.2d, v1.2d, #61 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotl_v4i64_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: shl v2.2d, v0.2d, #3 -; CHECK-GI-NEXT: shl v3.2d, v1.2d, #3 -; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #61 -; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #61 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotl_v4i64_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.2d, v0.2d, #3 +; CHECK-NEXT: shl v3.2d, v1.2d, #3 +; CHECK-NEXT: usra v2.2d, v0.2d, #61 +; CHECK-NEXT: usra v3.2d, v1.2d, #61 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %a, <4 x i64> ) ret <4 x i64> %d } define <4 x i64> @rotr_v4i64_c(<4 x i64> %a) { -; CHECK-SD-LABEL: rotr_v4i64_c: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: shl v2.2d, v0.2d, #61 -; CHECK-SD-NEXT: shl v3.2d, v1.2d, #61 -; CHECK-SD-NEXT: usra v2.2d, v0.2d, #3 -; CHECK-SD-NEXT: usra v3.2d, v1.2d, #3 -; CHECK-SD-NEXT: mov v0.16b, v2.16b -; CHECK-SD-NEXT: mov v1.16b, v3.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: rotr_v4i64_c: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: ushr v2.2d, v0.2d, #3 -; CHECK-GI-NEXT: ushr v3.2d, v1.2d, #3 -; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 -; CHECK-GI-NEXT: shl v1.2d, v1.2d, #61 -; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b -; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: rotr_v4i64_c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: shl v2.2d, v0.2d, #61 +; CHECK-NEXT: shl v3.2d, v1.2d, #61 +; CHECK-NEXT: usra v2.2d, v0.2d, #3 +; CHECK-NEXT: usra v3.2d, v1.2d, #3 +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: mov v1.16b, v3.16b +; CHECK-NEXT: ret entry: %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %a, <4 x i64> ) ret <4 x i64> %d @@ -4450,8 +4290,8 @@ define <2 x i64> @fshl_to_rev2i64(<2 x i64> %r) { ; CHECK-GI-LABEL: fshl_to_rev2i64: ; CHECK-GI: // %bb.0: ; CHECK-GI-NEXT: shl v1.2d, v0.2d, #32 -; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #32 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-GI-NEXT: usra v1.2d, v0.2d, #32 +; CHECK-GI-NEXT: mov v0.16b, v1.16b ; CHECK-GI-NEXT: ret %or = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %r, <2 x i64> %r, <2 x i64> splat (i64 32)) ret <2 x i64> %or @@ -4466,8 +4306,8 @@ define <4 x i32> @fshl_to_rev4i32(<4 x i32> %r) { ; CHECK-GI-LABEL: fshl_to_rev4i32: ; CHECK-GI: // %bb.0: ; CHECK-GI-NEXT: shl v1.4s, v0.4s, #16 -; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #16 -; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-GI-NEXT: usra v1.4s, v0.4s, #16 +; CHECK-GI-NEXT: mov v0.16b, v1.16b ; CHECK-GI-NEXT: ret %or = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %r, <4 x i32> %r, <4 x i32> splat (i32 16)) ret <4 x i32> %or @@ -4482,8 +4322,8 @@ define <2 x i32> @fshl_to_rev2i32(<2 x i32> %r) { ; CHECK-GI-LABEL: fshl_to_rev2i32: ; CHECK-GI: // %bb.0: ; CHECK-GI-NEXT: shl v1.2s, v0.2s, #16 -; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #16 -; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b +; CHECK-GI-NEXT: usra v1.2s, v0.2s, #16 +; CHECK-GI-NEXT: fmov d0, d1 ; CHECK-GI-NEXT: ret %or = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %r, <2 x i32> %r, <2 x i32> splat (i32 16)) ret <2 x i32> %or diff --git a/llvm/test/CodeGen/AArch64/rax1.ll b/llvm/test/CodeGen/AArch64/rax1.ll index 4bb551f0c512d..8452c5d594249 100644 --- a/llvm/test/CodeGen/AArch64/rax1.ll +++ b/llvm/test/CodeGen/AArch64/rax1.ll @@ -20,17 +20,15 @@ define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) { ; SHA3-GI-LABEL: rax1: ; SHA3-GI: // %bb.0: ; SHA3-GI-NEXT: shl v2.2d, v1.2d, #1 -; SHA3-GI-NEXT: ushr v1.2d, v1.2d, #63 -; SHA3-GI-NEXT: orr v1.16b, v2.16b, v1.16b -; SHA3-GI-NEXT: eor v0.16b, v0.16b, v1.16b +; SHA3-GI-NEXT: usra v2.2d, v1.2d, #63 +; SHA3-GI-NEXT: eor v0.16b, v0.16b, v2.16b ; SHA3-GI-NEXT: ret ; ; NOSHA3-GI-LABEL: rax1: ; NOSHA3-GI: // %bb.0: ; NOSHA3-GI-NEXT: shl v2.2d, v1.2d, #1 -; NOSHA3-GI-NEXT: ushr v1.2d, v1.2d, #63 -; NOSHA3-GI-NEXT: orr v1.16b, v2.16b, v1.16b -; NOSHA3-GI-NEXT: eor v0.16b, v0.16b, v1.16b +; NOSHA3-GI-NEXT: usra v2.2d, v1.2d, #63 +; NOSHA3-GI-NEXT: eor v0.16b, v0.16b, v2.16b ; NOSHA3-GI-NEXT: ret %a = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %y, <2 x i64> %y, <2 x i64> ) %b = xor <2 x i64> %x, %a diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir index 7fdee12315754..19fb0c7bbab85 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir @@ -48,7 +48,7 @@ body: | ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32) ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]] ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32) - ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]] + ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]] ; GFX6-NEXT: $sgpr0 = COPY [[OR]](s32) ; ; GFX8-LABEL: name: rotl_i15 @@ -93,7 +93,7 @@ body: | ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[LSHR]], [[AND3]](s16) ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16) - ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[ANYEXT]], [[ANYEXT1]] ; GFX8-NEXT: $sgpr0 = COPY [[OR]](s32) %2:_(s32) = COPY $sgpr0 %0:_(s15) = G_TRUNC %2(s32) @@ -134,7 +134,7 @@ body: | ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32) ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]] + ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]] ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) ; @@ -152,7 +152,7 @@ body: | ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16) ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[SUB]], [[C1]] ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND1]](s16) - ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[SHL]], [[LSHR]] + ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[SHL]], [[LSHR]] ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX8-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) %2:_(s32) = COPY $sgpr0 @@ -235,7 +235,7 @@ body: | ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32) ; GFX-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]] ; GFX-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32) - ; GFX-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]] + ; GFX-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]] ; GFX-NEXT: $sgpr0 = COPY [[OR]](s32) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -274,7 +274,7 @@ body: | ; GFX-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C1]] ; GFX-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC1]](s32) - ; GFX-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] + ; GFX-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] ; GFX-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64) %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $sgpr2_sgpr3 @@ -346,7 +346,7 @@ body: | ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND2]](s16) ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT1]](s32) ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) - ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]] + ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]] ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) ; @@ -364,7 +364,7 @@ body: | ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16) ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[SUB]], [[C1]] ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND1]](s16) - ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR]], [[SHL]] + ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[LSHR]], [[SHL]] ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX8-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) %2:_(s32) = COPY $sgpr0 @@ -427,7 +427,7 @@ body: | ; GFX-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C1]] ; GFX-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) ; GFX-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC1]](s32) - ; GFX-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; GFX-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] ; GFX-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64) %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $sgpr2_sgpr3 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir index fc94c2aaf2a1a..144de9133d19e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir @@ -27,7 +27,7 @@ body: | ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s32) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s32) = COPY $x10 @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s32) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s32) = COPY $x10 @@ -92,7 +92,7 @@ body: | ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32) - ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] ; RV32I-NEXT: $x10 = COPY [[OR]](s32) ; RV32I-NEXT: PseudoRET implicit $x10 ; @@ -192,7 +192,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s32) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s32) = COPY $x10 @@ -226,7 +226,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s32) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s32) = COPY $x10 @@ -257,7 +257,7 @@ body: | ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32) ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) - ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] ; RV32I-NEXT: $x10 = COPY [[OR]](s32) ; RV32I-NEXT: PseudoRET implicit $x10 ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir index 776f5f53fafb7..8419f778195d1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -27,7 +27,7 @@ body: | ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -93,7 +93,7 @@ body: | ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]] - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SLLW]], [[SRLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -133,7 +133,7 @@ body: | ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -173,7 +173,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -207,7 +207,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -239,7 +239,7 @@ body: | ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]] ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]] - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SRLW]], [[SLLW]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SRLW]], [[SLLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -279,7 +279,7 @@ body: | ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64) ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ;