diff --git a/auto_generated/netlist_files/get_clocks_netlist.v b/auto_generated/netlist_files/get_clocks_netlist.v new file mode 100644 index 000000000..eca909b13 --- /dev/null +++ b/auto_generated/netlist_files/get_clocks_netlist.v @@ -0,0 +1,26 @@ +/* +Command: get_clocks +Description: + -Returns a list of clocks matching patterns + +SDC Example: + get_clocks clk1 + get_clocks -quiet clk1098 +*/ + +//Main module +module get_clocks( + input wire clk1, + input wire clk2, + input wire clk_gen, + input wire clock, + output reg dummy_out +); + initial dummy_out = 1'b1; + + always @(posedge clk1 or posedge clk2 or posedge clk_gen or posedge clock) begin + dummy_out <= ~dummy_out; + end + +endmodule + diff --git a/auto_generated/netlist_files/get_pins_netlist.v b/auto_generated/netlist_files/get_pins_netlist.v new file mode 100644 index 000000000..a590d9867 --- /dev/null +++ b/auto_generated/netlist_files/get_pins_netlist.v @@ -0,0 +1,35 @@ +/* +Command: get_pins +Description: + -Returns a list of all instance pins matching patterns + +SDC Example: + get_pins -regexp u1/D + get_pins u1/D +*/ + +//Main module +module get_pins( + input wire clk, + input wire data_in, + output reg [1:0] data_out +); + wire u1_out, u2_out; + + //Datapath + DFF u1(.clk(clk), .D(data_in), .Q(u1_out)); + DFF u2(.clk(clk), .D(~data_in), .Q(u2_out)); + + assign data_out = {u1_out, u2_out}; + +endmodule + +module DFF( + input wire clk, + input wire D, + output reg Q +); + always @(posedge clk) begin + Q <= D; + end +endmodule \ No newline at end of file diff --git a/auto_generated/netlist_files/get_ports_netlist.v b/auto_generated/netlist_files/get_ports_netlist.v new file mode 100644 index 000000000..06980e208 --- /dev/null +++ b/auto_generated/netlist_files/get_ports_netlist.v @@ -0,0 +1,32 @@ +/* +Command: get_ports +Description: + -Returns a list of all top level ports that match patterns + +SDC Example: + get_ports data* + get_ports -regexp rst +*/ + +module get_ports( + input wire clk, + input wire rst, + input wire data1_in, + input wire data2_in, + input wire valid_in, + output reg result_out, + output wire ready_out +); + //ready_out is always 1 for this simple module + assign ready_out = 1'b1; + + always @(posedge clk or posedge rst) begin + if (rst) begin + result_out <= 1'b0; + end + else if (valid_in) begin + result_out <= data1_in + data2_in; + end + end + +endmodule \ No newline at end of file diff --git a/docs/images/Synopsys-Design-Constraints.png b/docs/images/Synopsys-Design-Constraints.png new file mode 100644 index 000000000..1a3b6d792 Binary files /dev/null and b/docs/images/Synopsys-Design-Constraints.png differ diff --git a/docs/images/Syntax-Suite.png b/docs/images/Syntax-Suite.png new file mode 100644 index 000000000..f2ed5cd22 Binary files /dev/null and b/docs/images/Syntax-Suite.png differ diff --git a/docs/images/Timing-Suite.png b/docs/images/Timing-Suite.png new file mode 100644 index 000000000..74add0fa9 Binary files /dev/null and b/docs/images/Timing-Suite.png differ diff --git a/scripts/generate_sdc.py b/scripts/generate_sdc.py index 8922d6bee..5f5ff379c 100644 --- a/scripts/generate_sdc.py +++ b/scripts/generate_sdc.py @@ -100,9 +100,9 @@ ''' PATTERNS = { - "clock": ["clk*", "*clk*", "clk[0-9]*", "clock_*"], - "port": ["*_in", "*_out", "data*", "port*"], - "pin": ["pin*", "*/Q", "*/D", "*/CLK"], + "clock": ["clk*", "clk_gen", "clock", "clk1"], + "port": ["data*", "*in", "*out", "valid_in"], + "pin": ["u1/*", "*/Q", "u2/D", "*/clk"], "cell": ["inst*", "reg_*", "*_buffer"], "net": ["net*", "n[0-9]*", "*_data"] } @@ -235,11 +235,11 @@ def generate_create_clock(): def generate_get_ports(): ''' - Optional: -filter, -regexp, -nocase(Legal only with -regexp), -quiet, -of_objects, patterns + Optional: -regexp, -nocase(Legal only with -regexp), -quiet ''' commands = [] #List containing all possible combinations of options - optional_options = ["-filter", "-regexp", "-nocase", "-quiet", "-of_objects", "patterns"] + optional_options = ["-regexp", "-nocase", "-quiet"] for i in range(len(optional_options) + 1): for option_combination in combinations(optional_options, i): @@ -249,12 +249,6 @@ def generate_get_ports(): continue pieces = ["get_ports"] - - if "-filter" in option_combination: - #FIXME: Random filter type - filter_type = choose_filter_type() - expr = generate_filter(filter_type, "port") - pieces.append(f"-filter {expr}") if "-regexp" in option_combination: pieces.append("-regexp") @@ -264,30 +258,25 @@ def generate_get_ports(): if "-quiet" in option_combination: pieces.append("-quiet") - - if "-of_objects" in option_combination: - #FIXME: Do not make this random. - #The name of net or list of nets - net_list = random.choice(NETS) - pieces.append(f"-of_objects {net_list}") - if "patterns" in option_combination: - #FIXME: Do not make this random. - #A list of port name patterns - pattern = generate_pattern("port") - pieces.append(pattern) - - commands.append(" ".join(pieces)) + #A list of port name patterns + pattern = generate_pattern("port") + pieces.append(pattern) + + #Join the options to create a proper command + pieces = " ".join(pieces) + #Add create_clock prerequisites + pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces) + commands.append(pieces) return commands def generate_get_clocks(): ''' - Required: - Optional: -filter, -regexp, -nocase(Legal only with -regexp), -quiet, patterns + Optional: -regexp, -nocase(Legal only with -regexp), -quiet ''' commands = [] #List containing all possible combinations of options - optional_options = ["-filter", "-regexp", "-nocase", "-quiet", "patterns"] + optional_options = ["-regexp", "-nocase", "-quiet"] for i in range(len(optional_options) + 1): for option_combination in combinations(optional_options, i): @@ -298,12 +287,6 @@ def generate_get_clocks(): pieces = ["get_clocks"] - if "-filter" in option_combination: - #Filter expression with object type "clock" - filter_type = choose_filter_type() - expr = generate_filter(filter_type, "clock") - pieces.append(f"-filter {expr}") - if "-regexp" in option_combination: pieces.append("-regexp") @@ -313,12 +296,18 @@ def generate_get_clocks(): if "-quiet" in option_combination: pieces.append("-quiet") - if "patterns" in option_combination: - #FIXME: Do not make this random. - pattern = generate_pattern("clock") - pieces.append(pattern) - - commands.append(" ".join(pieces)) + pattern = generate_pattern("clock") + pieces.append(pattern) + + #Join the options to create a proper command + pieces = " ".join(pieces) + #Add create_clock prerequisites + pieces = ("create_clock -period 10 -name clk1 [get_ports clk1]\n" + + "create_clock -period 10 -name clk2 [get_ports clk2]\n" + + "create_clock -period 10 -name clk_gen [get_ports clk_gen]\n" + + "create_clock -period 10 -name clock [get_ports clock]\n" + + pieces) + commands.append(pieces) return commands @@ -338,26 +327,8 @@ def generate_get_pins(): if "-nocase" in option_combination and "-regexp" not in option_combination: continue #Skip this invalid combination - #Constraint 2: -hierarchical cannot be used with -of_objects - if "-hierarchical" in option_combination and "-of_objects" in option_combination: - continue #Skip this invalid combination - pieces = ["get_pins"] - if "-hierarchical" in option_combination: - pieces.append("-hierarchical") - - if "-hsc" in option_combination: - #FIXME: Do not make this random. - separator = random.choice(SEPARATOR) - pieces.append(f"-hsc {separator}") - - if "-filter" in option_combination: - #Filter expression with object type "pin" - filter_type = choose_filter_type() - expr = generate_filter(filter_type, "pin") - pieces.append(f"-filter {expr}") - if "-regexp" in option_combination: pieces.append("-regexp") @@ -367,18 +338,15 @@ def generate_get_pins(): if "-quiet" in option_combination: pieces.append("-quiet") - if "-of_objects" in option_combination: - #FIXME: Do not make this random. - #The name or list of nets or instances. - net_inst_list = random.choice(NETS + INSTANCES) - pieces.append(f"-of_objects {net_inst_list}") - - if "patterns" in option_combination: - #A list of pin name patterns - pattern = generate_pattern("pin") - pieces.append(pattern) + pattern = generate_pattern("pin") + pieces.append(pattern) - commands.append(" ".join(pieces)) + + #Join the options to create a proper command + pieces = " ".join(pieces) + #Add create_clock prerequisites + pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces) + commands.append(pieces) return commands