4949 */
5050void SPI_DeInit (void )
5151{
52- SPI -> CR1 = SPI_CR1_RESET_VALUE ;
53- SPI -> CR2 = SPI_CR2_RESET_VALUE ;
54- SPI -> ICR = SPI_ICR_RESET_VALUE ;
55- SPI -> SR = SPI_SR_RESET_VALUE ;
56- SPI -> CRCPR = SPI_CRCPR_RESET_VALUE ;
52+ SPI1 -> CR1 = SPI_CR1_RESET_VALUE ;
53+ SPI1 -> CR2 = SPI_CR2_RESET_VALUE ;
54+ SPI1 -> ICR = SPI_ICR_RESET_VALUE ;
55+ SPI1 -> SR = SPI_SR_RESET_VALUE ;
56+ SPI1 -> CRCPR = SPI_CRCPR_RESET_VALUE ;
5757}
5858
5959/**
@@ -88,26 +88,26 @@ void SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudR
8888 assert_param (IS_SPI_CRC_POLYNOMIAL_OK (CRCPolynomial ));
8989
9090 /* Frame Format, BaudRate, Clock Polarity and Phase configuration */
91- SPI -> CR1 = (uint8_t )((uint8_t )((uint8_t )FirstBit | BaudRatePrescaler ) |
91+ SPI1 -> CR1 = (uint8_t )((uint8_t )((uint8_t )FirstBit | BaudRatePrescaler ) |
9292 (uint8_t )((uint8_t )ClockPolarity | ClockPhase ));
9393
9494 /* Data direction configuration: BDM, BDOE and RXONLY bits */
95- SPI -> CR2 = (uint8_t )((uint8_t )(Data_Direction ) | (uint8_t )(Slave_Management ));
96-
95+ SPI1 -> CR2 = (uint8_t )((uint8_t )(Data_Direction ) | (uint8_t )(Slave_Management ));
96+
9797 if (Mode == SPI_MODE_MASTER )
9898 {
99- SPI -> CR2 |= (uint8_t )SPI_CR2_SSI ;
99+ SPI1 -> CR2 |= (uint8_t )SPI_CR2_SSI ;
100100 }
101101 else
102102 {
103- SPI -> CR2 &= (uint8_t )~(SPI_CR2_SSI );
103+ SPI1 -> CR2 &= (uint8_t )~(SPI_CR2_SSI );
104104 }
105105
106106 /* Master/Slave mode configuration */
107- SPI -> CR1 |= (uint8_t )(Mode );
108-
107+ SPI1 -> CR1 |= (uint8_t )(Mode );
108+
109109 /* CRC configuration */
110- SPI -> CRCPR = (uint8_t )CRCPolynomial ;
110+ SPI1 -> CRCPR = (uint8_t )CRCPolynomial ;
111111}
112112
113113/**
@@ -123,11 +123,11 @@ void SPI_Cmd(FunctionalState NewState)
123123
124124 if (NewState != DISABLE )
125125 {
126- SPI -> CR1 |= SPI_CR1_SPE ; /* Enable the SPI peripheral*/
126+ SPI1 -> CR1 |= SPI_CR1_SPE ; /* Enable the SPI peripheral*/
127127 }
128128 else
129129 {
130- SPI -> CR1 &= (uint8_t )(~SPI_CR1_SPE ); /* Disable the SPI peripheral*/
130+ SPI1 -> CR1 &= (uint8_t )(~SPI_CR1_SPE ); /* Disable the SPI peripheral*/
131131 }
132132}
133133
@@ -150,11 +150,11 @@ void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
150150
151151 if (NewState != DISABLE )
152152 {
153- SPI -> ICR |= itpos ; /* Enable interrupt*/
153+ SPI1 -> ICR |= itpos ; /* Enable interrupt*/
154154 }
155155 else
156156 {
157- SPI -> ICR &= (uint8_t )(~itpos ); /* Disable interrupt*/
157+ SPI1 -> ICR &= (uint8_t )(~itpos ); /* Disable interrupt*/
158158 }
159159}
160160
@@ -165,7 +165,7 @@ void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
165165 */
166166void SPI_SendData (uint8_t Data )
167167{
168- SPI -> DR = Data ; /* Write in the DR register the data to be sent*/
168+ SPI1 -> DR = Data ; /* Write in the DR register the data to be sent*/
169169}
170170
171171/**
@@ -175,7 +175,7 @@ void SPI_SendData(uint8_t Data)
175175 */
176176uint8_t SPI_ReceiveData (void )
177177{
178- return ((uint8_t )SPI -> DR ); /* Return the data in the DR register*/
178+ return ((uint8_t )SPI1 -> DR ); /* Return the data in the DR register*/
179179}
180180
181181/**
@@ -191,11 +191,11 @@ void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
191191
192192 if (NewState != DISABLE )
193193 {
194- SPI -> CR2 |= SPI_CR2_SSI ; /* Set NSS pin internally by software*/
194+ SPI1 -> CR2 |= SPI_CR2_SSI ; /* Set NSS pin internally by software*/
195195 }
196196 else
197197 {
198- SPI -> CR2 &= (uint8_t )(~SPI_CR2_SSI ); /* Reset NSS pin internally by software*/
198+ SPI1 -> CR2 &= (uint8_t )(~SPI_CR2_SSI ); /* Reset NSS pin internally by software*/
199199 }
200200}
201201
@@ -206,7 +206,7 @@ void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
206206 */
207207void SPI_TransmitCRC (void )
208208{
209- SPI -> CR2 |= SPI_CR2_CRCNEXT ; /* Enable the CRC transmission*/
209+ SPI1 -> CR2 |= SPI_CR2_CRCNEXT ; /* Enable the CRC transmission*/
210210}
211211
212212/**
@@ -222,11 +222,11 @@ void SPI_CalculateCRCCmd(FunctionalState NewState)
222222
223223 if (NewState != DISABLE )
224224 {
225- SPI -> CR2 |= SPI_CR2_CRCEN ; /* Enable the CRC calculation*/
225+ SPI1 -> CR2 |= SPI_CR2_CRCEN ; /* Enable the CRC calculation*/
226226 }
227227 else
228228 {
229- SPI -> CR2 &= (uint8_t )(~SPI_CR2_CRCEN ); /* Disable the CRC calculation*/
229+ SPI1 -> CR2 &= (uint8_t )(~SPI_CR2_CRCEN ); /* Disable the CRC calculation*/
230230 }
231231}
232232
@@ -244,11 +244,11 @@ uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)
244244
245245 if (SPI_CRC != SPI_CRC_RX )
246246 {
247- crcreg = SPI -> TXCRCR ; /* Get the Tx CRC register*/
247+ crcreg = SPI1 -> TXCRCR ; /* Get the Tx CRC register*/
248248 }
249249 else
250250 {
251- crcreg = SPI -> RXCRCR ; /* Get the Rx CRC register*/
251+ crcreg = SPI1 -> RXCRCR ; /* Get the Rx CRC register*/
252252 }
253253
254254 /* Return the selected CRC register status*/
@@ -277,7 +277,7 @@ void SPI_ResetCRC(void)
277277 */
278278uint8_t SPI_GetCRCPolynomial (void )
279279{
280- return SPI -> CRCPR ; /* Return the CRC polynomial register */
280+ return SPI1 -> CRCPR ; /* Return the CRC polynomial register */
281281}
282282
283283/**
@@ -292,11 +292,11 @@ void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)
292292
293293 if (SPI_Direction != SPI_DIRECTION_RX )
294294 {
295- SPI -> CR2 |= SPI_CR2_BDOE ; /* Set the Tx only mode*/
295+ SPI1 -> CR2 |= SPI_CR2_BDOE ; /* Set the Tx only mode*/
296296 }
297297 else
298298 {
299- SPI -> CR2 &= (uint8_t )(~SPI_CR2_BDOE ); /* Set the Rx only mode*/
299+ SPI1 -> CR2 &= (uint8_t )(~SPI_CR2_BDOE ); /* Set the Rx only mode*/
300300 }
301301}
302302
@@ -315,7 +315,7 @@ FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)
315315 assert_param (IS_SPI_FLAGS_OK (SPI_FLAG ));
316316
317317 /* Check the status of the specified SPI flag */
318- if ((SPI -> SR & (uint8_t )SPI_FLAG ) != (uint8_t )RESET )
318+ if ((SPI1 -> SR & (uint8_t )SPI_FLAG ) != (uint8_t )RESET )
319319 {
320320 status = SET ; /* SPI_FLAG is set */
321321 }
@@ -347,7 +347,7 @@ void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)
347347{
348348 assert_param (IS_SPI_CLEAR_FLAGS_OK (SPI_FLAG ));
349349 /* Clear the flag bit */
350- SPI -> SR = (uint8_t )(~SPI_FLAG );
350+ SPI1 -> SR = (uint8_t )(~SPI_FLAG );
351351}
352352
353353/**
@@ -379,9 +379,9 @@ ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)
379379 /* Set the IT mask */
380380 itmask2 = (uint8_t )((uint8_t )1 << itmask1 );
381381 /* Get the SPI_ITPENDINGBIT enable bit status */
382- enablestatus = (uint8_t )((uint8_t )SPI -> SR & itmask2 );
382+ enablestatus = (uint8_t )((uint8_t )SPI1 -> SR & itmask2 );
383383 /* Check the status of the specified SPI interrupt */
384- if (((SPI -> ICR & itpos ) != RESET ) && enablestatus )
384+ if (((SPI1 -> ICR & itpos ) != RESET ) && enablestatus )
385385 {
386386 /* SPI_ITPENDINGBIT is set */
387387 pendingbitstatus = SET ;
@@ -419,8 +419,8 @@ void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)
419419 /* Get the SPI pending bit index */
420420 itpos = (uint8_t )((uint8_t )1 << (uint8_t )((uint8_t )(SPI_IT & (uint8_t )0xF0 ) >> 4 ));
421421 /* Clear the pending bit */
422- SPI -> SR = (uint8_t )(~itpos );
423-
422+ SPI1 -> SR = (uint8_t )(~itpos );
423+
424424}
425425
426426/**
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