Add intrinsics for the new FP conversions introduced by the 2024 dpISA #407

amilendra · 2025-08-20T15:06:41Z

FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit

For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to

Single Precision to 64-bit : Dd,Sn
Double Precision to 32-bit : Sd,Dn

The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; Hd,Hn, so this patch fixes them to be

Half Precision to 32-bit : Sd,Hn
Half Precision to 64-bit : Dd,Hn

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main/acle.md

tools/intrinsic_db/advsimd.csv

ktkachov · 2025-09-18T13:58:58Z

As these instructions operate only on scalar values should they be defined in the arm_acle.h header instead of arm_neon.h?

CarolineConcatto · 2025-09-19T12:40:34Z

Hi @ktkachov,
So this is a PR to add in the ACLE specification more type sizes to intrinsics, they are also using converts between only neon registers. There is no general purpose registers.
I am not sure why you are asking which library should this be on? But just in case from the ACLE what should be in

<arm_acle.h> provides access to intrinsics that do not belong
to the more specific header files below. These intrinsics are in the
C implementation namespace and begin with double underscores. It is
unspecified whether they are available without the header being
included. When __ARM_ACLE is defined to 1, the header file is
guaranteed to be available.

The new type for the converts are for FPRCVT.
These new instructions will probably be inside arm_neon.h, as I think the previous ones are also in

main/acle.md

tools/intrinsic_db/advsimd.csv

FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit 2) Half Precision to 64-bit 3) Single Precision to 64-bit 4) Double Precision to 32-bit For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to - Single Precision to 64-bit : <INST> Dd,Sn - Double Precision to 32-bit : <INST> Sd,Dn The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; <INST> Hd,Hn, so this patch fixes them to be - Half Precision to 32-bit : <INST> Sd,Hn - Half Precision to 64-bit : <INST> Dd,Hn

Lukacma · 2025-10-08T09:06:27Z

tools/intrinsic_db/advsimd.csv

 uint32x2_t vcvta_u32_f32(float32x2_t a)	a -> Vn.2S	FCVTAU Vd.2S,Vn.2S	Vd.2S -> result	A32/A64
 uint32x4_t vcvtaq_u32_f32(float32x4_t a)	a -> Vn.4S	FCVTAU Vd.4S,Vn.4S	Vd.4S -> result	A32/A64
 int32_t vcvts_s32_f32(float32_t a)	a -> Sn	FCVTZS Sd,Sn	Sd -> result	A64
+int64_t vcvts_s64_f32(float32_t a)	a -> Sn	FCVTZS Dd,Sn	Dd -> result	A64


Is there a reason you didn't include GPR variants here ?

My reasoning was that the fact that there were no existing conversion intrinsics that lowered to GPRs (https://developer.arm.com/documentation/ddi0602/2025-06/SIMD-FP-Instructions/FCVTZS--scalar--integer---Floating-point-convert-to-signed-integer--rounding-toward-zero--scalar--) we would only need to implement the intrinsics that lower to Neon registers. Thinking a bit more I guess it is better to extend the proposal to intrinsics that lower to both GP and Neon registers?

…both GP/Neon registers

Lukacma

LGTM

AlfieRichardsArm · 2025-11-04T14:40:14Z

Im not sure why the comments about removing AArch32 versions were resolved, that still seems like an issue here

Lukacma · 2025-12-01T16:10:14Z

@AlfieRichardsArm are you happy about the removal of AArch32 versions ?

AlfieRichardsArm · 2025-12-22T08:59:37Z

@Lukacma not really, Im still unclear why this is removing the AArch32 version of vcvth_s32_f16 and similar?

AlfieRichardsArm · 2025-12-22T09:00:33Z

tools/intrinsic_db/advsimd.csv

+int32_t vcvth_s32_f16(float16_t a)	a -> Hn	FCVTZS Sd/Wd,Hn	Sd/Wd -> result	A64
+int64_t vcvth_s64_f16(float16_t a)	a -> Hn	FCVTZS Dd/Xd,Hn	Dd/Xd -> result	A64
 uint16_t vcvth_u16_f16(float16_t a)	a -> Hn	FCVTZU Hd,Hn	Hd -> result	A64
-uint32_t vcvth_u32_f16(float16_t a)	a -> Hn	FCVTZU Hd,Hn	Hd -> result	A32/A64


It seems here the A32 variant is removed? Why is this? I dont think we should do that.

I don't know for sure, but from what I could find the only conversion instruction I could find in A32 is this one which operates on 32 bit values only. So maybe only intrinsics for this variant should exist in A32 and rest should be A64 only ?

There are more conversion instructions here.

But regardless, if we currently support these intrinsics for AAarch32, and have done for some time, removing them is a breaking change that would need much wider discussion?

As I understand it, this extension adds support for existing conversions in AArch64 but allows the integer part to remain in the FP registers. It should have no effect on our AArch32 intrinsics so removing AArch32 intrinsics here seems wrong.

Okay. I don't think any compiler actually supports these intrinsics in aarch32 as their corresponding instructions don't exist, but I agree this change is unrelated to the core of the patch so I will remove it.

Lukacma reviewed Aug 21, 2025

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amilendra force-pushed the 2025-acle-fprcvt branch 2 times, most recently from 4dbaa35 to a4bc412 Compare September 15, 2025 11:56

Lukacma reviewed Oct 3, 2025

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amilendra force-pushed the 2025-acle-fprcvt branch from 04bd0d1 to f080ec7 Compare October 7, 2025 10:26

Lukacma reviewed Oct 8, 2025

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Extend FP Single<->Double precision conversions to return results in …

85c2698

…both GP/Neon registers

Lukacma approved these changes Oct 9, 2025

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CarolineConcatto approved these changes Dec 1, 2025

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AlfieRichardsArm suggested changes Dec 22, 2025

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Add intrinsics for the new FP conversions introduced by the 2024 dpISA #407

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amilendra commented Aug 20, 2025 •

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