Add intrinsics for the FEAT_SVE2p2/FEAT_SME2p2 features introduced by the 2024 dpISA #412

amilendra · 2025-09-15T16:00:39Z

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main/acle.md

AlfieRichardsArm · 2025-09-18T10:14:40Z

~~This seems to be missing~~
~~- the zeroing forms of all the unary instructions added in S(M|V)E2p2? Such as NOT (zeroing) and REVB (zeroing) and lots more.~~
~~- FRECPX~~
~~- FSQRT~~

~~Will they be added separately?~~

Corrected offline that these intrinsics are all already present, and will just be simplified by the new instructions.

Lukacma · 2025-09-23T14:45:38Z

main/acle.md

+ [`<arm_sve.h>`](#arm_sve.h) or [`<arm_sme.h>`](#arm_sme.h)
+when `__ARM_FEATURE_SVE2p2` or `__ARM_FEATURE_SME2p2` is defined, respectively.
+
+These intrinsics can only be called from non-streaming code if


So this is not correct. These instruction can be called in non-streaming mode if we have sme2p2 and sve as well.

For FIRSTP and LASTP you can also run them in streaming mode if you have sve2p2 and sme.

I've updated the conditions. Please can you have another look?

main/acle.md

Lukacma

LGTM

main/acle.md

CarolineConcatto · 2025-10-06T16:22:25Z

main/acle.md

+`__ARM_FEATURE_SME2p2` feature macro is defined.
+
+They can be called from non-streaming code if the `__ARM_FEATURE_SVE2p2` feature
+macro is defined or both the `__ARM_FEATURE_SVE` and `__ARM_FEATURE_SME2p2`


I am not sure this is correct:
__ARM_FEATURE_SVE and __ARM_FEATURE_SME2p2
should it be:
__ARM_FEATURE_SME and __ARM_FEATURE_SME2p2
Why are you writing that it needs SVE, have you seeing this in the pseudo code from the instruction?

Yes. Actually that is something I understood from the pseudocode.

For example the psuedocode of COMPACT checks for SVE

It was not immediately obvious to me either, and was pointed out by @Lukacma

The size that is now available also in sme2p2 and sve is Word and doubleword.
You are adding new ones that are only available for sve2p2 or sme2p2

Removed those conditions because it is simply repeating information already available in the ISA docs.

CarolineConcatto · 2025-10-06T16:25:02Z

main/acle.md

+
+Scalar index of first/last true predicate element (predicated).
+
+These intrinsics can be called from streaming mode if either of the feature


I believe this is incorrect. Can you remove these sentences?
They need sve2p2 or sme2p2, there is nothing saying about sve or sme.

Similar to COMPACT, this is also something I understood from the CheckSVEEnabled pseudocode used by FIRSTP

That is when the instructions is defined:
if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
CheckSVEEnabled is how it will run, in streaming mode or sve.

Removed those conditions because it is simply repeating information already available in the ISA docs.

main/acle.md

CarolineConcatto · 2025-10-06T16:26:59Z

main/acle.md

+
+Copy active vector elements to/from lower-numbered elements.
+
+These intrinsics can be called from streaming code only if the


I believe this sentence are applied to all sve2p2 and sme2p2 instruction you can move it up. After line 13601

Removed those conditions because it is simply repeating information already available in the ISA docs.

Lukacma · 2025-10-14T12:16:31Z

main/acle.md

+
+``` c
+  // Variants are also available for:
+  // [_single_f32_x2]


I think we should split this into x2 and x4 variants. I think this might confuse users as to what type to use for arguments.

I've split them up. Does this look okay?

main/acle.md

These instructions are available under features FEAT_SVE2p2 or FEAT_SME2p2. COMPACT: Copy Active vector elements to lower-numbered elements (Byte/Halfword variants) EXPAND: Copy lower-numbered vector elements to Active elements (Byte/Halfword/Word/Doubleword variants) FIRSTP: Scalar index of first true predicate element (predicated) (Byte/Halfword/Word/Doubleword variants) LASTP: Scalar index of last true predicate element (predicated) (Byte/Halfword/Word/Doubleword variants) FMUL (multiple and single vector): Multi-vector floating-point multiply by vector FMUL (multiple vectors): Multi-vector floating-point multiply

…ing code

1. Change firstp/lastp parameter names to match the register names: op -> pn 2. split the x2 and x4 variants of the FMUL intrinsics

Lukacma · 2025-11-14T12:05:21Z

main/acle.md

+extended in the future.
+
+The intrinsics in this section are defined by the header file
+[`<arm_sme.h>`](#arm_sme.h) when `__ARM_FEATURE_SME2p2` is defined.


Since these instructions do not operate on ZA array, I think they should be in arm_sve.h.

After internal discusion this whole system of specifying header files will be overhauled, so no changes necessary here until then

CarolineConcatto · 2025-11-19T10:49:32Z

We need to add these new instructions also:
FRINT32X
FRINT32Z
FRINT64X
FRINT64Z
They are sve2p2 as well

CarolineConcatto · 2025-11-25T13:36:39Z

main/acle.md

+```c
+
+// Variant is available for _f64
+svfloat32_t frint32x[_f32]_z(svbool_t pg, svfloat32_t zn);


I believe this should be:
s /frint/svrint/g

CarolineConcatto · 2025-11-25T13:47:01Z

main/acle.md

+// _f32_f64, _bf16_f32
+svfloat16_t	svcvtnt_f16[_f32]_z	(svfloat16_t even, svbool_t pg, svfloat32_t op)
+
+svfloat32_t	svcvtxnt_f32[_f64]_z	(svfloat32_t even, svbool_t pg, svfloat64_t op);


nit: space between the function name and the parameters

This patch add supports in Clang for these assembly intrinsics: FRINT32X FRINT32Z FRINT64X FRINT64Z By adding support for these intrinsics: // Variant is available for _f64 svfloat32_t svrint32x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); ``` according to the ACLE[1] [1]ARM-software/acle#412

CarolineConcatto · 2025-11-26T15:52:18Z

main/acle.md

+
+// Variants are available for:
+// _f32_f64, _bf16_f32
+svfloat16_t	svcvtnt_f16[_f32]_z	(svfloat16_t even, svbool_t pg, svfloat32_t op)


Missing comma at the end of the intrinsic

…rinsics This patch adds support in Clang for these assembly instructions FCVTXNT, FCVTLT, {B}FCVTNT By implementing these prototypes: // Variant is available for _f64_f32 svfloat32_t svcvtlt_f32[_f16]_z (svbool_t pg, svfloat16_t op); // Variants are available for: // _f32_f64, _bf16_f32 svfloat16_t svcvtnt_f16[_f32]_z (svfloat16_t even, svbool_t pg, svfloat32_t op); svfloat32_t svcvtxnt_f32[_f64]_z (svfloat32_t even, svbool_t pg, svfloat64_t op); according to the ACLE[1] [1] ARM-software/acle#412

This patch adds intrinsics for multi-vector FMUL instructions introduced in armv9.6, based on [this](ARM-software/acle#412) ACLE proposal. Depends on #163536 Intrinsics implemented: //BFMUL: svbfloat16x2_t svmul[_bf16_x2](svbfloat16x2_t zd, svbfloat16x2_t zm) __arm_streaming; svbfloat16x2_t svmul[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zm) __arm_streaming; svbfloat16x4_t svmul[_bf16_x4](svbfloat16x4_t zd, svbfloat16x4_t zm) __arm_streaming; svbfloat16x4_t svmul[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zm) __arm_streaming;

…63397) This patch adds intrinsics for multi-vector FMUL instructions introduced in armv9.6, based on [this](ARM-software/acle#412) ACLE proposal. Depends on #163536 Intrinsics implemented: //BFMUL: svbfloat16x2_t svmul[_bf16_x2](svbfloat16x2_t zd, svbfloat16x2_t zm) __arm_streaming; svbfloat16x2_t svmul[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zm) __arm_streaming; svbfloat16x4_t svmul[_bf16_x4](svbfloat16x4_t zd, svbfloat16x4_t zm) __arm_streaming; svbfloat16x4_t svmul[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zm) __arm_streaming;

…rinsics This patch adds support in Clang for these assembly instructions FCVTXNT, FCVTLT, {B}FCVTNT By implementing these prototypes: // Variant is available for _f64_f32 svfloat32_t svcvtlt_f32[_f16]_z (svbool_t pg, svfloat16_t op); // Variants are available for: // _f32_f64, _bf16_f32 svfloat16_t svcvtnt_f16[_f32]_z (svfloat16_t even, svbool_t pg, svfloat32_t op); svfloat32_t svcvtxnt_f32[_f64]_z (svfloat32_t even, svbool_t pg, svfloat64_t op); according to the ACLE[1] [1] ARM-software/acle#412

This patch add intrinsics for SVE2p2 instructions defined in [this](ARM-software/acle#412) ACLE proposal. Intrinsics added: ``` // Variants are available for: // _s8, _s16, _u16, _mf8, _bf16, _f16 svuint8_t svcompact[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64 // _mf8, _bf16, _f16, _f32, _f64 svuint8_t svexpand[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _b16, _b32, _b64 int64_t svfirstp_b8(svbool_t pg, svbool_t pn); // Variants are available for: // _b16, _b32, _b64 int64_t svlastp_b8(svbool_t pg, svbool_t pn); ``` It also generates Sema tests using aarch64_builtins_test_generator script for some previously merged intrinsics patches, which were merged without regenerating. --------- Co-authored-by: Kerry McLaughlin <kerry.mclaughlin@arm.com>

…#163575) This patch add intrinsics for SVE2p2 instructions defined in [this](ARM-software/acle#412) ACLE proposal. Intrinsics added: ``` // Variants are available for: // _s8, _s16, _u16, _mf8, _bf16, _f16 svuint8_t svcompact[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64 // _mf8, _bf16, _f16, _f32, _f64 svuint8_t svexpand[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _b16, _b32, _b64 int64_t svfirstp_b8(svbool_t pg, svbool_t pn); // Variants are available for: // _b16, _b32, _b64 int64_t svlastp_b8(svbool_t pg, svbool_t pn); ``` It also generates Sema tests using aarch64_builtins_test_generator script for some previously merged intrinsics patches, which were merged without regenerating. --------- Co-authored-by: Kerry McLaughlin <kerry.mclaughlin@arm.com>

This patch add intrinsics for SVE2p2 instructions defined in [this](ARM-software/acle#412) ACLE proposal. Intrinsics added: ``` // Variants are available for: // _s8, _s16, _u16, _mf8, _bf16, _f16 svuint8_t svcompact[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64 // _mf8, _bf16, _f16, _f32, _f64 svuint8_t svexpand[_u8](svbool_t pg, svuint8_t zn); // Variants are available for: // _b16, _b32, _b64 int64_t svfirstp_b8(svbool_t pg, svbool_t pn); // Variants are available for: // _b16, _b32, _b64 int64_t svlastp_b8(svbool_t pg, svbool_t pn); ``` It also generates Sema tests using aarch64_builtins_test_generator script for some previously merged intrinsics patches, which were merged without regenerating. --------- Co-authored-by: Kerry McLaughlin <kerry.mclaughlin@arm.com>

amilendra force-pushed the 2025-acle-sve-sme2p2 branch from b421a82 to 2dd7a0d Compare September 16, 2025 12:41

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amilendra force-pushed the 2025-acle-sve-sme2p2 branch from 2dd7a0d to 137ff03 Compare September 18, 2025 14:04

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amilendra force-pushed the 2025-acle-sve-sme2p2 branch from 137ff03 to 7de9269 Compare October 1, 2025 15:02

amilendra mentioned this pull request Oct 2, 2025

Add support for the Brain 16-bit floating-point vector multiplication (FEAT_SVE_BFSCALE) intrinsics #410

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amilendra changed the title ~~Add support for COMPACT/EXPAND and FIRSTP/LASTP intrinsics~~ Add intrinsics for the FEAT_SVE2p2/FEAT_SME2p2 features introduced by the 2024 dpISA Oct 2, 2025

Lukacma approved these changes Oct 3, 2025

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amilendra force-pushed the 2025-acle-sve-sme2p2 branch from ff8fbf9 to 777686d Compare October 7, 2025 15:48

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This was referenced Oct 14, 2025

[AArch64] Add intrinsics support for multi-vector FMUL llvm/llvm-project#163397

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[AArch64] Add intrinsics support for SVE2p2 instructions llvm/llvm-project#163575

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amilendra added 4 commits October 24, 2025 11:45

Add SME2.2/SVE2.2 support status (Alpha) to the content

78c7dd0

SME/SVE2.2 Remove conditions for being called by streaming/non-stream…

09763cc

…ing code

Address review comments

29f8554

1. Change firstp/lastp parameter names to match the register names: op -> pn 2. split the x2 and x4 variants of the FMUL intrinsics

amilendra force-pushed the 2025-acle-sve-sme2p2 branch from 5f3e66f to 29f8554 Compare October 24, 2025 12:42

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Lukacma added 3 commits November 19, 2025 12:04

add frint intrinsics

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remove empty lines

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Add missing zeroing forms of predicated convert intrinsics

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CarolineConcatto reviewed Nov 25, 2025

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CarolineConcatto reviewed Nov 26, 2025

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Fix frint intrinsics and formatting errors

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CarolineConcatto mentioned this pull request Dec 2, 2025

[Clang][LLVM][AArch64] Add support for FCVTXNT, FCVTLT, {B}FCVTNT int… llvm/llvm-project#170356

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		Scalar index of first/last true predicate element (predicated).

		These intrinsics can be called from streaming mode if either of the feature


		Copy active vector elements to/from lower-numbered elements.

		These intrinsics can be called from streaming code only if the

Add intrinsics for the FEAT_SVE2p2/FEAT_SME2p2 features introduced by the 2024 dpISA #412

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