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e6d03bb
Homework 2
Sep 23, 2017
e8363d8
Homework 2
Sep 24, 2017
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22 changes: 21 additions & 1 deletion adder.t.v
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Expand Up @@ -6,9 +6,29 @@ module testFullAdder();
reg a, b, carryin;
wire sum, carryout;

behavioralFullAdder adder (sum, carryout, a, b, carryin);
structuralFullAdder adder (sum, carryout, a, b, carryin);

initial begin
// Your test code here
$dumpfile("adder.vcd");
$dumpvars(0, testFullAdder);
$display("a b cin| sum cout | Expected Output");
a=0;b=0;carryin=0; #1000
$display("%b %b %b | %b %b | All false", a, b, carryin, sum, carryout);
a=0;b=1;carryin=0; #1000
$display("%b %b %b | %b %b | sum Only", a, b, carryin, sum, carryout);
a=0;b=0;carryin=1; #1000
$display("%b %b %b | %b %b | sum Only", a, b, carryin, sum, carryout);
a=0;b=1;carryin=1; #1000
$display("%b %b %b | %b %b | carryout Only", a, b, carryin, sum, carryout);
a=1;b=0;carryin=0; #1000
$display("%b %b %b | %b %b | sum Only", a, b, carryin, sum, carryout);
a=1;b=1;carryin=0; #1000
$display("%b %b %b | %b %b | carryout Only", a, b, carryin, sum, carryout);
a=1;b=0;carryin=1; #1000
$display("%b %b %b | %b %b | carryout Only", a, b, carryin, sum, carryout);
a=1;b=1;carryin=1; #1000
$display("%b %b %b | %b %b | All true", a, b, carryin, sum, carryout);

end
endmodule
28 changes: 28 additions & 0 deletions adder.v
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@@ -1,4 +1,8 @@
// Adder circuit
`define AND and #50
`define OR or #50
`define NOT not #50
`define XOR xor #50

module behavioralFullAdder
(
Expand All @@ -21,4 +25,28 @@ module structuralFullAdder
input carryin
);
// Your adder code here
wire AandB;
wire AandBandCin;
wire AandCin;
wire BandCin;
wire AxorB;
wire AxorB_xorCin;
wire notCin;
wire preCout1;
wire preCout2;

`AND andgate1(AandB, a, b);
`AND andgate2(AandCin, a, carryin);
`AND andgate2(BandCin, b, carryin);

`AND s_andgate1(AandBandCin, AandB, carryin);
`XOR xorgate1(AxorB, a, b);
`XOR xorgate2(AxorB_xorCin, AxorB, carryin);
`OR s_orgate(sum, AandBandCin, AxorB_xorCin);

`NOT not_cgate(notCin, carryin);
`OR cout_orgate1(preCout1, AandCin, BandCin);
`AND cout_andgate2(preCout2, notCin, AandB);
`OR cout_orgate2(carryout, preCout1, preCout2);

endmodule
38 changes: 20 additions & 18 deletions decoder.t.v
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Expand Up @@ -7,27 +7,29 @@ module testDecoder ();
reg enable;
wire out0,out1,out2,out3;

behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
//structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing

initial begin
$display("En A0 A1| O0 O1 O2 O3 | Expected Output");
enable=0;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
$dumpfile("decoder.vcd");
$dumpvars(0, testDecoder);
$display("En A0 A1| O0 O1 O2 O3 | Expected Output");
enable=0;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
end

endmodule
20 changes: 20 additions & 0 deletions decoder.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
// Decoder circuit
`define AND and #50
`define NOT not #50

module behavioralDecoder
(
Expand All @@ -18,5 +20,23 @@ module structuralDecoder
input enable
);
// Your decoder code here
wire notAddr0;
wire notAddr1;
wire preOut0;
wire preOut1;
wire preOut2;
wire preOut3;

`NOT not_addr0(notAddr0, address0);
`NOT not_addr1(notAddr1, address1);
`AND addr_andgate3(preOut0, notAddr0, notAddr1);
`AND addr_andgate1(preOut1, address0, notAddr1);
`AND addr_andgate2(preOut2, notAddr0, address1);
`AND addr_andgate0(preOut3, address0, address1);
`AND out_andgate0(out0, enable, preOut0);
`AND out_andgate1(out1, enable, preOut1);
`AND out_andgate2(out2, enable, preOut2);
`AND out_andgate3(out3, enable, preOut3);

endmodule

142 changes: 142 additions & 0 deletions multiplexer.t.v
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Expand Up @@ -4,4 +4,146 @@

module testMultiplexer ();
// Your test code here
reg addr0, addr1;
reg in0, in1, in2, in3;
wire out;

structuralMultiplexer multiplexer (out, addr0, addr1, in0, in1, in2, in3);

initial begin
$dumpfile("multiplexer.vcd");
$dumpvars(0, testMultiplexer);
$display("addr0 addr1 in0 in1 in2 in3 | out | Expected Output");
addr0=0;addr1=0; in0=0; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=0; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=0; in0=1; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);

addr0=0;addr1=1; in0=0; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=0; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=0;addr1=1; in0=1; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);

addr0=1;addr1=0; in0=0; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=0; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=0; in0=1; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);

addr0=1;addr1=1; in0=0; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=0; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=0; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=0; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=0; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=0; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=1; in2=0; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=1; in2=0; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=1; in2=1; in3=0; #1000
$display("%b %b %b %b %b %b | %b | false", addr0, addr1, in0, in1, in2, in3, out);
addr0=1;addr1=1; in0=1; in1=1; in2=1; in3=1; #1000
$display("%b %b %b %b %b %b | %b | true", addr0, addr1, in0, in1, in2, in3, out);
end
endmodule
31 changes: 31 additions & 0 deletions multiplexer.v
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,7 @@
// Multiplexer circuit
`define AND and #50
`define OR or #50
`define NOT not #50

module behavioralMultiplexer
(
Expand All @@ -20,5 +23,33 @@ module structuralMultiplexer
input in0, in1, in2, in3
);
// Your multiplexer code here
wire notAddr0;
wire notAddr1;
wire andAddr0;
wire andAddr1;
wire andAddr2;
wire andAddr3;

wire postIn0;
wire postIn1;
wire postIn2;
wire postIn3;
wire preOut0;
wire preOut1;

`NOT not_addr0(notAddr0, address0);
`NOT not_addr1(notAddr1, address1);
`AND addr_andgate0(andAddr0, notAddr0, notAddr1);
`AND addr_andgate1(andAddr2, notAddr0, address1);
`AND addr_andgate2(andAddr1, address0, notAddr1);
`AND addr_andgate3(andAddr3, address0, address1);
`AND in0_andgate(postIn0, in0, andAddr0);
`AND in1_andgate(postIn1, in1, andAddr1);
`AND in2_andgate(postIn2, in2, andAddr2);
`AND in3_andgate(postIn3, in3, andAddr3);
`OR orgate1(preOut0, postIn0, postIn1);
`OR orgate2(preOut1, postIn2, postIn3);
`OR orgate3(out, preOut0, preOut1);

endmodule