CompArchFA17 · Joboman555 · Sep 17, 2017 · Sep 17, 2017 · Sep 17, 2017 · Sep 17, 2017
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+*.out
diff --git a/README.md b/README.md
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 # HW 0b010: Verilog Building Blocks
 
-Due: September 23rd
+Jonah Spear
 
-This homework prepares some of the gate level primitives you will use in the design of your processor.  You will reuse these modules in several future designs.  Therefore, the structure and test will be in separate modules.
+The purpose of the homework was to build several digital circucit building-blocks in verilog. All of the code was tested using icarus verilog. 
 
-This homework is to be done individually.
+## Multiplexer
 
-## The Devices
+![Multiplexer Truth Table](/resources/mux_table.png?raw=true)
+![Multiplexer Signal Trace](/resources/mux_test.png?raw=true)
 
-This homework is based on the following three devices:
+## Decoder
 
-1. 2-bit decoder with enable (2+1 inputs, 4 outputs)
-1. 4:1 (four input multiplexer)
-1. 1-bit full adder
+![Decoder Truth Table](/resources/decoder_table.png?raw=true)
+![Decoder Signal Trace](/resources/decoder_test.png?raw=true)
 
-For each of these three devices, you will do the following:
-
-1. Write a test bench to test the functionality of the device.
-1. Test your test bench against my version of the device.
-1. Write your own version of the device.
-1. Test your device against your test bench.
-
-## The Test Benches
-For each device, first write a test bench that verifies the appropriate behavior of your device.  We have already completed this for you for the 2 bit decoder as an example, so you will only have to write the other two.
-
-The test bench should:
-
-1. Instantiate a copy of the device it is testing (Device Under Test = DUT)
-1. Show what the truth table should be
-1. Show what the truth table is
-
-## The Behavioral Devices
-We've provided versions of each of the three devices in a language subset called "Behavioral Verilog".  Use these versions to test your test benches.  Connect the test bench to the device definition provided and verify that your test bench passes with the given behavioral device.
-
-## The Structural Devices
-Create the three devices in Structural Verilog, using only the gate primitives we have already gone over:
-```verilog
-NOT AND NAND OR NOR XOR
-```
-
-Do not use behavioral constructs such as `assign` or `case`.
-
-Give all of your gates a delay of 50 units of time.
-
-## The Write Up
-Create a PDF or Markdown file demonstrating your circuits working correctly. It should contain pictures of your test bench results and your waveforms that clearly show the gate propagation delays.  
-
-## Submission
-Please submit:
-
-1. Your 3 Verilog files
-2. Your writeup as a PDF or Markdown file
-3. The scripts you used to run the tests
-
-Push the work to your repo, then submit a pull request to the course repo (CompArchFA17/HW2) for us to respond to with feedback.
-
-## Hints / Tricks
-
-### Gate delays
-In order to model some sort of delay for our gates, simply put these statements at the top of your Verilog source:
-
-```verilog
-// define gates with delays
-`define AND and #50
-`define OR or #50
-`define NOT not #50
-```
-
-Then, when you go to instantiate an AND, for instance, instead of using just `and`, use `` `AND``. That is, back-tick followed by the define you specified. Think of the back-tick as a macro definition.
-
-That means that the gate, `` `AND``, has a delay of 50 units. Then, in your simulation, you should wait between transitions of the input long enough to allow the signals to propagate to the output of your circuit.
-
-### Signal Declaration
-You need to declare all your inputs and outputs and all the intermediate signals you use in your designs.   Thus, if you have the statement:
-```verilog
-and myandgate(out, in1, in2)
-```
-
-You need to have previously declared `out`, `in1`, and `in2`, to be some sort of physical entity (`wire`, `reg`).
-
-### Tutorials
-There are some Verilog resources listed on the [course website](http://sites.google.com/site/ca17fall/resources/verilog)
+## Adder
 
+![Adder Truth Table](/resources/adder_table.png?raw=true)
+![Adder Signal Trace](/resources/adder_test.png?raw=true)
diff --git a/adder.t.v b/adder.t.v
diff --git a/adder.v b/adder.v
diff --git a/decoder.t.v b/decoder.t.v
diff --git a/decoder.v b/decoder.v
diff --git a/multiplexer.t.v b/multiplexer.t.v
diff --git a/multiplexer.v b/multiplexer.v
diff --git a/resources/adder.vcd b/resources/adder.vcd
@@ -0,0 +1,125 @@
+$date
+	Sun Sep 17 21:41:41 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testFullAdder $end
+$var wire 1 ! carryout $end
+$var wire 1 " sum $end
+$var reg 1 # a $end
+$var reg 1 $ b $end
+$var reg 1 % carryin $end
+$scope module adder $end
+$var wire 1 & _carryin $end
+$var wire 1 ' a $end
+$var wire 1 ( aandb $end
+$var wire 1 ) aorb $end
+$var wire 1 * b $end
+$var wire 1 + carryin $end
+$var wire 1 ! carryout $end
+$var wire 1 , outputIfCarryin $end
+$var wire 1 - outputIf_Carryin $end
+$var wire 1 . s $end
+$var wire 1 " sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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+0(
+0.
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+#100000
+0"
+0,
+#150000
+0!
+#1000000
+1#
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+#2000000
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+1!
+#4000000
+1%
+1+
+0$
+0*
+0#
+0'
+#4050000
+1"
+0&
+1-
+0(
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+0,
+0-
+#4150000
+0!
+#5000000
+1#
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+#5050000
+1.
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+#5100000
+0"
+1-
+#5150000
+1!
+#6000000
+1$
+1*
+0#
+0'
+#7000000
+1#
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+#7050000
+0.
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diff --git a/resources/adder_table.png b/resources/adder_table.png
diff --git a/resources/adder_test.png b/resources/adder_test.png