hw 2 submission

Adder.vcd

@@ -0,0 +1,118 @@
+$date
+	Thu Sep 21 00:00:54 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module behavioralFullAdder $end
+$var wire 1 ! a $end
+$var wire 1 " b $end
+$var wire 1 # carryin $end
+$var wire 1 $ carryout $end
+$var wire 1 % sum $end
+$upscope $end
+$scope module testFullAdder $end
+$var wire 1 & carryout $end
+$var wire 1 ' sum $end
+$var reg 1 ( a $end
+$var reg 1 ) b $end
+$var reg 1 * carryin $end
+$scope module potatoz $end
+$var wire 1 + a $end
+$var wire 1 , aandb $end
+$var wire 1 - axorb $end
+$var wire 1 . b $end
+$var wire 1 / candaxorb $end
+$var wire 1 0 carryin $end
+$var wire 1 & carryout $end
+$var wire 1 ' sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+00
+z/
+0.
+z-
+z,
+0+
+0*
+0)
+0(
+x'
+x&
+x%
+x$
+z#
+z"
+z!
+$end
+#50000
+0/
+0,
+0-
+#100000
+0&
+0'
+#1000000
+1(
+1+
+#1050000
+1-
+#1100000
+1'
+#2000000
+1)
+1.
+0(
+0+
+#3000000
+1(
+1+
+#3050000
+0-
+1,
+#3100000
+0'
+1&
+#4000000
+1*
+10
+0)
+0.
+0(
+0+
+#4050000
+1'
+0,
+#4100000
+0&
+#5000000
+1(
+1+
+#5050000
+1-
+#5100000
+0'
+1/
+#5150000
+1&
+#6000000
+1)
+1.
+0(
+0+
+#7000000
+1(
+1+
+#7050000
+0-
+1,
+#7100000
+1'
+0/
+#8000000

Decoder.vcd

@@ -0,0 +1,162 @@
+$date
+	Thu Sep 21 00:01:30 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module behavioralDecoder $end
+$var wire 1 ! address0 $end
+$var wire 1 " address1 $end
+$var wire 1 # enable $end
+$var wire 1 $ out0 $end
+$var wire 1 % out1 $end
+$var wire 1 & out2 $end
+$var wire 1 ' out3 $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 ( out0 $end
+$var wire 1 ) out1 $end
+$var wire 1 * out2 $end
+$var wire 1 + out3 $end
+$var reg 1 , addr0 $end
+$var reg 1 - addr1 $end
+$var reg 1 . enable $end
+$scope module decode $end
+$var wire 1 / A0 $end
+$var wire 1 0 A0andA1 $end
+$var wire 1 1 A0andnA1 $end
+$var wire 1 2 A1 $end
+$var wire 1 3 enable $end
+$var wire 1 4 nA0 $end
+$var wire 1 5 nA0andA1 $end
+$var wire 1 6 nA0andnA1 $end
+$var wire 1 7 nA1 $end
+$var wire 1 ( out0 $end
+$var wire 1 ) out1 $end
+$var wire 1 * out2 $end
+$var wire 1 + out3 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z7
+x6
+z5
+z4
+03
+02
+z1
+z0
+0/
+0.
+0-
+0,
+z+
+z*
+z)
+z(
+x'
+x&
+x%
+x$
+z#
+z"
+z!
+$end
+#50000
+0+
+0*
+0)
+0(
+00
+05
+01
+14
+17
+#100000
+16
+#1000000
+1,
+1/
+#1050000
+04
+11
+#1100000
+06
+#2000000
+1-
+12
+0,
+0/
+#2050000
+07
+14
+01
+#2100000
+15
+#3000000
+1,
+1/
+#3050000
+04
+10
+#3100000
+05
+#4000000
+0-
+02
+0,
+0/
+1.
+13
+#4050000
+17
+14
+00
+1+
+#4100000
+16
+0+
+#4150000
+1(
+#5000000
+1,
+1/
+#5050000
+04
+11
+#5100000
+06
+1)
+#5150000
+0(
+#6000000
+1-
+12
+0,
+0/
+#6050000
+07
+14
+01
+#6100000
+15
+0)
+#6150000
+1*
+#7000000
+1,
+1/
+#7050000
+04
+10
+#7100000
+05
+1+
+#7150000
+0*
+#8000000