HW2 Submission

.gitignore

@@ -0,0 +1,2 @@
+*.vcd
+*.out

WRITEUP.md

@@ -0,0 +1,70 @@
+# HW2 Write Up
+## Alexander Hoppe
+
+## 2-bit Decoder w/ Enable
+The decoder is two stages of a simple signal splitting unit. The basic unit is a pair of `AND` gates connected to the signal that is being "split", and with their other inputs tied to a selector signal and its inversion. Cascading two of these stages in a row allows the `Enable` signal to be "split" into four different outputs.
+
+### Test Bench Output
+```
+En A0 A1| O0 O1 O2 O3 | Expected Output
+0  0  0 |  0  0  0  0 | All false
+0  1  0 |  0  0  0  0 | All false
+0  0  1 |  0  0  0  0 | All false
+0  1  1 |  0  0  0  0 | All false
+1  0  0 |  1  0  0  0 | O0 Only
+1  1  0 |  0  1  0  0 | O1 Only
+1  0  1 |  0  0  1  0 | O2 Only
+1  1  1 |  0  0  0  1 | O3 Only
+```
+### Waveforms
+![decoder.png](decoder.png)
+
+## 4-bit Multiplexer
+The multiplexer is two stages of selectors cascaded together, similar to the decoder. The selector unit is comprised of two `AND` gates each connected to an input and a selector signal or its inverse. To avoid the `AND` gates fighting an output, their outputs are `OR`ed together. In this way, `n` input signals can select between `2^n` outputs.
+
+### Test Bench Output
+```
+A1 A0 | I0 I1 I2 I3  |  O | Expected Output
+0  0  |  0  x  x  x  |  0 | Input 0
+0  0  |  1  x  x  x  |  1 | Input 0
+0  1  |  x  0  x  x  |  0 | Input 1
+0  1  |  x  1  x  x  |  1 | Input 1
+1  0  |  x  x  0  x  |  0 | Input 2
+1  0  |  x  x  1  x  |  1 | Input 2
+1  1  |  x  x  x  0  |  0 | Input 3
+1  1  |  x  x  x  1  |  1 | Input 3
+```
+
+### Waveforms
+![multiplexer.png](multiplexer.png)
+
+## 1-bit Full Adder
+The 1-bit adder required two different stages. I first developed the stage to create the sum, `S`, which is `(A XOR B) XOR Cin`. I realized that `S` was `A XOR B` when `Cin` was 0, and it was the inverse of that when `Cin` was 1. By making a truth table, I realized that `XOR` can be used like an inverter with an enable function:
+
+```
+Inverter    
+w/ Enable   XOR
+I  E | O    A  B | A XOR B
+0  0 | 0    0  0 | 0
+1  0 | 1    1  0 | 1
+0  1 | 1    0  1 | 1
+1  1 | 0    1  1 | 0
+```
+
+The next stage was to create `Cout`, which I figured out to be `AB + (A XOR B)Cin` by looking at the full truth table.
+
+### Test Bench Output
+```
+A  B  Cin | S Cout | Expected Output
+0  0   0  | 0   0  | 0  0
+0  1   0  | 1   0  | 1  0
+1  0   0  | 1   0  | 1  0
+1  1   0  | 0   1  | 0  1
+0  0   1  | 1   0  | 1  0
+0  1   1  | 0   1  | 0  1
+1  0   1  | 0   1  | 0  1
+1  1   1  | 1   1  | 1  1
+```
+
+### Waveforms
+![adder.png](adder.png)

adder.t.v

@@ -6,9 +6,28 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    // behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+        $dumpfile("adder.vcd");
+        $dumpvars(0,adder);
+        $display("A  B  Cin | S Cout | Expected Output");
+        a=0;b=0;carryin=0; #1000
+        $display("%b  %b   %b  | %b   %b  | 0  0", a, b, carryin, sum, carryout);
+        a=0;b=1;carryin=0; #1000
+        $display("%b  %b   %b  | %b   %b  | 1  0", a, b, carryin, sum, carryout);
+        a=1;b=0;carryin=0; #1000
+        $display("%b  %b   %b  | %b   %b  | 1  0", a, b, carryin, sum, carryout);
+        a=1;b=1;carryin=0; #1000
+        $display("%b  %b   %b  | %b   %b  | 0  1", a, b, carryin, sum, carryout);
+        a=0;b=0;carryin=1; #1000
+        $display("%b  %b   %b  | %b   %b  | 1  0", a, b, carryin, sum, carryout);
+        a=0;b=1;carryin=1; #1000
+        $display("%b  %b   %b  | %b   %b  | 0  1", a, b, carryin, sum, carryout);
+        a=1;b=0;carryin=1; #1000
+        $display("%b  %b   %b  | %b   %b  | 0  1", a, b, carryin, sum, carryout);
+        a=1;b=1;carryin=1; #1000
+        $display("%b  %b   %b  | %b   %b  | 1  1", a, b, carryin, sum, carryout);
     end
 endmodule

adder.v

@@ -1,11 +1,15 @@
 // Adder circuit
 
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+
 module behavioralFullAdder
 (
-    output sum, 
+    output sum,
     output carryout,
-    input a, 
-    input b, 
+    input a,
+    input b,
     input carryin
 );
     // Uses concatenation operator and built-in '+'
@@ -14,11 +18,18 @@ endmodule
 
 module structuralFullAdder
 (
-    output sum, 
+    output sum,
     output carryout,
-    input a, 
-    input b, 
+    input a,
+    input b,
     input carryin
 );
-    // Your adder code here
+    wire axorb, axorb_andcarryin, aandb;
+
+    `XOR xorab (axorb, a, b);
+    `XOR xorsumout (sum, carryin, axorb);
+    `AND andab (aandb, a, b);
+    `AND andaxorbcarryin (axorb_andcarryin, axorb, carryin);
+    `OR orcarryout (carryout, aandb, axorb_andcarryin);
+
 endmodule

decoder.t.v

@@ -2,31 +2,33 @@
 `timescale 1 ns / 1 ps
 `include "decoder.v"
 
-module testDecoder (); 
+module testDecoder ();
     reg addr0, addr1;
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars(0,decoder);
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
+    enable=0;addr0=0;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
     enable=0;addr0=1;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
+    enable=0;addr0=0;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
+    enable=0;addr0=1;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
+    enable=1;addr0=0;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
+    enable=1;addr0=1;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
+    enable=1;addr0=0;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
+    enable=1;addr0=1;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
     end
 

decoder.v

@@ -1,5 +1,12 @@
 // Decoder circuit
 
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define NAND nand #50
+`define NOR nor #50
+`define XOR xor #50
+
 module behavioralDecoder
 (
     output out0, out1, out2, out3,
@@ -17,6 +24,16 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
-endmodule
+    wire A, B, _address0, _address1;
+
+    `NOT add0inv(_address0, address0);
+    `NOT add1inv(_address1, address1);
 
+    `AND add1low(A, enable, _address1);
+    `AND add1high(B, enable, address1);
+
+    `AND add0lowlow(out0, A, _address0);
+    `AND add0lowhigh(out1, A, address0);
+    `AND add0highlow(out2, B, _address0);
+    `AND add0highhigh(out3, B, address0);
+endmodule

multiplexer.t.v

@@ -3,5 +3,35 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
+    reg addr0, addr1, in0, in1, in2, in3;
+    wire out;
+
+    // behavioralMultiplexer multiplexer (out,addr0, addr1, in0, in1, in2, in3);
+    structuralMultiplexer multiplexer (out, addr0, addr1, in0, in1, in2, in3); // Swap after testing
+
+    initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0,multiplexer);
+    $display("A1 A0 | I0 I1 I2 I3  |  O | Expected Output");
+    addr0=0;addr1=0;in0=0;in1=1'bX;in2=1'bX;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 0", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=0;addr1=0;in0=1;in1=1'bX;in2=1'bX;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 0", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in0=1'bX;in1=0;in2=1'bX;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 1", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in0=1'bX;in1=1;in2=1'bX;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 1", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in0=1'bX;in1=1'bX;in2=0;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 2", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in0=1'bX;in1=1'bX;in2=1;in3=1'bX; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 2", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in0=1'bX;in1=1'bX;in2=1'bX;in3=0; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 3", addr1, addr0, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in0=1'bX;in1=1'bX;in2=1'bX;in3=1; #1000
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | Input 3", addr1, addr0, in0, in1, in2, in3, out);
+    end
+
+
+
   // Your test code here
 endmodule

multiplexer.v

@@ -1,5 +1,9 @@
 // Multiplexer circuit
 
+`define NOT not #50
+`define AND and #50
+`define OR or #50
+
 module behavioralMultiplexer
 (
     output out,
@@ -19,6 +23,21 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
-endmodule
+    wire A, B, _address0, _address1, in0sel, in1sel, in2sel, in3sel, Aout, Bout, A1lowout, A1highout;
+
+    `NOT add0inv(_address0, address0);
+    `NOT add1inv(_address1, address1);
+
+    `AND in0sel (in0sel, in0, _address0);
+    `AND in1sel (in1sel, in1, address0);
+    `AND in2sel (in2sel, in2, _address0);
+    `AND in3sel (in3sel, in3, address0);
 
+    `OR A (Aout, in0sel, in1sel);
+    `OR B (Bout, in2sel, in3sel);
+
+    `AND A1low(A1lowout, Aout, _address1);
+    `AND A1high(A1highout, Bout, address1);
+
+    `OR out (out, A1lowout, A1highout);
+endmodule