submitting HW2

adder.t.v

@@ -6,9 +6,44 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+        $dumpfile("adder.vcb");
+        $dumpvars;
+
+        $display("a  b  carryin  |  carryout  sum  |  expected");
+
+        a=0; b=0; carryin=0; #1000
+        $display("%b  %b     %b     |     %b       %b   |   0  0",
+        a, b, carryin, carryout, sum);
+
+        a=0; b=0; carryin=1; #1000
+        $display("%b  %b     %b     |     %b       %b   |   0  1",
+        a, b, carryin, carryout, sum);
+
+        a=0; b=1; carryin=0; #1000
+        $display("%b  %b     %b     |     %b       %b   |   0  1",
+        a, b, carryin, carryout, sum);
+
+        a=0; b=1; carryin=1; #1000
+        $display("%b  %b     %b     |     %b       %b   |   1  0",
+        a, b, carryin, carryout, sum);
+
+        a=1; b=0; carryin=0; #1000
+        $display("%b  %b     %b     |     %b       %b   |   0  1",
+        a, b, carryin, carryout, sum);
+
+        a=1; b=0; carryin=1; #1000
+        $display("%b  %b     %b     |     %b       %b   |   1  0",
+        a, b, carryin, carryout, sum);
+
+        a=1; b=1; carryin=0; #1000
+        $display("%b  %b     %b     |     %b       %b   |   1  0",
+        a, b, carryin, carryout, sum);
+
+        a=1; b=1; carryin=1; #1000
+        $display("%b  %b     %b     |     %b       %b   |   1  1",
+        a, b, carryin, carryout, sum);
     end
 endmodule

adder.v

@@ -1,4 +1,10 @@
 // Adder circuit
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
+
 
 module behavioralFullAdder
 (
@@ -12,6 +18,30 @@ module behavioralFullAdder
     assign {carryout, sum}=a+b+carryin;
 endmodule
 
+
+
+// define XOR gate from primatives
+// No delay is necessary since primatives already contain delay
+module XOR
+(
+    output out,
+    input in,
+    input in1
+);
+
+wire nA;
+wire nB;
+wire AnB;
+wire BnA;
+`NOT(nA,in);
+`NOT(nB,in1);
+`AND(AnB,in,nB);
+`AND(BnA,nA,in1);
+`OR(out,AnB,BnA);
+endmodule
+
+
+
 module structuralFullAdder
 (
     output sum, 
@@ -20,5 +50,18 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire BCin;
+    wire ACin;
+    wire AB;
+
+    wire BxorCin;
+
+    `AND(BCin,b,carryin);
+    `AND(ACin,a,carryin);
+    `AND(AB, a, b);
+    `OR(carryout,BCin,ACin,AB);
+
+   XOR xor0(BxorCin,b,carryin);
+   XOR xor1(sum,a,BxorCin);
+
 endmodule

decoder.t.v

@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars;
+
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
@@ -26,7 +28,7 @@ module testDecoder ();
     $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
     enable=1;addr0=0;addr1=1; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
+    enable=1;addr0=1;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
     end
 

decoder.v

@@ -1,4 +1,9 @@
 // Decoder circuit
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 
 module behavioralDecoder
 (
@@ -17,6 +22,14 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+    wire n0;
+    wire n1;
+
+    `NOT a0(n0, address0);
+    `NOT a1(n1, address1);
+    `AND n0n1(out0,n0,n1,enable);
+    `AND a0n1(out1,address0,n1,enable);
+    `AND n0a1(out2,n0,address1,enable);
+    `AND a0a1(out3,address0,address1,enable);
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,50 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  reg addr0, addr1;
+  reg in0, in1, in2, in3;
+  wire out;
+  integer i;
+  integer j;
+  integer k;
+  integer l;
+  integer m;
+  integer n;
+
+  structuralMultiplexer multiplexer1 (out,addr0,addr1,in0,in1,in2,in3);
+
+    initial begin
+
+    $dumpfile("multiplexer.vcd");
+    $dumpvars;
+
+    $display("Expected Value = in3 for addr = 00");
+    $display("Expected Value = in2 for addr = 01");
+    $display("Expected Value = in1 for addr = 10");
+    $display("Expected Value = in0 for addr = 11");
+
+
+    $display("addr0 addr1 | in0  in1  in2  in3  |  out");
+
+    for(i=0; i<2; i=i+1) begin
+    	for(j=0; j<2; j=j+1) begin
+    		for(k=0; k<2; k=k+1) begin
+    			for(l=0; l<2; l=l+1) begin
+    				for(m=0; m<2; m=m+1) begin
+    					for(n=0; n<2; n=n+1) begin
+
+addr1=i; addr0=j; in3=k; in2=l; in1=m; in0=n; #1000
+$display("  %b     %b   |  %b    %b    %b    %b   |   %b", addr1, addr0, in3, in2,  in1, in0, out);
+
+    					end
+    				end
+    			end
+    		end
+    		$display("");
+    		$display(""); //split up each address into separate truth tables for easier reading
+    	end
+    end
+
+end
+
 endmodule

multiplexer.v

@@ -1,4 +1,9 @@
 // Multiplexer circuit
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 
 module behavioralMultiplexer
 (
@@ -19,6 +24,22 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+
+wire naddress0;
+wire naddress1;
+wire d0;
+wire d1;
+wire d2;
+wire d3;
+
+`NOT(naddress0,address0);
+`NOT(naddress1,address1);
+`AND(d0,in0,naddress0,naddress1);
+`AND(d1,in1,address0,naddress1);
+`AND(d2,in2,naddress0,address1);
+`AND(d3,in3,address0,address1);
+`OR(out,d0,d1,d2,d3);
+
+
 endmodule