Completed HW 2

Writeup.md

@@ -0,0 +1,43 @@
+# Homework 2
+## Tobias Shapinsky
+
+### Multiplexer
+Results:
+```
+A0 A1 | I0 I1 I2 I3 | Out | Expected Out
+0  0  | 1  0  1  0  | 1   | 1
+1  0  | 1  0  1  0  | 0   | 0
+0  1  | 1  0  1  0  | 1   | 1
+1  1  | 1  0  1  0  | 0   | 0
+```
+![multiplexer](https://github.com/TShapinsky/HW2/blob/master/multiplexer.PNG?raw=true)
+
+### Decoder
+Results:
+```
+En A0 A1| O0 O1 O2 O3 | Expected Output
+0  0  0 |  0  0  0  0 | All false
+0  1  0 |  0  0  0  0 | All false
+0  0  1 |  0  0  0  0 | All false
+0  1  1 |  0  0  0  0 | All false
+1  0  0 |  1  0  0  0 | O0 Only
+1  1  0 |  0  1  0  0 | O1 Only
+1  0  1 |  0  0  1  0 | O2 Only
+1  1  1 |  0  0  0  1 | O3 Only
+```
+![decoder](https://github.com/TShapinsky/HW2/blob/master/decoder.png?raw=true)
+
+### Adder
+Reults:
+```
+A B Cin | S Cout | Expected
+0 0 0   | 0 0    | 0 0
+0 0 1   | 1 0    | 1 0
+0 1 0   | 1 0    | 1 0
+0 1 1   | 0 1    | 0 1
+1 0 0   | 1 0    | 1 0
+1 0 1   | 0 1    | 0 1
+1 1 0   | 0 1    | 0 1
+1 1 1   | 1 1    | 1 1
+```
+![adder](https://github.com/TShapinsky/HW2/blob/master/adder.PNG?raw=true)

adder.t.v

@@ -6,9 +6,43 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+       $dumpfile("adder.vcd");
+       $dumpvars;
+       $display("A B Cin | S Cout | Expected");
+       a=0;
+       b=0;
+       carryin=0; #1000
+       $display("%b %b %b   | %b %b    | 0 0", a, b, carryin, sum, carryout);
+       a=0;
+       b=0;
+       carryin=1; #1000
+       $display("%b %b %b   | %b %b    | 1 0", a, b, carryin, sum, carryout);
+       a=0;
+       b=1;
+       carryin=0; #1000
+       $display("%b %b %b   | %b %b    | 1 0", a, b, carryin, sum, carryout);
+       a=0;
+       b=1;
+       carryin=1; #1000
+       $display("%b %b %b   | %b %b    | 0 1", a, b, carryin, sum, carryout);
+       a=1;
+       b=0;
+       carryin=0; #1000
+       $display("%b %b %b   | %b %b    | 1 0", a, b, carryin, sum, carryout);
+       a=1;
+       b=0;
+       carryin=1; #1000
+       $display("%b %b %b   | %b %b    | 0 1", a, b, carryin, sum, carryout);
+       a=1;
+       b=1;
+       carryin=0; #1000
+       $display("%b %b %b   | %b %b    | 0 1", a, b, carryin, sum, carryout);
+       a=1;
+       b=1;
+       carryin=1; #1000
+       $display("%b %b %b   | %b %b    | 1 1", a, b, carryin, sum, carryout);
     end
 endmodule

adder.v

@@ -1,5 +1,9 @@
 // Adder circuit
-
+//define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
 module behavioralFullAdder
 (
     output sum, 
@@ -20,5 +24,15 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+   wire   absum;
+   wire   abcarry;
+   wire   carrycarry;
+
+
+   `XOR xorab(absum, a, b);
+   `XOR xorsum(sum, absum, carryin);
+   `AND andab(abcarry, a, b);
+   `AND andcc(carrycarry, absum, carryin);
+   `OR  orcarry(carryout, carrycarry, abcarry);
+
 endmodule

decoder.t.v

@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+       $dumpfile("decoder.vcd");
+       $dumpvars;
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);

decoder.v

@@ -1,5 +1,8 @@
 // Decoder circuit
-
+//define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
 module behavioralDecoder
 (
     output out0, out1, out2, out3,
@@ -17,6 +20,24 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+   wire   A0_;
+   wire   A1_;
+   wire   en0;
+   wire   en1;
+   wire   en2;
+   wire   en3;
+
+
+   `NOT nA0(A0_, address0);
+   `NOT nA1(A1_, address1);
+   `AND E00(en0, A0_, A1_);
+   `AND E01(en1, address0, A1_);
+   `AND E02(en2, A0_, address1);
+   `AND E03(en3, address0, address1);
+   `AND O0(out0, enable, en0);
+   `AND O1(out1, enable, en1);
+   `AND O2(out2, enable, en2);
+   `AND O3(out3, enable, en3);   
+
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,24 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+   reg addr0, addr1, in0, in1, in2, in3;
+   wire out;
+   //behavioralMultiplexer multiplexer(out, addr0, addr1, in0, in1, in2, in3);
+   structuralMultiplexer multiplexer(out, addr0, addr1, in0, in1, in2, in3);
+
+
+   initial begin
+      $dumpfile("multiplexer.vcd");
+      $dumpvars;
+
+      $display("A0 A1 | I0 I1 I2 I3 | Out | Expected Out");
+      addr0=0;addr1=0;in0=1;in1=0;in2=1;in3=0;#1000
+      $display("%b  %b  | %b  %b  %b  %b  | %b   | 1", addr0, addr1, in0, in1, in2, in3, out);
+      addr0=1;addr1=0;in0=1;in1=0;in2=1;in3=0;#1000
+      $display("%b  %b  | %b  %b  %b  %b  | %b   | 0", addr0, addr1, in0, in1, in2, in3, out);
+      addr0=0;addr1=1;in0=1;in1=0;in2=1;in3=0;#1000
+      $display("%b  %b  | %b  %b  %b  %b  | %b   | 1", addr0, addr1, in0, in1, in2, in3, out);
+      addr0=1;addr1=1;in0=1;in1=0;in2=1;in3=0;#1000
+      $display("%b  %b  | %b  %b  %b  %b  | %b   | 0", addr0, addr1, in0, in1, in2, in3, out);
+   end
 endmodule

multiplexer.v

@@ -1,5 +1,8 @@
 // Multiplexer circuit
-
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
 module behavioralMultiplexer
 (
     output out,
@@ -19,6 +22,36 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+   wire   A0_;
+   wire   A1_;
+   wire   en0;
+   wire   en1;
+   wire   en2;
+   wire   en3;
+   wire   out0;
+   wire   out1;
+   wire   out2;
+   wire   out3;
+   wire   out01;
+   wire   out23;
+
+
+
+
+   `NOT nA0(A0_, address0);
+   `NOT nA1(A1_, address1);
+   `AND E00(en0, A0_, A1_);
+   `AND E01(en1, address0, A1_);
+   `AND E02(en2, A0_, address1);
+   `AND E03(en3, address0, address1);
+   `AND O0(out0, in0, en0);
+   `AND O1(out1, in1, en1);
+   `AND O2(out2, in2, en2);
+   `AND O3(out3, in3, en3);
+   `OR O01(out01, out0, out1);
+   `OR O23(out23, out2, out3);
+   `OR O0123(out, out01, out23);
+
+
 endmodule