Turning in HW4

Makefile

@@ -0,0 +1,8 @@
+test: build
+	./regfile
+
+build: regfile.t.v regfile.v gates.v register.v decoders.v
+	iverilog -o regfile regfile.t.v
+
+clean:
+	rm alu

decoders.v

@@ -8,7 +8,6 @@ input		enable,
 input[4:0]	address
 );
 
-    assign out = enable<<address; 
+    assign out = enable<<address;
 
 endmodule
-

gates.v

@@ -0,0 +1,78 @@
+`include "register.v"
+`include "decoders.v"
+
+//Deliverable 2:
+module register32(output[31:0] q,
+                  input[31:0] d, input wrenable, input clk);
+
+  genvar i;
+  generate
+    for(i=0; i<32; i=i+1) begin: bits
+      register reg_inst(q[i], d[i], wrenable, clk);
+    end
+  endgenerate
+
+endmodule
+
+//Deliverable 3:
+module register32zero(output[31:0] q,
+                      input[31:0] d, input wrenable, input clk);
+  assign q[31:0] = 0;
+endmodule
+
+//Deliverable 4:
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+  assign out = inputs[address];
+endmodule
+
+//Deliverable 5
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0,input1,input2,input3,input4,input5,input6,input7,
+              input8,input9,input10,input11,input12,input13,input14,input15,
+              input16,input17,input18,input19,input20,input21,input22,input23,
+              input24,input25,input26,input27,input28,input29,input30,input31
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = input0;
+  assign mux[1] = input1;
+  assign mux[2] = input2;
+  assign mux[3] = input3;
+  assign mux[4] = input4;
+  assign mux[5] = input5;
+  assign mux[6] = input6;
+  assign mux[7] = input7;
+  assign mux[8] = input8;
+  assign mux[9] = input9;
+  assign mux[10] = input10;
+  assign mux[11] = input11;
+  assign mux[12] = input12;
+  assign mux[13] = input13;
+  assign mux[14] = input14;
+  assign mux[15] = input15;
+  assign mux[16] = input16;
+  assign mux[17] = input17;
+  assign mux[18] = input18;
+  assign mux[19] = input19;
+  assign mux[20] = input20;
+  assign mux[21] = input21;
+  assign mux[22] = input22;
+  assign mux[23] = input23;
+  assign mux[24] = input24;
+  assign mux[25] = input25;
+  assign mux[26] = input26;
+  assign mux[27] = input27;
+  assign mux[28] = input28;
+  assign mux[29] = input29;
+  assign mux[30] = input30;
+  assign mux[31] = input31;
+  assign out = mux[address];	// Connect the output of the array
+endmodule

regfile.t.v

@@ -1,5 +1,6 @@
+`include "regfile.v"
 //------------------------------------------------------------------------------
-// Test harness validates hw4testbench by connecting it to various functional 
+// Test harness validates hw4testbench by connecting it to various functional
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
@@ -34,15 +35,15 @@ module hw4testbenchharness();
   hw4testbench tester
   (
     .begintest(begintest),
-    .endtest(endtest), 
+    .endtest(endtest),
     .dutpassed(dutpassed),
     .ReadData1(ReadData1),
     .ReadData2(ReadData2),
-    .WriteData(WriteData), 
-    .ReadRegister1(ReadRegister1), 
+    .WriteData(WriteData),
+    .ReadRegister1(ReadRegister1),
     .ReadRegister2(ReadRegister2),
     .WriteRegister(WriteRegister),
-    .RegWrite(RegWrite), 
+    .RegWrite(RegWrite),
     .Clk(Clk)
   );
 
@@ -90,8 +91,6 @@ output reg[4:0]		WriteRegister,
 output reg		RegWrite,
 output reg		Clk
 );
-
-  // Initialize register driver signals
   initial begin
     WriteData=32'd0;
     ReadRegister1=5'd0;
@@ -107,7 +106,7 @@ output reg		Clk
     dutpassed = 1;
     #10
 
-  // Test Case 1: 
+  // Test Case 1:
   //   Write '42' to register 2, verify with Read Ports 1 and 2
   //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
@@ -116,14 +115,15 @@ output reg		Clk
   ReadRegister1 = 5'd2;
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
+  #5
 
   // Verify expectations and report test result
-  if((ReadData1 != 42) || (ReadData2 != 42)) begin
+  if((ReadData1 != 42) || (ReadData2 != 42) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
     dutpassed = 0;	// Set to 'false' on failure
     $display("Test Case 1 Failed");
   end
 
-  // Test Case 2: 
+  // Test Case 2:
   //   Write '15' to register 2, verify with Read Ports 1 and 2
   //   (Fails with example register file, but should pass with yours)
   WriteRegister = 5'd2;
@@ -133,16 +133,90 @@ output reg		Clk
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;
 
-  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+  if((ReadData1 != 15) || (ReadData2 != 15) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
     dutpassed = 0;
     $display("Test Case 2 Failed");
   end
 
+  //Deliverable 8
+
+  //test case 3:
+  //  disable regWrite, write '16' to register 2, verify with
+  //  read ports 1 and 2 that the value has not changed
+  RegWrite = 0;
+  WriteData = 32'd16;
+  WriteRegister = 5'd2;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 16) || (ReadData2 == 16) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+  //test case 4:
+  //  enable regWrite, write '17 to register 3, verify with
+  //  ports 1 and 2 that register 2 is not 16
+  WriteData = 32'd17;
+  WriteRegister = 5'd3;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 17) || (ReadData2 == 17) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+  //test case 5:
+  //  enable regWrite, write '18' to register 0 verify with
+  //  ports 1 and 2 that it is still 0
+  WriteData = 32'd18;
+  WriteRegister = 5'd0;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData2 != 0) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+  //test case 6:
+  //  write '19' to register 1, verify that ports 1 and two read
+  //  correctly. Then write '20' to register 2, Verify that ports
+  //  1 and 2 read correctly
+  WriteData = 32'd19;
+  WriteRegister = 5'd1;
+  ReadRegister1 = 5'd1;
+  ReadRegister2 = 5'd1;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 19) || (ReadData2 != 19) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
+    dutpassed = 0;
+    $display("Test Case 6 Failed");
+  end
+
+  WriteData = 32'd20;
+  WriteRegister = 5'd2;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 20) || (ReadData2 != 20) || ^ReadData1 === 1'bX || ^ReadData2 === 1'bX) begin
+    dutpassed = 0;
+    $display("Test Case 6 Failed");
+  end
 
   // All done!  Wait a moment and signal test completion.
   #5
   endtest = 1;
 
 end
 
-endmodule
+endmodule

regfile.v

@@ -1,3 +1,5 @@
+`include "gates.v"
+
 //------------------------------------------------------------------------------
 // MIPS register file
 //   width: 32 bits
@@ -17,11 +19,23 @@ input[4:0]	WriteRegister,	// Address of register to write
 input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
+  genvar i;
+  wire[31:0] wrEn;
+  wire[31:0] bus[31:0];
+  decoder1to32 wrEnDecode(wrEn, RegWrite, WriteRegister);
+  mux32to1by32 port1Mux(ReadData1, ReadRegister1, bus[0],  bus[1],  bus[2],  bus[3],  bus[4],  bus[5],  bus[6],  bus[7],
+                                                      bus[8], bus[9],  bus[10],  bus[11],  bus[12],  bus[13],  bus[14],  bus[15],
+                                                      bus[16],  bus[17],  bus[18],  bus[19],  bus[20],  bus[21],  bus[22],  bus[23],
+                                                      bus[24],  bus[25],  bus[26],  bus[27],  bus[28],  bus[29],  bus[30],  bus[31]);
+  mux32to1by32 port2Mux(ReadData2, ReadRegister2, bus[0],  bus[1],  bus[2],  bus[3],  bus[4],  bus[5],  bus[6],  bus[7],
+                                                      bus[8], bus[9],  bus[10],  bus[11],  bus[12],  bus[13],  bus[14],  bus[15],
+                                                      bus[16],  bus[17],  bus[18],  bus[19],  bus[20],  bus[21],  bus[22],  bus[23],
+                                                      bus[24],  bus[25],  bus[26],  bus[27],  bus[28],  bus[29],  bus[30],  bus[31]);
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
-
-endmodule
+  register32zero zeroReg(bus[0], WriteData, wrEn[0], Clk);
+  generate
+    for(i=1; i<32; i=i+1) begin: registers
+      register32 reg_inst(bus[i], WriteData, wrEn[i], Clk);
+    end
+  endgenerate
+endmodule

register.v

@@ -14,4 +14,4 @@ input		clk
         end
     end
 
-endmodule
+endmodule