Turning in HW4!

deliverable6.txt

@@ -0,0 +1,9 @@
+Deliverable 6
+
+This module shifts the enable bit left based on the address, until enable is
+stored in the address. The value of enable will be stored in output (specifically,
+in output[address]). All the other bits will be set to zero. Thus when enable is 1,
+then 1 will be stored in output[address] and all other values will be set to zero.
+This corresponds to the same behavior as a decoder, where at most only one value
+is 1 (if enable = 1) in order to select an option (otherwise if enable = 1,
+everything will be 0).

muxes.v

@@ -0,0 +1,52 @@
+module mux32to1by1
+(
+output		out,
+input[4:0]	address,
+input[31:0]	inputs
+);
+  assign out = inputs[address];
+endmodule
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = input0;		// Connect the sources of the array
+  assign mux[1] = input1;
+  assign mux[2] = input2;
+  assign mux[3] = input3;
+  assign mux[4] = input4;
+  assign mux[5] = input5;
+  assign mux[6] = input6;
+  assign mux[7] = input7;
+  assign mux[8] = input8;
+  assign mux[9] = input9;
+  assign mux[10] = input10;
+  assign mux[11] = input11;
+  assign mux[12] = input12;
+  assign mux[13] = input13;
+  assign mux[14] = input14;
+  assign mux[15] = input15;
+  assign mux[16] = input16;
+  assign mux[17] = input17;
+  assign mux[18] = input18;
+  assign mux[19] = input19;
+  assign mux[20] = input20;
+  assign mux[21] = input21;
+  assign mux[22] = input22;
+  assign mux[23] = input23;
+  assign mux[24] = input24;
+  assign mux[25] = input25;
+  assign mux[26] = input26;
+  assign mux[27] = input27;
+  assign mux[28] = input28;
+  assign mux[29] = input29;
+  assign mux[30] = input30;
+  assign mux[31] = input31;
+  assign out = mux[address];	// Connect the output of the array
+
+endmodule

regfile.t.v

@@ -1,8 +1,10 @@
 //------------------------------------------------------------------------------
-// Test harness validates hw4testbench by connecting it to various functional 
+// Test harness validates hw4testbench by connecting it to various functional
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -34,15 +36,15 @@ module hw4testbenchharness();
   hw4testbench tester
   (
     .begintest(begintest),
-    .endtest(endtest), 
+    .endtest(endtest),
     .dutpassed(dutpassed),
     .ReadData1(ReadData1),
     .ReadData2(ReadData2),
-    .WriteData(WriteData), 
-    .ReadRegister1(ReadRegister1), 
+    .WriteData(WriteData),
+    .ReadRegister1(ReadRegister1),
     .ReadRegister2(ReadRegister2),
     .WriteRegister(WriteRegister),
-    .RegWrite(RegWrite), 
+    .RegWrite(RegWrite),
     .Clk(Clk)
   );
 
@@ -107,7 +109,12 @@ output reg		Clk
     dutpassed = 1;
     #10
 
-  // Test Case 1: 
+  // All test cases also test if any of the data is x's, as suggested by Will Derksen,
+  // because apparently x's will still pass an equivalence test in Verilog. I felt that
+  // this additional test is necessary because depending on the way something is broken,
+  // there might be something set to x and that will still be considered True (unbroken).
+
+  // Test Case 1:
   //   Write '42' to register 2, verify with Read Ports 1 and 2
   //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
@@ -118,12 +125,12 @@ output reg		Clk
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
   // Verify expectations and report test result
-  if((ReadData1 != 42) || (ReadData2 != 42)) begin
+  if((ReadData1 != 42) || (ReadData2 != 42) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
     dutpassed = 0;	// Set to 'false' on failure
     $display("Test Case 1 Failed");
   end
 
-  // Test Case 2: 
+  // Test Case 2:
   //   Write '15' to register 2, verify with Read Ports 1 and 2
   //   (Fails with example register file, but should pass with yours)
   WriteRegister = 5'd2;
@@ -133,16 +140,92 @@ output reg		Clk
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;
 
-  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+  if((ReadData1 != 15) || (ReadData2 != 15) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
     dutpassed = 0;
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3a:
+  // Write '40' to register 2, RegWrite is '1', verify with Read Ports 1 and 2
+  WriteRegister = 5'd2;
+  WriteData = 32'd40;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 40) || (ReadData2 != 40) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+    dutpassed = 0;
+    $display("Test Case 3a Failed");
+  end
+
+  // Write Enable is broken / ignored – Register is always written to.
+  // Write '10' to register 2, RegWrite is '0', verify with Read Ports 1 and 2
+  WriteRegister = 5'd2;
+  WriteData = 32'd10;
+  RegWrite = 0;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 10) || (ReadData2 == 10) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+    dutpassed = 0;
+    $display("Test Case 3b Failed");
+  end
+
+  // Test Case 4:
+  // Decoder is broken – All registers are written to
+  // Write '11' to register 2, don't write '11' to register 4, verify with Read Ports 1 and 2
+  // I don't check whether Port 2 is all x's because in this case I only care if it is equal to 11,
+  // and then it fails - it doesn't matter if nothing it written to it/if it is x's.
+  WriteRegister = 5'd2;
+  WriteData = 32'd11;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd4;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 11) || (ReadData2 == 11) || (ReadData1 === 32'bx)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+  // Test Case 5:
+  // Register Zero is actually a register instead of the constant value zero.
+  // Write '12' to register 0, verify with Read Ports 1 and 2
+  // I don't care about Port 2 being x's in this case - only Port 1 which is
+  // writing to Register Zero
+  WriteRegister = 5'd0;
+  WriteData = 32'd12;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd4;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData1 === 32'bx)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+  // Test Case 6:
+  // Port 2 is broken and always reads register 14 (for example)
+  // Write '10' to register 2, verify with Read Ports 1
+  WriteRegister = 5'd14;
+  WriteData = 32'd13;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd14;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 13) || (ReadData1 === 32'bx) || (ReadData2 === 32'bx)) begin
+    dutpassed = 0;
+    $display("Test Case 6 Failed");
+  end
 
   // All done!  Wait a moment and signal test completion.
   #5
   endtest = 1;
 
 end
 
-endmodule
+endmodule

regfile.v

@@ -6,6 +6,10 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "registers.v"
+`include "muxes.v"
+`include "decoders.v"
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -18,10 +22,22 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+  wire[31:0] interdecoder;
+  wire[31:0] intermux[31:0];
+
+  decoder1to32 decode(interdecoder, RegWrite, WriteRegister);
+
+  register32zero register0 (intermux[0], WriteData, RegWrite, Clk);
+
+  genvar i;
+  generate
+  for (i = 1; i < 32; i = i + 1)
+    begin: ripple
+      register32 register1(intermux[i], WriteData, interdecoder[i], Clk);
+    end
+  endgenerate
+
+  mux32to1by32 mux1(ReadData1, ReadRegister1, intermux[0], intermux[1], intermux[2], intermux[3], intermux[4], intermux[5], intermux[6], intermux[7], intermux[8], intermux[9], intermux[10], intermux[11], intermux[12], intermux[13], intermux[14], intermux[15], intermux[16], intermux[17], intermux[18], intermux[19], intermux[20], intermux[21], intermux[22], intermux[23], intermux[24], intermux[25], intermux[26], intermux[27], intermux[28], intermux[29], intermux[30], intermux[31]);
+  mux32to1by32 mux2(ReadData2, ReadRegister2, intermux[0], intermux[1], intermux[2], intermux[3], intermux[4], intermux[5], intermux[6], intermux[7], intermux[8], intermux[9], intermux[10], intermux[11], intermux[12], intermux[13], intermux[14], intermux[15], intermux[16], intermux[17], intermux[18], intermux[19], intermux[20], intermux[21], intermux[22], intermux[23], intermux[24], intermux[25], intermux[26], intermux[27], intermux[28], intermux[29], intermux[30], intermux[31]);
 
-endmodule
+endmodule

registers.v

@@ -0,0 +1,43 @@
+module register
+(
+output reg	q,
+input		d,
+input		wrenable,
+input		clk
+);
+  always @(posedge clk) begin
+      if(wrenable) begin
+          q = d;
+      end
+  end
+endmodule
+
+module register32
+(
+  output reg[31:0]	q,
+  input[31:0]		d,
+  input		wrenable,
+  input		clk
+);
+
+always @(posedge clk) begin
+    if(wrenable) begin
+      q = d;
+    end
+end
+
+endmodule
+
+module register32zero
+(
+  output reg[31:0]	q,
+  input[31:0]		d,
+  input		wrenable,
+  input		clk
+);
+
+always @(posedge clk) begin
+    q = 32'b0;
+end
+
+endmodule