Submitting HW4

decoders.v

@@ -9,6 +9,8 @@ input[4:0]	address
 );
 
     assign out = enable<<address; 
+    //Deliverable 6: the operator << shifts enable by the amount address to the left. If enable is 0, the result
+    // will still be zero no matter the shift. Other wise, the place specified by the address will become 1 in out.
 
 endmodule
 

mux.v

@@ -0,0 +1,43 @@
+// module mux32to1by1
+// (
+// output      out,
+// input[4:0]  address,
+// input[31:0] inputs
+// );
+//   assign out = inputs[address];
+// endmodule
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   inputs[31:0]
+// input[31:0]   input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10,
+// input11, input12, input13, input14, input15, input16, input17, input18, input19, input20,
+// input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  // assign mux[0] = input0;		// Connect the sources of the array
+  // assign mux[1] = input1; assign mux[2] = input2; assign mux[3] = input3;
+  // assign mux[4] = input4; assign mux[5] = input5; assign mux[6] = input6;
+  // assign mux[7] = input7; assign mux[8] = input8; assign mux[9] = input9;
+  // assign mux[10] = input10; assign mux[11] = input11; assign mux[12] = input11;
+  // assign mux[13] = input13; assign mux[14] = input14; assign mux[15] = input14;
+  // assign mux[16] = input16; assign mux[17] = input17; assign mux[18] = input17;
+  // assign mux[19] = input19; assign mux[20] = input20; assign mux[21] = input20;
+  // assign mux[22] = input22; assign mux[23] = input23; assign mux[24] = input23;
+  // assign mux[25] = input25; assign mux[26] = input26; assign mux[27] = input26;
+  // assign mux[28] = input28; assign mux[29] = input29; assign mux[30] = input29;
+  // assign mux[31] = input31; 
+  genvar j;
+  generate
+  	for (j = 0; j < 32; j = j + 1)
+  	begin: assinputs
+  		assign mux[j] = inputs[j];
+  	end
+  endgenerate
+
+  assign out = mux[address];	// Connect the output of the array
+
+endmodule

regfile.t.v

@@ -3,6 +3,8 @@
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -109,7 +111,6 @@ output reg		Clk
 
   // Test Case 1: 
   //   Write '42' to register 2, verify with Read Ports 1 and 2
-  //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
   WriteData = 32'd42;
   RegWrite = 1;
@@ -118,26 +119,52 @@ output reg		Clk
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
   // Verify expectations and report test result
-  if((ReadData1 != 42) || (ReadData2 != 42)) begin
+  if((ReadData1 != WriteData) || (ReadData2 != WriteData)) begin
     dutpassed = 0;	// Set to 'false' on failure
-    $display("Test Case 1 Failed");
+    $display("Test Case 1:check correct value is written and read Failed");
   end
 
   // Test Case 2: 
-  //   Write '15' to register 2, verify with Read Ports 1 and 2
-  //   (Fails with example register file, but should pass with yours)
-  WriteRegister = 5'd2;
+  //   Write '15' to register 10 without RegWrite = high, verify with Read Ports
+  WriteRegister = 5'd10;
+  WriteData = 32'd15;
+  RegWrite = 0;
+  ReadRegister1 = 5'd10;
+  ReadRegister2 = 5'd10;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 2:check write enable Failed");
+  end
+
+  // Test Case 3: 
+  //   Write '15' to register 15, verifying that no other changed
+  WriteRegister = 5'd15;
   WriteData = 32'd15;
   RegWrite = 1;
-  ReadRegister1 = 5'd2;
-  ReadRegister2 = 5'd2;
+  ReadRegister1 = 5'd15;
+  ReadRegister2 = 5'd20;
   #5 Clk=1; #5 Clk=0;
 
-  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+  if((ReadData1 != 15) || (ReadData2 != 0)) begin
     dutpassed = 0;
-    $display("Test Case 2 Failed");
+    $display("Test Case 3:check decoder Failed");
   end
 
+  // Test Case 4: 
+  //   Write '15' to register 0
+  WriteRegister = 5'd0;
+  WriteData = 32'd15;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 4:check register zero Failed");
+  end
 
   // All done!  Wait a moment and signal test completion.
   #5

regfile.v

@@ -6,6 +6,10 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "register.v"
+`include "decoders.v"
+`include "mux.v"
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -17,11 +21,20 @@ input[4:0]	WriteRegister,	// Address of register to write
 input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
+  wire[31:0] regouts[31:0];
+  wire[31:0] regselect;
+
+  register32zero reg0(regouts[0], WriteData, regselect[0], Clk);
+  genvar i;
+  generate
+  	for (i = 1; i < 32; i = i + 1)
+  	begin: createregisters
+  		register32 areg(regouts[i], WriteData, regselect[i], Clk);
+  	end
+  endgenerate
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+  decoder1to32 decoder(regselect, RegWrite, WriteRegister);
+  mux32to1by32 mux1(ReadData1, ReadRegister1, regouts);
+  mux32to1by32 mux2(ReadData2, ReadRegister2, regouts);
 
 endmodule

register.v

@@ -1,17 +1,32 @@
 // Single-bit D Flip-Flop with enable
 //   Positive edge triggered
-module register
+module register32
 (
-output reg	q,
-input		d,
+output reg[31:0]	q,
+input[31:0]		d,
 input		wrenable,
 input		clk
 );
 
     always @(posedge clk) begin
         if(wrenable) begin
-            q = d;
+            assign q = d;
         end
     end
 
+endmodule
+
+
+module register32zero
+(
+output reg[31:0]	q,
+input[31:0]		d,
+input		wrenable,
+input		clk
+);
+
+    always @(posedge clk) begin
+    	q = 0;
+    end
+
 endmodule