adding my code for HW4

mux32to1by1.v

@@ -0,0 +1,10 @@
+// 32:1 multiplexer
+
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+  assign out = inputs[address];
+endmodule

mux32to1by32.v

@@ -0,0 +1,49 @@
+// 32:32 mux
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]  input0, input1, input2, input3, input4, input5, input6, input7, 
+	input8, input9, input10, input11, input12, input13, input14, input15,
+	input16, input17, input18, input19, input20, input21, input22, input23,
+	input24, input25, input26, input27, input28, input29, input30, input31  
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = input0;		// Connect the sources of the array
+  // Repeat 31 times...
+  assign mux[1] = input1;
+  assign mux[2] = input2;
+  assign mux[3] = input3;
+  assign mux[4] = input4;
+  assign mux[5] = input5;
+  assign mux[6] = input6;
+  assign mux[7] = input7;
+  assign mux[8] = input8;
+  assign mux[9] = input9;
+  assign mux[10] = input10;
+  assign mux[11] = input11;
+  assign mux[12] = input12;
+  assign mux[13] = input13;
+  assign mux[14] = input14;
+  assign mux[15] = input15;
+  assign mux[16] = input16;
+  assign mux[17] = input17;
+  assign mux[18] = input18;
+  assign mux[19] = input19;
+  assign mux[20] = input20;
+  assign mux[21] = input21;
+  assign mux[22] = input22;
+  assign mux[23] = input23;
+  assign mux[24] = input24;
+  assign mux[25] = input25;
+  assign mux[26] = input26;
+  assign mux[27] = input27;
+  assign mux[28] = input28;
+  assign mux[29] = input29;
+  assign mux[30] = input30;
+  assign mux[31] = input31;
+
+  assign out = mux[address];	// Connect the output of the array
+endmodule

muxAssignGenerator.py

@@ -0,0 +1,9 @@
+# typing is no fun, for loops are better
+
+for i in range(32):
+  print "  assign mux[{}] = input{};".format(i, i)
+
+print "\n"
+for i in range(32):
+  print "input{},".format(i),
+print ""

regCallGenerator.py

@@ -0,0 +1,10 @@
+# typing is no fun, for loops are better
+
+for i in range(32):
+  print "  register32 reg{} (allregs[{}], WriteData, write[{}], Clk);".format(i, i, i)
+
+print "\n"
+
+for i in range(32):
+  print "allregs[{}],".format(i),
+print ""

regfile.t.v

@@ -2,6 +2,7 @@
 // Test harness validates hw4testbench by connecting it to various functional 
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
+`include "regfile.v"
 
 module hw4testbenchharness();
 
@@ -108,7 +109,7 @@ output reg		Clk
     #10
 
   // Test Case 1: 
-  //   Write '42' to register 2, verify with Read Ports 1 and 2
+  //   Write '42' to register 2, verify with Read Port 1
   //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
   WriteData = 32'd42;
@@ -118,9 +119,9 @@ output reg		Clk
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
   // Verify expectations and report test result
-  if((ReadData1 != 42) || (ReadData2 != 42)) begin
+  if(!(ReadData1 === 42)) begin
     dutpassed = 0;	// Set to 'false' on failure
-    $display("Test Case 1 Failed");
+    $display("Test Case 1 Failed: general write/read1 broken");
   end
 
   // Test Case 2: 
@@ -133,16 +134,84 @@ output reg		Clk
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;
 
-  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+  if(!(ReadData1 === 15) || !(ReadData2 === 15)) begin
     dutpassed = 0;
-    $display("Test Case 2 Failed");
+    $display("Test Case 2 Failed: general read/write broken");
+    $display("               note: general read2 broken if test 1 passed");
   end
 
+  // Test Case 3: 
+  //   First Write '5' to register 5 with write enabled, 
+  //   then write '21' ro register 5 with write disabled,
+  //   verify with Read Ports 1 and 2
+  //   (Fails if write enable is broken)
+    // write 1
+  WriteRegister = 5'd5;
+  WriteData = 32'd5;
+  RegWrite = 1;
+  #5 Clk=1; #5 Clk=0;
+    // write 2
+  WriteRegister = 5'd5;
+  WriteData = 32'd21;
+  RegWrite = 0;
+  ReadRegister1 = 5'd5;
+  ReadRegister2 = 5'd5;
+  #5 Clk=1; #5 Clk=0;
 
+  if(!(ReadData1 === 5) || !(ReadData2 === 5)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed: testing write enable");
   // All done!  Wait a moment and signal test completion.
+  end
+
+  // Test Case 4:
+  // Test decoder (see if another register was written to)
+  // Read from register 2 and make sure it still reads 15
+    // note: this assumes it comes after tests 2 and 3
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  RegWrite = 0;
+  #5 Clk=1; #5 Clk=0;
+
+  if(!(ReadData1 === 15) || !(ReadData2 === 15)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed: testing decoder");
+  end
+
+  // Test Case 5: 
+  //   verify zero register works
+  //   Write '15' to register 0, verify output is zerowith Read Ports 1 and 2
+  WriteRegister = 5'd0;
+  WriteData = 32'd15;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+
+  if(!(ReadData1 === 0) || !(ReadData2 === 0)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed: zero register read non-zero value");
+  end
+
+  // Test Case 6: 
+  //   verify that read port 1 and 2 work independently
+  //   Write '15' to register 11, verify output with port 2
+  //   read register 0 with port 0 and verify that it's zero
+  WriteRegister = 5'd11;
+  WriteData = 32'd15;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd11;
+  #5 Clk=1; #5 Clk=0;
+
+  if(!(ReadData1 === 0) || !(ReadData2 === 15)) begin
+    dutpassed = 0;
+    $display("Test Case 6 failed: testing if read registers are independent");
+  end
+
   #5
   endtest = 1;
 
 end
 
-endmodule
+endmodule

regfile.v

@@ -5,6 +5,10 @@
 //   2 asynchronous read ports
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
+`include "mux32to1by32.v"
+`include "decoders.v"
+`include "register32.v"
+`include "register32zero.v"
 
 module regfile
 (
@@ -18,10 +22,44 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+  wire [31:0] allregs [0:31];// = {31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0, 31'b0};
 
-endmodule
+  mux32to1by32 rreg1 (ReadData1, ReadRegister1, allregs[0], allregs[1], allregs[2], allregs[3], allregs[4], allregs[5], allregs[6], allregs[7], allregs[8], allregs[9], allregs[10], allregs[11], allregs[12], allregs[13], allregs[14], allregs[15], allregs[16], allregs[17], allregs[18], allregs[19], allregs[20], allregs[21], allregs[22], allregs[23], allregs[24], allregs[25], allregs[26], allregs[27], allregs[28], allregs[29], allregs[30], allregs[31]);
+
+  mux32to1by32 rreg2 (ReadData2, ReadRegister2, allregs[0], allregs[1], allregs[2], allregs[3], allregs[4], allregs[5], allregs[6], allregs[7], allregs[8], allregs[9], allregs[10], allregs[11], allregs[12], allregs[13], allregs[14], allregs[15], allregs[16], allregs[17], allregs[18], allregs[19], allregs[20], allregs[21], allregs[22], allregs[23], allregs[24], allregs[25], allregs[26], allregs[27], allregs[28], allregs[29], allregs[30], allregs[31]);
+
+  wire[31:0] write;
+  decoder1to32 wreg (write, RegWrite, WriteRegister);
+  register32zero zeroreg (allregs[0], WriteData, write[0], Clk);
+  register32 reg1 (allregs[1], WriteData, write[1], Clk);
+  register32 reg2 (allregs[2], WriteData, write[2], Clk);
+  register32 reg3 (allregs[3], WriteData, write[3], Clk);
+  register32 reg4 (allregs[4], WriteData, write[4], Clk);
+  register32 reg5 (allregs[5], WriteData, write[5], Clk);
+  register32 reg6 (allregs[6], WriteData, write[6], Clk);
+  register32 reg7 (allregs[7], WriteData, write[7], Clk);
+  register32 reg8 (allregs[8], WriteData, write[8], Clk);
+  register32 reg9 (allregs[9], WriteData, write[9], Clk);
+  register32 reg10 (allregs[10], WriteData, write[10], Clk);
+  register32 reg11 (allregs[11], WriteData, write[11], Clk);
+  register32 reg12 (allregs[12], WriteData, write[12], Clk);
+  register32 reg13 (allregs[13], WriteData, write[13], Clk);
+  register32 reg14 (allregs[14], WriteData, write[14], Clk);
+  register32 reg15 (allregs[15], WriteData, write[15], Clk);
+  register32 reg16 (allregs[16], WriteData, write[16], Clk);
+  register32 reg17 (allregs[17], WriteData, write[17], Clk);
+  register32 reg18 (allregs[18], WriteData, write[18], Clk);
+  register32 reg19 (allregs[19], WriteData, write[19], Clk);
+  register32 reg20 (allregs[20], WriteData, write[20], Clk);
+  register32 reg21 (allregs[21], WriteData, write[21], Clk);
+  register32 reg22 (allregs[22], WriteData, write[22], Clk);
+  register32 reg23 (allregs[23], WriteData, write[23], Clk);
+  register32 reg24 (allregs[24], WriteData, write[24], Clk);
+  register32 reg25 (allregs[25], WriteData, write[25], Clk);
+  register32 reg26 (allregs[26], WriteData, write[26], Clk);
+  register32 reg27 (allregs[27], WriteData, write[27], Clk);
+  register32 reg28 (allregs[28], WriteData, write[28], Clk);
+  register32 reg29 (allregs[29], WriteData, write[29], Clk);
+  register32 reg30 (allregs[30], WriteData, write[30], Clk);
+  register32 reg31 (allregs[31], WriteData, write[31], Clk);
+endmodule

register32.v

@@ -0,0 +1,15 @@
+// 32 bit register definition
+
+module register32
+(
+output reg[31:0]  q,
+input[31:0]       d,
+input       wrenable,
+input       clk
+);
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q = d;
+        end
+    end
+endmodule

register32zero.v

@@ -0,0 +1,15 @@
+// 32 bit register definition
+
+module register32zero
+(
+output reg[31:0]  q,
+input[31:0]       d,
+input       wrenable,
+input       clk
+);
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q = 32'b0;
+        end
+    end
+endmodule

writeup.md

@@ -0,0 +1,10 @@
+## Homework 4 written deliverables
+Rocco DiVerdi
+
+### Deliverable 1:
+
+TODO: attach image
+
+### Deliverable 6:
+
+The decoder code is a binary shift which takes the enable bit (in the `2**0` place) and shifts it left by the number of spaces indicated by the address. Since there is only one enable bit, all other values in the output bit array are zero, and the bit which is now at the indicated address now matches the enable bit (1 if write is enabled, 0 otherwise). The result is the correct output for a decoder.