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HW4 Submission #22

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c8bc447
HW4
wiltang Oct 20, 2017
cd5d4d1
HW4
wiltang Oct 20, 2017
d5f105f
HW4 adding mux.v
wiltang Oct 20, 2017
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58 changes: 58 additions & 0 deletions mux.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@

//
module mux32to1by1
(
output out,
input[4:0] address,
input[31:0] inputs
);
wire[31:0] inputsofmux;
wire outputofmux;
assign outputofmux=inputsofmux[address];
endmodule


module mux32to1by32
(
output[31:0] out,
input[4:0] address,
input[31:0] input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
);

wire[31:0] mux[31:0]; // Create a 2D array of wires

assign mux[0] = input0; // Connect the sources of the array
assign mux[1] = input1; // Connect the sources of the array
assign mux[2] = input2; // Connect the sources of the array
assign mux[3] = input3; // Connect the sources of the array
assign mux[4] = input4; // Connect the sources of the array
assign mux[5] = input5; // Connect the sources of the array
assign mux[6] = input6; // Connect the sources of the array
assign mux[7] = input7; // Connect the sources of the array
assign mux[8] = input8; // Connect the sources of the array
assign mux[9] = input9; // Connect the sources of the array
assign mux[10] = input10; // Connect the sources of the array
assign mux[11] = input11; // Connect the sources of the array
assign mux[12] = input12; // Connect the sources of the array
assign mux[13] = input13; // Connect the sources of the array
assign mux[14] = input14; // Connect the sources of the array
assign mux[15] = input15; // Connect the sources of the array
assign mux[16] = input16; // Connect the sources of the array
assign mux[17] = input17; // Connect the sources of the array
assign mux[18] = input18; // Connect the sources of the array
assign mux[19] = input19; // Connect the sources of the array
assign mux[20] = input20; // Connect the sources of the array
assign mux[21] = input21; // Connect the sources of the array
assign mux[22] = input22; // Connect the sources of the array
assign mux[23] = input23; // Connect the sources of the array
assign mux[24] = input24; // Connect the sources of the array
assign mux[25] = input25; // Connect the sources of the array
assign mux[26] = input26; // Connect the sources of the array
assign mux[27] = input27; // Connect the sources of the array
assign mux[28] = input28; // Connect the sources of the array
assign mux[29] = input29; // Connect the sources of the array
assign mux[30] = input30; // Connect the sources of the array
assign mux[31] = input31; // Connect the sources of the array

assign out = mux[address]; // Connect the output of the array
endmodule
275 changes: 267 additions & 8 deletions regfile.t.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// or broken register files, and verifying that it correctly identifies each
//------------------------------------------------------------------------------

`include "regfile.v"
module hw4testbenchharness();

wire[31:0] ReadData1; // Data from first register read
Expand Down Expand Up @@ -35,6 +36,7 @@ module hw4testbenchharness();
(
.begintest(begintest),
.endtest(endtest),

.dutpassed(dutpassed),
.ReadData1(ReadData1),
.ReadData2(ReadData2),
Expand Down Expand Up @@ -107,14 +109,14 @@ output reg Clk
dutpassed = 1;
#10


// Test Case 1:
// Write '42' to register 2, verify with Read Ports 1 and 2
// (Passes because example register file is hardwired to return 42)
WriteRegister = 5'd2;
WriteRegister = 5'd1;
WriteData = 32'd42;
RegWrite = 1;
ReadRegister1 = 5'd2;
ReadRegister2 = 5'd2;
ReadRegister1 = 5'd1;
ReadRegister2 = 5'd1;
#5 Clk=1; #5 Clk=0; // Generate single clock pulse

// Verify expectations and report test result
Expand All @@ -125,19 +127,276 @@ output reg Clk

// Test Case 2:
// Write '15' to register 2, verify with Read Ports 1 and 2
// (Fails with example register file, but should pass with yours)
WriteRegister = 5'd2;
WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd2;
ReadRegister2 = 5'd2;
ReadRegister1 = 5'd1;
ReadRegister2 = 5'd1;
#5 Clk=1; #5 Clk=0;

if((ReadData1 != 15) || (ReadData2 != 15)) begin
dutpassed = 0;
$display("Test Case 2 Failed");
end

//Test Case 3: Check Register Zero
//Write to Register Zero with a value, and check it is zero and if it is a register
WriteRegister = 5'd0;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd0;
ReadRegister2 = 5'd0;
#5 Clk=1; #5 Clk=0;

if((ReadData1 != 32'b0)) begin
dutpassed = 0;
$display("Test Case 3 Failed");
end


//Test Case 4: Check Enable
// Write '15' to register 2, verify with Read Ports 1 and 2 on 2 different registers that there have been no changes
WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 0;
ReadRegister1 = 5'd2;
ReadRegister2 = 5'd20;
#5 Clk=1; #5 Clk=0;

if((ReadData1 != 0) || (ReadData2 != 0)) begin
dutpassed = 0;
$display("Test Case 4 Failed");
end


//Test Case 5: Check Decoder
// Write '15' to register 2, verify that register 2 is correct, and check that the other registers haven't been written to (exaustively)
WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd1;
ReadRegister2 = 5'd1;
#5 Clk=1; #5 Clk=0;

if((ReadData1 != WriteData) || (ReadData2 != WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd2;
ReadRegister2 = 5'd3;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd4;
ReadRegister2 = 5'd5;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd6;
ReadRegister2 = 5'd7;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd8;
ReadRegister2 = 5'd9;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd10;
ReadRegister2 = 5'd11;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd12;
ReadRegister2 = 5'd13;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd10;
ReadRegister2 = 5'd11;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd12;
ReadRegister2 = 5'd13;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd14;
ReadRegister2 = 5'd15;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd16;
ReadRegister2 = 5'd17;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd18;
ReadRegister2 = 5'd19;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd20;
ReadRegister2 = 5'd21;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd22;
ReadRegister2 = 5'd23;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd24;
ReadRegister2 = 5'd25;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd26;
ReadRegister2 = 5'd27;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd27;
ReadRegister2 = 5'd28;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd29;
ReadRegister2 = 5'd30;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end

WriteRegister = 5'd1;
WriteData = 32'd15;
RegWrite = 1;
ReadRegister1 = 5'd31;
ReadRegister2 = 5'd31;
#5 Clk=1; #5 Clk=0;

if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
dutpassed = 0;
$display("Test Case 5 Failed");
end


// All done! Wait a moment and signal test completion.
#5
Expand Down
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