DigitalElecDesign

数电课设 repository

项目结构

分别设置Verilog HDL源文件和约束文件

.
|-- README.md
`-- eclock
    |-- constraints
    |   `-- eclock_bimu.xdc
    `-- src
        |-- main.v
        `-- yima.v

Name		Name	Last commit message	Last commit date
Latest commit History 49 Commits
Tetris		Tetris
elock		elock
elock_modular		elock_modular
pill		pill
pill_modular		pill_modular
.gitignore		.gitignore
README.md		README.md