VHDL Verilog code for the Guessing Random Additive Noise Decoding (GRAND)
In this project we implemented the Guessing Random Additive Noise Decoding (GRAND) in VHDL Verilog in two versions: soft and hard. GRAND algorithm is a methodology used to recover signals that are corrupted. For more info about GRAND kindly visit: GRAND MIT. Soft Grand is a more sophisticated version that takes into consideration the probobility associated with Noise on each bit.
EDA playground for Hard Grand EDA playGround for Soft Grand
- Roni Bou Saab
- Bahaa Ammoury
- Jean El Jamous
This project was done in the EECE 320 - Digital Systems Design course under the supervion of Dr. Hadi Sarieddeen.