Add secp256k1 AVX2/AVX-512 field multiplication proof of concept

[hadv]

secp256k1 AVX2/AVX-512 Proof of Concept

This PR explored using AVX2 SIMD instructions to accelerate secp256k1 field multiplication for EOA address mining.

Benchmark Results

Field Multiplication (GitHub Actions - AMD EPYC 7763)

Implementation	Throughput	Speedup
Scalar (4x sequential)	46.22 M mul/sec	1x
AVX2 (4-way parallel)	169.11 M mul/sec	3.66x

Point Addition (Local - Apple Silicon via Rosetta)

Implementation	Throughput	Speedup
Scalar (4x sequential)	16.83 M add/sec	1x
AVX2 (4-way parallel)	11.60 M add/sec	0.69x (slower)

Key Findings

1. AVX2 field multiplication shows excellent speedup (3.66x on AMD EPYC)

2. AVX2 point addition is slower than scalar in this PoC due to:

   • Simplified field multiplication that ignores carries (for PoC simplicity)
   • Memory layout overhead from limb-slicing
   • Need for proper 128-bit intermediate handling

3. AVX-512 IFMA not available on GitHub Actions runners (AMD EPYC doesn't have it)

Technical Approach

• 5×52-bit limb representation for field elements
• Limb-slicing technique: Pack corresponding limbs from 4 field elements into 256-bit YMM registers
• 26-bit split for multiplication: Split 52-bit limbs for vpmuludq compatibility
• Jacobian coordinates for efficient point operations

Files Created

poc/secp256k1-avx2/
├── field.h              # 5×52 representation
├── field_mul.h          # Scalar reference + add/sub
├── field_mul_avx2.h     # AVX2 4-way multiplication
├── field_ops_avx2.h     # AVX2 4-way add/sub/neg
├── field_mul_avx512.h   # AVX-512 IFMA (for future)
├── group.h              # Point structures + generator G
├── group_avx2.h         # AVX2 4-way point operations
├── bench.c              # Field multiplication benchmark
├── bench_point.c        # Point addition benchmark
├── Makefile
└── README.md

Conclusion

While AVX2 shows promising speedup for individual field operations, achieving end-to-end speedup for point operations requires:

1. Proper carry propagation in field multiplication
2. Optimized memory layout to reduce gather/scatter overhead
3. Potentially AVX-512 IFMA for native 52×52→104 bit multiply-add

For EOA mining, CUDA/GPU implementation is likely more practical since GPUs can run thousands of parallel point operations vs 4-8 with SIMD.

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This PR is closed as an exploratory PoC. The code remains in the branch for reference.