ot_sram_ctrl: Connect the lc_ctrl HW_DEBUG_EN signal for ifetch / execution enablement

[AlexJones0]

The current SRAM controller ifetch / execution enablement logic only considers that the configured ifetch enable property should be true, in addition to the OTP HW_CFG1.EN_SRAM_IFETCH field and the sram_ctrl CSR EXEC.EN field. This is likely based on the EXEC.EN documentation which states that:

Note that this register only takes effect if the EN_SRAM_IFETCH switch in the OTP HW_CFG1 partition is set to kMultiBitBool8True. Otherwise execution from SRAM cannot be enabled via this register.

While this isn't incorrect, it doesn't paint the full picture. From the RTL:

    assign en_ifetch = (mubi8_test_true_strict(otp_en_sram_ifetch)) ? reg_ifetch_en :
                                                                      lc_ifetch_en;

In the case that the OTP iftech is disabled, the CSR value is entirely ignored and instead the value of the pervasive lifecycle controller hw_debug_en broadcast signal is used to determine SRAM ifetch enablement. This PR implements this functionality, retaining the behaviour that the ifetch config property acts a disable regardless of the HW_DEBUG_EN value.

[jwnrt]

LGTM

[rivos-eblot]

LGTM. Maybe add a link to a ticket for the doc to be updated?

[AlexJones0]

Maybe add a link to a ticket for the doc to be updated?

Done, I just opened a PR instead: lowRISC/opentitan#28900

[AlexJones0]

Merging as CI failures are unrelated.