Allow dumping of tofino registers as component details

[labbott]

These have been vetted to be safe to dump

[labbott]

This is where we need to fill out the rest of the registers

[labbott]

laura@lurch ~ $ FAUX_MGS=~/faux-mgs pilot sp exec -e 'component-details tofino' BRM44220006
Jan 09 14:08:43.009 INFO creating SP handle on interface axf2, component: faux-mgs
Jan 09 14:08:43.011 INFO initial discovery complete, addr: [fe80::aa40:25ff:fe05:500%3]:11111, interface: axf2, socket: control-plane-agent, component: faux-mgs
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x10 reg_result: Ok(0x5cb034ad)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x180 reg_result: Ok(0x215f)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x1a0 reg_result: Ok(0xe300)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x1b4 reg_result: Ok(0x0)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x80000 reg_result: Ok(0xf3fc000)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x80004 reg_result: Ok(0x70000a8)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x8000c reg_result: Ok(0x7fa1b18)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x80038 reg_result: Ok(0xc000c)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x8003c reg_result: Ok(0xc000c)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x80040 reg_result: Ok(0x10261028)) })
Pcie(PcieRegisterRead { bar: 0x0 offset: 0x80044 reg_result: Ok(0x261028)) })
Pcie(PcieRegisterRead { bar: 0x20000000 offset: 0x0 reg_result: Ok(0xe20f03)) })

[rmustacc]

Thanks for putting this together @labbott.

[labbott]

given this is a separate API just returning the raw FPGA error seemed much cleaner/more useful

[hawkw]

spurious whitespace change?

[hawkw]

this should be unreachable, due to the higher level code for enumerating components, right? perhaps this should be more explicit here?

[labbott]

I was going off of the example in mgs_compute_sled.rs but I'll tweak the wording to say this should be unreachable: