Prepare qcom-next based on tag 'Linux 6.16-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #33
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sa8775p-ride firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-5-b2cf4a20feda@oss.qualcomm.com Co-developed-by: Shivendra Pratap <quic_spratap@quicinc.com> Signed-off-by: Shivendra Pratap <quic_spratap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com>
SoC vendors have different types of resets and are controlled through
various registers. For instance, Qualcomm chipsets can reboot to a
"download mode" that allows a RAM dump to be collected. Another example
is they also support writing a cookie that can be read by bootloader
during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these
vendor reset types to be implemented without requiring drivers for every
register/cookie.
Add support in PSCI to statically map reboot mode commands from
userspace to a vendor reset and cookie value using the device tree.
A separate initcall is needed to parse the devicetree, instead of using
psci_dt_init because mm isn't sufficiently set up to allocate memory.
Reboot mode framework is close but doesn't quite fit with the
design and requirements for PSCI SYSTEM_RESET2. Some of these issues can
be solved but doesn't seem reasonable in sum:
1. reboot mode registers against the reboot_notifier_list, which is too
early to call SYSTEM_RESET2. PSCI would need to remember the reset
type from the reboot-mode framework callback and use it
psci_sys_reset.
2. reboot mode assumes only one cookie/parameter is described in the
device tree. SYSTEM_RESET2 uses 2: one for the type and one for
cookie.
3. psci cpuidle driver already registers a driver against the
arm,psci-1.0 compatible. Refactoring would be needed to have both a
cpuidle and reboot-mode driver.
Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-2-b2cf4a20feda@oss.qualcomm.com
Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
…or QUP SEs Default pinctrl configurations for all QUP (Qualcomm Universal Peripheral) Serial Engines (SEs) are missing in the SoC device tree. These configurations are required by client teams when enabling any SEs as I2C, SPI, or Serial protocols. Add default pin configurations for Serial Engines (SEs) for all supported protocols, including I2C, SPI, and UART, to the sa8775p device tree. This change facilitates slave device driver clients to enable usecase with minimal modifications. Remove duplicate pin configurations from target-specific file as same pin configuration is included in the SoC device tree. Link: https://lore.kernel.org/r/20250509090443.4107378-1-quic_vdadhani@quicinc.com Acked-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
…board QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC. Unlike QCS9100, it doesn't have safety monitoring feature of Safety-Island(SAIL) subsystem, which affects thermal management. qcs9075-iq-9075-evk board is based on QCS9075 SOC. Link: https://lore.kernel.org/r/20250528122753.3623570-2-quic_wasimn@quicinc.com Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
…/qcs9075 SA8775P has a memory map which caters to the auto specific requirements. QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which inherit the memory map of SA8775P require a slightly different memory map as compared to SA8775P auto parts. This new memory map is applicable for all the IoT boards which inherit the initial SA8775P memory map. This is not applicable for non-IoT boards. Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been introduced as part of firmware updates for IoT. The size and base address have been updated for video PIL carveout compared to SA8775P since it is being brought up for the first time on IoT boards. The base addresses of the rest of the PIL carveouts have been updated to accommodate the change in size of video since PIL regions are relocatable and their functionality is not impacted due to this change. The size of camera pil has also been increased without breaking any feature. The size of trusted apps carveout has also been reduced since it is sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem carveout and its corresponding scm reference has been removed as these are not required for IoT parts. Incorporate these changes in the updated memory map. Link: https://lore.kernel.org/r/20250528122753.3623570-3-quic_wasimn@quicinc.com Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
QCS9075 is an IoT variant of SA8775P SOC, most notably without safety monitoring feature of Safety Island(SAIL) subsystem. Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC, PMICs, Memory-map updates. Use this SOM for qcs9075-iq-9075-evk board. Link: https://lore.kernel.org/r/20250528122753.3623570-4-quic_wasimn@quicinc.com Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Add initial device tree support for IQ-9075-EVK board, based on Qualcomm's QCS9075 SOC. Implement basic features like uart/ufs to enable boot to shell. Link: https://lore.kernel.org/r/20250528122753.3623570-5-quic_wasimn@quicinc.com Co-developed-by: Rakesh Kota <quic_kotarake@quicinc.com> Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com> Co-developed-by: Sayali Lokhande <quic_sayalil@quicinc.com> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Add RTC node, the RTC is controlled by PMIC device via spmi bus. Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> Link: https://lore.kernel.org/r/20240902104302.3959670-1-quic_tingguoc@quicinc.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Correct the ngpios entry to account for the UFS_RESET pin being exported as a GPIO in addition to the real GPIOs, allowing the UFS driver to toggle it. Fixes: b698f36 ("pinctrl: qcom: add the tlmm driver for QCS615 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20241219-correct_gpio_ranges-v2-3-19af8588dbd0@quicinc.com/ Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
… for qcs615 Correct the gpio-ranges in the QCS615 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Link: https://lore.kernel.org/r/20250506-correct_gpio_ranges-v3-1-49a7d292befa@quicinc.com Fixes: 55c487e ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
… for qcs8300 Correct the gpio-ranges in the QCS8300 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Link: https://lore.kernel.org/r/20250506-correct_gpio_ranges-v3-2-49a7d292befa@quicinc.com Fixes: 5778535 ("dt-bindings: pinctrl: describe qcs8300-tlmm") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Correct the ngpios entry to account for the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory and is exported as GPIOs in addition to the real GPIOs, allowing the UFS driver to toggle it. Link: https://lore.kernel.org/r/20250506-correct_gpio_ranges-v3-4-49a7d292befa@quicinc.com Fixes: 0c4cd2c ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
The files generated by gen_header.py capture the source path to the input files and the date. While that can be informative, it varies based on where and when the kernel was built as the full path is captured. Since all of the files that this tool is run on is under the drivers directory, this modifies the application to strip all of the path before drivers. Additionally it prints <stripped> instead of the date. Signed-off-by: Ryan Eatmon <reatmon@ti.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com> Link: https://lore.kernel.org/dri-devel/20250524-binrep-v2-1-09040177218e@oss.qualcomm.com/ Signed-off-by: Viswanath Kraleti <viswanath.kraleti@oss.qualcomm.com>
Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-1-b2cf4a20feda@oss.qualcomm.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com>
qcm6490-idp firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-3-b2cf4a20feda@oss.qualcomm.com Co-developed-by: Shivendra Pratap <quic_spratap@quicinc.com> Signed-off-by: Shivendra Pratap <quic_spratap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com>
…ypes qcs6490-rb3gen2 firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-4-b2cf4a20feda@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com>
Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-2-quic_pkumpatl@quicinc.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
…ution Manage clock settings for ADSP solution and document the clock properties on sc7280 lpass pincontrol node which is required for ADSP based solution. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-3-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Add WSA LPASS macro Codec along with SoundWire controller. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-4-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
…lock settings for audioreach Modify and enable WSA, VA, RX and TX lpass macros and lpass_tlmm clock settings. For audioreach solution mclk, npl and fsgen clocks are enabled through the q6prm clock driver. For qcs6490 RX drives clk from TX CORE which is mandated from DSP side, Unlike dedicated core clocks. Core TX clk is used for both RX and WSA as per DSP recommendations. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-5-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
…lifier Add nodes for WSA8830 speakers amplifier on qcs6490-rb3gen2 board. Enable lpass_wsa and lpass_va macros along with pinctrl settings for audio. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-6-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Add the sound card node with tested playback over WSA8835 speakers and digital on-board mics. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-7-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
…9370 headset codec Add nodes for WSA8830 speakers and WCD9370 headset codec on qcm6490-idp board. Enable lpass macros along with audio support pin controls. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-8-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Add the sound card node with tested playback over WSA8835 speakers, digital on-board mics along with wcd9370 headset playabck and record. Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> Link: https://lore.kernel.org/linux-arm-msm/20250527111227.2318021-9-quic_pkumpatl@quicinc.com/ Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Firmware might hold the DPB buffers for reference in case of sequence change, so skip destroying buffers for which QUEUED flag is not removed. Cc: stable@vger.kernel.org Fixes: 73702f4 ("media: iris: allocate, initialize and queue internal buffers") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-1-59b4ff7d331c@quicinc.com/ Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Validate all internal buffers queued to firmware are released back to driver on close. This helps ensure buffer lifecycle correctness and aids in debugging any resporce leaks. Cc: stable@vger.kernel.org Fixes: 73702f4 ("media: iris: allocate, initialize and queue internal buffers") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-2-59b4ff7d331c@quicinc.com/ Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Update the width, height and buffer size of CAPTURE based on the resolution set to OUTPUT via VIDIOC_S_FMT. This is required to set the updated capture resolution to firmware when S_FMT is called only for OUTPUT. Cc: stable@vger.kernel.org Fixes: b530b95 ("media: iris: implement s_fmt, g_fmt and try_fmt ioctls") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-3-59b4ff7d331c@quicinc.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Vikash Garodia <quic_vgarodia@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
…econfig During reconfig, the firmware sends the resolution aligned to 8 bytes. If the driver sends the same resolution back to the firmware the resolution will be aligned to 16 bytes not 8. The alignment mismatch would then subsequently cause the firmware to send another redundant sequence change event. Fix this by not setting the resolution property during reconfig. Cc: stable@vger.kernel.org Fixes: 3a19d7b ("media: iris: implement set properties to firmware during streamon") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-4-59b4ff7d331c@quicinc.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Currently, port check enforces that session property response must arrive only on the BITSTREAM port. However, firmware can send some responses on other port as well. Remove the strict port validation to correctly handle session property responses from the firmware. Cc: stable@vger.kernel.org Fixes: 3a19d7b ("media: iris: implement set properties to firmware during streamon") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-5-59b4ff7d331c@quicinc.com/ Acked-by: Vikash Garodia <quic_vgarodia@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
…t state The current check only considers the core error state before allowing writes to the HFI queues. However, the core can also transition to the deinit state due to a system error triggered by the response thread. In such cases, writing to the HFI queues should not be allowed. Fix this by adding a check for the core deinit state, ensuring that writes are rejected when core is not in a valid state. Cc: stable@vger.kernel.org Fixes: fb583a2 ("media: iris: introduce host firmware interface with necessary hooks") Link: https://lore.kernel.org/linux-arm-msm/20250509-video-iris-hevc-vp9-v5-6-59b4ff7d331c@quicinc.com/ Acked-by: Vikash Garodia <quic_vgarodia@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Link: https://lore.kernel.org/all/20250423-tgu_patch-v5-4-3b52c105cc63@quicinc.com/ Signed-off-by: Songwei Chai <quic_songchai@quicinc.com>
Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Link: https://lore.kernel.org/all/20250423-tgu_patch-v5-5-3b52c105cc63@quicinc.com/ Signed-off-by: Songwei Chai <quic_songchai@quicinc.com>
Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Link: https://lore.kernel.org/all/20250423-tgu_patch-v5-6-3b52c105cc63@quicinc.com/ Signed-off-by: Songwei Chai <quic_songchai@quicinc.com>
Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes Link: https://lore.kernel.org/all/20250423-tgu_patch-v5-7-3b52c105cc63@quicinc.com/ Signed-off-by: Songwei Chai <quic_songchai@quicinc.com>
Add an ethernet controller node for QCS615 SoC to enable ethernet functionality. Link: https://lore.kernel.org/r/20250121-dts_qcs615-v3-3-fa4496950d8a@quicinc.com Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Enable the ethernet node, add the phy node and pinctrl for ethernet. This change is necessary to support ethernet functionality on this board. Link: https://lore.kernel.org/r/20250121-dts_qcs615-v3-4-fa4496950d8a@quicinc.com Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
…on qcs615-ride The timing of sampling at the RX side for qcs615-ride needs adjustment. It varies from board to board. Link: https://lore.kernel.org/r/20241225-support_10m100m-v1-3-4b52ef48b488@quicinc.com Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
Document the components used to boot the ADSP and CDSP on the Qualcomm QCS615 SoC. Use fallback to indicate the compatibility of the remoteproc on the QCS615 with that on the SM8150. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-1-06a7d8bed0b5@quicinc.com
Document qcom,qcs615-imem compatible. It has a child node for debugging purposes. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-2-06a7d8bed0b5@quicinc.com
The Shared Memory Point to Point (SMP2P) protocol facilitates communication of a single 32-bit value between two processors. Add these two nodes for remoteproc enablement on QCS615 SoC. Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-3-06a7d8bed0b5@quicinc.com
Add a simple-mfd representing IMEM on QCS615 and define the PIL relocation info region as its child. The PIL region in IMEM is used to communicate load addresses of remoteproc to post mortem debug tools, so that these tools can collect ramdumps. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-4-06a7d8bed0b5@quicinc.com
Add nodes for remoteprocs: ADSP and CDSP for QCS615 SoC to enable proper remoteproc functionality. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-5-06a7d8bed0b5@quicinc.com
Enable all remoteproc nodes on the qcs615-ride board and point to the appropriate firmware files to allow proper functioning of the remote processors. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-6-06a7d8bed0b5@quicinc.com
At least on SC8280XP, if the PCIe reset is asserted, the corresponding AUX_CLK will be stuck at 'off'. This has not been an issue so far, since the reset is both left de-asserted by the previous boot stages and the driver only toggles it briefly in .init. As part of the upcoming suspend procedure however, the reset will be held asserted. Assert the reset (which may end up being a NOP in some cases) and de-assert it back *before* turning on the clocks in preparation for introducing RC powerdown and reinitialization. Link: https://lore.kernel.org/linux-pci/20240210-topic-8280_pcie-v2-0-1cef4b606883@linaro.org/ Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krishna Chaitanya Chundru <krichai@qti.qualcomm.com>
Currently, we've only been minimizing the power draw while keeping the RC up at all times. This is suboptimal, as it draws a whole lot of power and prevents the SoC from power collapsing. Implement full shutdown and re-initialization to allow for powering off the controller. This is mainly intended for SC8280XP with a broken power rail setup, which requires a full RC shutdown/reinit in order to reach SoC-wide power collapse, but sleeping is generally better than not sleeping and less destructive suspend can be implemented later for platforms that support it. Link: https://lore.kernel.org/linux-pci/20240210-topic-8280_pcie-v2-0-1cef4b606883@linaro.org/ Co-developed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krishna Chaitanya Chundru <krichai@qti.qualcomm.com>
Add prune.config fragment to disable support for non-Qualcomm architectures. This helps reduce boot image size and improves kernel build KPIs by trimming unnecessary configuration options. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
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Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA
tech/bsp/pinctrl d7e196c
tech/bus/pci/all 1103f9c
tech/debug/hwtracing efd272e
tech/mm/drm aa742d7
tech/mm/video 8e7bd48
tech/pm/power 1eeed9b
tech/all/dt/qcs6490 e9c1cce
tech/all/dt/qcs9100 de711b0
tech/all/dt/qcs615 9121250
tech/all/config dd11b10