[Addon in validation] Add Ram-Pak support

[whitequark]

WIP: This PR will remain a draft until 1bitSquared finalizes a production design for Ram-Pak.

Ram-Pak schematic: https://github.com/esden/glasgow-addons/blob/master/hardware/ram-pak/ram-pak-sch.pdf

Current status of the controller gateware:

• PHY that uses DDR output registers to phase-shift clock
• sequencer that shifts command/address and controls flow of data
• manual testing of all kinds of register writes
• manual testing of small memory writes
• large scale testing by writing the entire bee movie script into the RAM 48 times and then reading it back
• glasgow run selftest addon-ram-pak
• gateware.hyperram.Arbiter
  • performs arbitrage of a sequencer between several controllers
  • switches between controllers when one sends o.last
  • also switches between controllers and sends i.last prematurely to ensure fairness
• gateware.hyperram.Reader
  • convert address input stream into data output stream
  • reading from consecutive addresses performs a burst
  • prefetches one address and sends o.last if there is a jump
  • reacts to i.last (premature or not) by restarting command/address
• gateware.hyperram.Writer
  • same thing but for address, data tuples
• gateware.hyperram.Queue
  • first-in first-out queue
  • ~same interface as amaranth.lib.fifo.SyncFIFOBuffered
  • very efficient for bursts, less efficient for one-off fetches

Details of the above aren't really clear. Fairness and correct handling of bursts seems difficult.