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@rodrigo455 rodrigo455 commented Nov 5, 2025

PR Description

  • This PR is not meant to be merged, as it targets an upstream mirror
  • I want to collect feedback and run CI pipelines if possible
  • This PR adds the ADF41513 driver implementation and documentation
  • ADF41513 is a dual modulus PLL frequency synth
  • Current implementation is based on existing PLL drivers
  • the driver implements a clock provider/supplier, but clock-scales is not taken care here, because that feature is not available in this branch

PR Type

  • Bug fix (a change that fixes an issue)
  • New feature (a change that adds new functionality)
  • Breaking change (a change that affects other repos or cause CIs to fail)

PR Checklist

  • I have conducted a self-review of my own code changes
  • I have compiled my changes, including the documentation
  • I have tested the changes on the relevant hardware
  • I have updated the documentation outside this repo accordingly
  • I have provided links for the relevant upstream lore

@gastmaier gastmaier marked this pull request as draft November 5, 2025 09:38
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch 4 times, most recently from ccd64ff to 76e3d30 Compare November 5, 2025 12:29
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@github-actions github-actions bot force-pushed the mirror/jic23/iio/testing branch from c9591d3 to 65e501e Compare November 7, 2025 00:00
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Just some comments about using legacy platform_data. Once you mark this ready for reviewing I'll give a more in depth review.

@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch from 76e3d30 to fe10392 Compare November 7, 2025 13:00
@rodrigo455 rodrigo455 marked this pull request as ready for review November 7, 2025 13:10
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch from fe10392 to f98be31 Compare November 7, 2025 14:54
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Ok, I'm done for now :). We'll need some iterations on this one and skipped more questionable/complicated things for now. We are also pushing the limits of what can go into a DT property so be ready to justify them when upstreaming.

@github-actions github-actions bot force-pushed the mirror/jic23/iio/testing branch 2 times, most recently from 950132e to b60429f Compare November 10, 2025 00:10
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch from f98be31 to 3150872 Compare November 10, 2025 12:20
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch from fc5e37e to 3cd51ea Compare December 4, 2025 17:29
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Ok, it looks like we're getting closer to an upstream v2. My main doubt right now is phase_resync computation


adf41513_suspend(st);
if (st->chip_enable)
gpiod_set_value_cansleep(st->chip_enable, 0);
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Just curious... Are disabling different blocks with the enable_gpio when compared to adf41513_suspend()? IOW, do we need both?

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likely not, it could be one or the other. it would not make difference to use both though

return dev_err_probe(dev, -ERANGE,
"power-up frequency %llu Hz out of range\n",
st->data.power_up_frequency_hz);
}
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I though you had the above as mandatory now?

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yeah, decided to make optional with 10 GHz as default. Still, this value should be set for specific hardware designs so that the initialization sequence starts from a valid configuration.

frequency accordingly.
The value written has no effect until out_altvoltageY_frequency
is updated. Consider to use out_altvoltageY_powerdown to power down the
PLL and its RFOut buffers during REFin changes.
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The above two lines makes me wonder if this is something we can automatically do in the driver (if it is a best practice to do so)?

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The value written has no effect until out_altvoltageY_frequency is updated

I can handle this part.

Consider to use out_altvoltageY_powerdown to power down the PLL and its RFOut buffers during REFin changes

this is not really necessary but avoid glitches in the output.

@github-actions github-actions bot force-pushed the mirror_ci/jic23/iio/testing branch from 21cdfb2 to a879dd2 Compare December 12, 2025 00:15
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch 2 times, most recently from 450379a to 5be3835 Compare December 12, 2025 11:52
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Ok, take my comments and I think we are good for v2.

dt-bindings for ADF41513, an ultralow noise PLL frequency synthesizer that
can be used to implement local oscillators (LOs) as high as 26.5 GHz.
Most properties refer to existing PLL driver properties (e.g. ADF4350).

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
The driver is based on existing PLL drivers in the IIO subsystem and
implements the following key features:

- Integer-N and fractional-N (fixed/variable modulus) synthesis modes
- High-resolution frequency calculations using microhertz (µHz) precision
  to handle sub-Hz resolution across multi-GHz frequency ranges
- IIO debugfs interface for direct register access
- FW property parsing from devicetree including charge pump settings,
  reference path configuration and muxout options
- Power management support with suspend/resume callbacks
- Lock detect GPIO monitoring

The driver uses 64-bit microhertz values throughout PLL calculations to
maintain precision when working with frequencies that exceed 32-bit Hz
representation while requiring fractional Hz resolution.

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
When LE sync is enabled, it is must be set after powering up and must be
disabled when powering down. It is recommended when using the PLL as
a frequency synthesizer, where reference signal will always be present
while the device is being configured.

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
Set Bleed current when PFD frequency changes (bleed enabled when in
fractional mode). Set lock detector window size, handling bias and
precision. Add phase resync support, setting clock dividers when
PFD frequency changes.

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
add documentation for ADF41513 driver which describes the device
driver files and shows how userspace may consume the ABI for various
tasks

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
Add ABI documentation for ADF41513 PLL sysfs interfaces

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
@rodrigo455 rodrigo455 force-pushed the staging/jic23_iio_adf41513 branch from 5be3835 to b2c782a Compare December 19, 2025 11:35
@github-actions github-actions bot force-pushed the mirror_ci/jic23/iio/testing branch from 2d1c47d to d06d4c7 Compare December 20, 2025 00:00
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6 participants