Support more useful properties

include/sta/Liberty.hh

@@ -467,6 +467,7 @@ public:
   // Find a timing arc set equivalent to key.
   TimingArcSet *findTimingArcSet(TimingArcSet *key) const;
   TimingArcSet *findTimingArcSet(unsigned arc_set_index) const;
+  bool hasTimingArcs() const;
   bool hasTimingArcs(LibertyPort *port) const;
 
   const InternalPowerSeq &internalPowers() const { return internal_powers_; }

liberty/Liberty.cc

@@ -1480,6 +1480,13 @@ LibertyCell::timingArcSetCount() const
   return timing_arc_sets_.size();
 }
 
+bool
+LibertyCell::hasTimingArcs() const
+{
+  return !timing_arc_set_from_map_.empty()
+    || !timing_arc_set_to_map_.empty();
+}
+
 bool
 LibertyCell::hasTimingArcs(LibertyPort *port) const
 {

search/Property.cc

@@ -40,6 +40,8 @@
 #include "Path.hh"
 #include "power/Power.hh"
 #include "Sta.hh"
+#include "Search.hh"
+#include "PathGroup.hh"
 
 namespace sta {
 
@@ -732,11 +734,18 @@ Properties::getProperty(const LibertyCell *cell,
     return PropertyValue(cell->filename());
   else if (property == "library")
     return PropertyValue(cell->libertyLibrary());
+  else if (property == "is_sequential")
+    return PropertyValue(cell->hasSequentials());
+  else if (property == "has_timing_model")
+    return PropertyValue(cell->hasTimingArcs());
   else if (property == "is_buffer")
     return PropertyValue(cell->isBuffer());
-  else if (property =="is_inverter")
+  else if (property == "is_clock_gate"
+           || property == "is_integrated_clock_gating_cell")
+    return PropertyValue(cell->isClockGate());
+  else if (property == "is_inverter")
     return PropertyValue(cell->isInverter());
-  else if (property == "is_memory")
+  else if (property == "is_memory" || property == "is_memory_cell")
     return PropertyValue(cell->isMemory());
   else if (property == "dont_use")
     return PropertyValue(cell->dontUse());
@@ -767,7 +776,18 @@ Properties::getProperty(const Port *port,
     return PropertyValue(network->direction(port)->name());
   else if (property == "liberty_port")
     return PropertyValue(network->libertyPort(port));
-
+  else if (property == "clocks") {
+    const Instance *top_inst = network->topInstance();
+    const Pin *pin = network->findPin(top_inst, port);
+    ClockSet clks = sta_->clocks(pin);
+    return PropertyValue(&clks);
+  }
+  else if (property == "clock_domains") {
+    const Instance *top_inst = network->topInstance();
+    const Pin *pin = network->findPin(top_inst, port);
+    ClockSet clk_domains = sta_->clockDomains(pin);
+    return PropertyValue(&clk_domains);
+  }
   else if (property == "activity") {
     const Instance *top_inst = network->topInstance();
     const Pin *pin = network->findPin(top_inst, port);
@@ -868,7 +888,8 @@ Properties::getProperty(const LibertyPort *port,
   else if (property == "direction"
 	   || property == "port_direction")
     return PropertyValue(port->direction()->name());
-  else if (property == "capacitance") {
+  else if (property == "capacitance"
+           || property == "pin_capacitance") {
     float cap = port->capacitance(RiseFall::rise(), MinMax::max());
     return capacitancePropertyValue(cap);
   }
@@ -960,7 +981,7 @@ Properties::getProperty(const Instance *inst,
     return PropertyValue(liberty_cell && liberty_cell->isInverter());
   else if (property == "is_macro")
     return PropertyValue(liberty_cell && liberty_cell->isMacro());
-  else if (property == "is_memory")
+  else if (property == "is_memory" || property == "is_memory_cell")
     return PropertyValue(liberty_cell && liberty_cell->isMemory());
   else {
     PropertyValue value = registry_instance_.getProperty(inst, property,
@@ -991,13 +1012,11 @@ Properties::getProperty(const Pin *pin,
     return PropertyValue(network->isHierarchical(pin));
   else if (property == "is_port")
     return PropertyValue(network->isTopLevelPort(pin));
+  else if (property == "is_register_clock")
+    return PropertyValue(network->isRegClkPin(pin));
   else if (property == "is_clock") {
-    const LibertyPort *port = network->libertyPort(pin);
-    return PropertyValue(port->isClock());
-  }
-  else if (property == "is_register_clock") {
-    const LibertyPort *port = network->libertyPort(pin);
-    return PropertyValue(port && port->isRegClk());
+    LibertyPort *liberty_port = network->libertyPort(pin);
+    return PropertyValue(liberty_port && liberty_port->isClock());
   }
   else if (property == "clocks") {
     ClockSet clks = sta_->clocks(pin);
@@ -1260,14 +1279,26 @@ Properties::getProperty(PathEnd *end,
     PathExpanded expanded(end->path(), sta_);
     return PropertyValue(expanded.startPath()->pin(sta_));
   }
-  else if (property == "startpoint_clock")
-    return PropertyValue(end->path()->clock(sta_));
+  else if (property == "startpoint_clock"){
+    const Clock *clk = end->path()->clock(sta_);
+    if (clk)
+      return PropertyValue(clk->name());
+    else
+      return PropertyValue();
+  }
   else if (property == "endpoint")
     return PropertyValue(end->path()->pin(sta_));
-  else if (property == "endpoint_clock")
-    return PropertyValue(end->targetClk(sta_));
+  else if (property == "endpoint_clock") {
+    const Clock *clk = end->targetClk(sta_);
+    if (clk)
+      return PropertyValue(clk->name());
+    else
+      return PropertyValue();
+  }
   else if (property == "endpoint_clock_pin")
     return PropertyValue(end->targetClkPath()->pin(sta_));
+  else if (property == "path_group")
+    return PropertyValue(sta_->search()->pathGroup(end)->name());
   else if (property == "slack")
     return PropertyValue(delayPropertyValue(end->slack(sta_)));
   else if (property == "points") {

test/get_property_flags.ok

@@ -0,0 +1,44 @@
+TEST 1
+get_clocks
+clk
+get_clocks 2
+vclk
+get_lib_cells
+asap7_small/BUFx2_ASAP7_75t_R
+get_lib_cells 2
+asap7_small/AND2x2_ASAP7_75t_R
+asap7_small/BUFx2_ASAP7_75t_R
+asap7_small/DFFHQx4_ASAP7_75t_R
+get_pins
+r1/CLK
+r1/D
+r2/CLK
+r2/D
+r3/CLK
+r3/D
+u1/A
+u2/A
+u2/B
+get_pins 2
+r1/Q
+r2/Q
+r3/Q
+u1/Y
+u2/Y
+get_ports
+clk1
+clk2
+clk3
+in1
+in2
+get_ports 2
+out
+TEST 2
+get_clocks
+get_clocks 2
+get_lib_cells
+get_lib_cells 2
+get_pins
+get_pins 2
+get_ports
+get_ports 2

test/get_property_flags.tcl

@@ -0,0 +1,44 @@
+# get_* -filter with property flags
+
+# Read in design and libraries
+read_liberty asap7_small.lib.gz
+read_verilog reg1_asap7.v
+link_design top
+create_clock -name clk -period 500 {clk1 clk2 clk3}
+create_clock -name vclk -period 1000
+
+puts "TEST 1"
+puts "get_clocks"
+report_object_full_names [get_clocks -filter is_virtual==0 *]
+puts "get_clocks 2"
+report_object_full_names [get_clocks -filter is_virtual==1 *]
+puts "get_lib_cells"
+report_object_full_names [get_lib_cells -filter is_buffer==1 *]
+puts "get_lib_cells 2"
+report_object_full_names [get_lib_cells -filter is_inverter==0 *]
+puts "get_pins"
+report_object_full_names [get_pins -filter direction==input *]
+puts "get_pins 2"
+report_object_full_names [get_pins -filter direction==output *]
+puts "get_ports"
+report_object_full_names [get_ports -filter direction==input *]
+puts "get_ports 2"
+report_object_full_names [get_ports -filter direction==output *]
+
+puts "TEST 2"
+puts "get_clocks"
+report_object_full_names [get_clocks -filter is_virtual==false *]
+puts "get_clocks 2"
+report_object_full_names [get_clocks -filter is_virtual==true *]
+puts "get_lib_cells"
+report_object_full_names [get_lib_cells -filter is_buffer==true *]
+puts "get_lib_cells 2"
+report_object_full_names [get_lib_cells -filter is_inverter==false *]
+puts "get_pins"
+report_object_full_names [get_pins -filter direction==in *]
+puts "get_pins 2"
+report_object_full_names [get_pins -filter direction==out *]
+puts "get_ports"
+report_object_full_names [get_ports -filter direction==in *]
+puts "get_ports 2"
+report_object_full_names [get_ports -filter direction==out *]

test/regression_vars.tcl

@@ -143,6 +143,7 @@ record_sta_tests {
   get_lib_pins_of_objects
   get_noargs
   get_objrefs
+  get_property_flags
   liberty_arcs_one2one_1
   liberty_arcs_one2one_2
   liberty_backslash_eol